CN104241094A - Machining method for preventing edge of ultra-thin silicon wafer from being broken - Google Patents
Machining method for preventing edge of ultra-thin silicon wafer from being broken Download PDFInfo
- Publication number
- CN104241094A CN104241094A CN201410312414.8A CN201410312414A CN104241094A CN 104241094 A CN104241094 A CN 104241094A CN 201410312414 A CN201410312414 A CN 201410312414A CN 104241094 A CN104241094 A CN 104241094A
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- China
- Prior art keywords
- silicon chip
- silicon wafer
- groove
- thinning
- diaphragm
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a machining method for preventing the edge of an ultra-thin silicon wafer from being broken. The method is characterized by comprising the following steps that first, a groove is machined in the edge of the silicon wafer needing to be thinned, and the groove opening of the groove is located in the surface of the silicon wafer; second, a protective film is attached to the surface, with the machined groove, of the silicon wafer, and the protective film is arranged across the groove, or the surface, with the machined groove, of the silicon wafer is attached to another silicon wafer; third, the back side of the silicon wafer is ground so that the silicon wafer can be thinned to a specified thickness; fourth, the protecting film on the surface of the silicon wafer is torn off, and the thinned silicon wafer meeting the requirement is obtained, or the thinned silicon wafer is separated from the other silicon wafer so that the thinned silicon wafer meeting the requirement can be obtained. Compared with the prior art, the machining method for preventing the edge of the ultra-thin silicon wafer from being broken has the advantages that machining is easy to carry out, film attachment can be easily carried out, and the subsequent machining technology of the silicon wafer is compatible with a traditional method.
Description
Technical field
The present invention relates to the processing technique field of silicon chip, particularly a kind of processing method avoiding ultra thin silicon wafers edge breakage.
Background technology
In wafer thinning technique, particularly in the ultra thin silicon wafers course of processing, silicon chip edge is very easy to break.Its reason be thinning after, silicon chip edge is very sharp, so especially easily damaged.
In order to prevent the edge break of silicon chip in the ultra thin silicon wafers course of processing, see Fig. 1 to Fig. 4, current method is the edge 13 (see Fig. 1 and 2) on the surface 3 of first grinding silicon chip 2, then adopt adhesive 24 to paste on the surface 26 of another block silicon chip 4 on the surface 3 of silicon chip 2 ground for marginal surface, the back side 5 finally grinding away silicon chip 3 obtains the silicon chip 2 of neat in edge.The method complex process, and be also a problem for silicon chip 2 film on surface after edge grinding.
Summary of the invention
Technical problem to be solved by this invention is for the problem existing for the above-mentioned processing method in order to prevent the edge break of silicon chip in the ultra thin silicon wafers course of processing from adopting and provides a kind of technique simply to avoid the processing method of ultra thin silicon wafers edge breakage.
Technical problem to be solved by this invention can be achieved through the following technical solutions:
Avoid a processing method for ultra thin silicon wafers edge breakage, specifically comprise the steps:
(1) process a groove at the thinning silicon chip edge of needs, the notch of described groove is positioned at the surface of silicon chip;
(2) paste a diaphragm on the surface of the silicon chip being processed with groove, described diaphragm strides across described groove; Or the surface being processed with the silicon chip of groove is attached on another silicon chip;
(3) reduction processing is carried out to described silicon chip in the back side of grinding described silicon chip, is thinned to specific thickness;
(4) tear the diaphragm of silicon chip surface off, obtain satisfactory thinning after silicon chip; Or the silicon chip after thinning is separated with another silicon chip obtain meeting thinning after silicon chip.
In a preferred embodiment of the invention, the degree of depth of described groove is greater than the thickness of thinning rear silicon chip, and when tearing the diaphragm of silicon chip surface off, the silicon chip edge outside described groove taken away by described diaphragm.
In a preferred embodiment of the invention, the degree of depth of described groove is less than the thickness of thinning rear silicon chip, tear off again after grinding away the silicon chip edge outside described groove silicon chip surface diaphragm or just thinning after silicon chip be separated with another silicon chip.
In a preferred embodiment of the invention, described groove adopts the one or any two or more Combined machining in laser cutting method, emery wheel cutting method, plasma etching method, chemicals wet etching method to form.
Owing to have employed technical scheme as above, the present invention compared with prior art, has the following advantages: 1, processing is simple; 2, pad pasting is easy to; 3 and the follow-up processing technology of silicon chip and traditional method compatible.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is existing silicon chip processing method schematic diagram.
Fig. 5 is the not thinning silicon chip structural representation that the present invention is processed with the degree of depth and is greater than the groove of the thickness of thinning rear silicon chip.
Fig. 6 is the schematic diagram after the present invention is processed with the not thinning silicon chip pad pasting of groove.
Fig. 7 is that the present invention is processed with groove and posts the schematic diagram of the thinning rear silicon chip of pad pasting.
Fig. 8 is finished silicon chip architecture structural representation of the present invention.
Fig. 9 is that the present invention is processed with the degree of depth and is less than the groove of the thickness of thinning rear silicon chip and posts the schematic diagram of the thinning rear silicon chip of pad pasting.
Embodiment
Avoid a processing method for ultra thin silicon wafers edge breakage, specifically comprise the steps:
(1) see Fig. 5, the groove 110 processing a degree of depth needing the edge of thinning silicon chip 100 and be greater than the thickness of thinning rear silicon chip, the notch of groove 110 is positioned at the surface 120 of silicon chip 100.
(2) see Fig. 6, a diaphragm 200 is pasted on the surface 120 of the silicon chip 100 being processed with groove 110, diaphragm 200 crossed slot 110;
(3) see Fig. 7,130 pairs, the back side silicon chip 100 of grinding silicon chip 100 carries out reduction processing, is thinned to specific thickness;
(4) tear the diaphragm 200 on silicon chip 100 surface off, when tearing the diaphragm 200 on silicon chip 100 surface off, the silicon chip edge 130 outside groove 110 taken away by diaphragm 200, obtain satisfactory thinning after silicon chip;
Above-mentioned steps (2) also can be adopted and be replaced with the following method: the surface 120 being processed with the silicon chip 100 of groove 110 is attached on another silicon chip.Above-mentioned steps (4) also can be adopted and be replaced with the following method: the silicon chip 100 after thinning is separated with another silicon chip obtain meeting thinning after silicon chip.
In addition see Fig. 9; the groove 110a that also can the edge of thinning silicon chip 100 needed to process a degree of depth be less than the thickness of thinning rear silicon chip; the notch of groove 110a is positioned at the surface 120 of silicon chip 100; a diaphragm 200 is pasted, diaphragm 200 crossed slot 110 on the surface 120 of the silicon chip 100 being processed with groove 110a.
Above-mentioned groove 110 or 100a adopt the one or any two or more Combined machining in laser cutting method, emery wheel cutting method, plasma etching method, chemicals wet etching method to form.
Claims (4)
1. avoid a processing method for ultra thin silicon wafers edge breakage, it is characterized in that, specifically comprise the steps:
(1) process a groove at the thinning silicon chip edge of needs, the notch of described groove is positioned at the surface of silicon chip;
(2) paste a diaphragm on the surface of the silicon chip being processed with groove, described diaphragm strides across described groove; Or the surface being processed with the silicon chip of groove is attached on another silicon chip;
(3) reduction processing is carried out to described silicon chip in the back side of grinding described silicon chip, is thinned to specific thickness;
(4) tear the diaphragm of silicon chip surface off, obtain satisfactory thinning after silicon chip; Or the silicon chip after thinning is separated with another silicon chip obtain meeting thinning after silicon chip.
2. avoid the processing method of ultra thin silicon wafers edge breakage as claimed in claim 1, it is characterized in that, the degree of depth of described groove is greater than the thickness of thinning rear silicon chip, and when tearing the diaphragm of silicon chip surface off, the silicon chip edge outside described groove taken away by described diaphragm.
3. avoid the processing method of ultra thin silicon wafers edge breakage as claimed in claim 1; it is characterized in that; the degree of depth of described groove is less than the thickness of thinning rear silicon chip, tear off again after grinding away the silicon chip edge outside described groove silicon chip surface diaphragm or just thinning after silicon chip be separated with another silicon chip.
4. avoid the processing method of ultra thin silicon wafers edge breakage as claimed in claim 1, it is characterized in that, described groove adopts the one or any two or more Combined machining in laser cutting method, emery wheel cutting method, plasma etching method, chemicals wet etching method to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312414.8A CN104241094A (en) | 2014-10-08 | 2014-10-08 | Machining method for preventing edge of ultra-thin silicon wafer from being broken |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312414.8A CN104241094A (en) | 2014-10-08 | 2014-10-08 | Machining method for preventing edge of ultra-thin silicon wafer from being broken |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104241094A true CN104241094A (en) | 2014-12-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410312414.8A Pending CN104241094A (en) | 2014-10-08 | 2014-10-08 | Machining method for preventing edge of ultra-thin silicon wafer from being broken |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10727128B2 (en) | 2018-02-14 | 2020-07-28 | Disco Corporation | Method of processing a wafer |
-
2014
- 2014-10-08 CN CN201410312414.8A patent/CN104241094A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10727128B2 (en) | 2018-02-14 | 2020-07-28 | Disco Corporation | Method of processing a wafer |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141224 |
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| RJ01 | Rejection of invention patent application after publication |