CN111900083B - IGBT wafer thinning method - Google Patents

IGBT wafer thinning method Download PDF

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Publication number
CN111900083B
CN111900083B CN202010618537.XA CN202010618537A CN111900083B CN 111900083 B CN111900083 B CN 111900083B CN 202010618537 A CN202010618537 A CN 202010618537A CN 111900083 B CN111900083 B CN 111900083B
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Prior art keywords
wafer
film
thinning
thickness
igbt
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CN111900083A (en
Inventor
郁新举
叶斐
朱伟杰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The application discloses a thinning method of an IGBT wafer, which comprises the following steps: attaching a first thin film to the front surface of the wafer integrated with the IGBT device; thinning the wafer to reduce the thickness of the wafer to a first target thickness; removing the first film, and attaching a second film to the front surface of the wafer; thinning the second film; thinning the wafer to a second target thickness; and removing the second film. According to the method and the device, the back face of the wafer and the film attached to the front face of the wafer are thinned in sequence before the back face of the wafer is ground to the required thickness in the process of manufacturing the IGBT wafer, so that the influence of the thickness of the wafer and the thickness of the film on the thinning process in the wafer grinding process is reduced, and the consistency of the thickness of the thinned wafer is improved.

Description

IGBT wafer thinning method
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for thinning an Insulated Gate Bipolar Transistor (IGBT) wafer.
Background
An IGBT device is a composite fully-controlled voltage-driven power semiconductor device composed of Bipolar Junction Transistor (BJT) devices and metal-oxide-semiconductor field-effect transistor (MOSFET) devices, has the advantages of high input impedance of MOSFET devices and low on-voltage of power transistor (GTR) devices, and is widely used in the fields of inverter systems (such as ac motors, frequency converters, switching power supplies, lighting circuits, traction drives, etc.) with dc voltages of 600 volts (V) or more.
In the related art, in the process of thinning the wafer integrated with the IGBT device, in order to reduce the influence of the stress of the front pattern on the back thinning process on the thinning process, a thin film is usually attached to the front surface of the wafer. Generally, the thinning process for the wafer integrated with the IGBT device is as follows: attaching a film to the front surface of the wafer; thinning the back of the wafer; and removing the film.
However, the thickness of the IGBT wafer thinned by the thinning method provided by the related art has poor consistency.
Disclosure of Invention
The application provides a thinning method of an IGBT wafer, which can solve the problem of poor thickness consistency caused by the thinning method of the IGBT wafer provided in the related technology.
On one hand, the embodiment of the application provides a thinning method of an IGBT wafer, which comprises the following steps:
attaching a first film to the front surface of a wafer integrated with an IGBT device, wherein the front surface is the surface of a graph of the IGBT device formed by the wafer;
thinning the wafer to enable the thickness of the wafer to be reduced to a first target thickness;
removing the first film, and attaching a second film to the front surface of the wafer;
thinning the second film;
thinning the wafer to a second target thickness;
and removing the second film.
Optionally, the first film and the second film are blue films.
Optionally, the first target thickness is 400 micrometers (μm) to 700 micrometers.
Optionally, after the second film is thinned, the sum of the thicknesses of the second film and the wafer is 400 to 800 micrometers.
Optionally, the second target thickness is 40 to 400 microns.
Optionally, the thinning the wafer includes:
and grinding the wafer by a Back Grinding (BG) process, and thinning the wafer.
Optionally, the thinning the second film includes:
and scraping and thinning the surface of the second film by a diamond grinding disc.
The technical scheme at least comprises the following advantages:
in the process of manufacturing the wafer integrated with the IGBT device, the back face of the wafer and the film attached to the front face of the wafer are thinned in sequence before the back face of the wafer is ground to the required thickness, so that the influence of the thickness of the wafer and the thickness of the film on the thinning process in the wafer grinding process is reduced, and the consistency of the thickness of the thinned wafer is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a thinning method of an IGBT wafer according to an exemplary embodiment of the present application;
fig. 2 to 8 are schematic diagrams of a thinning process of an IGBT wafer according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
In the related art, the thinning process of the wafer integrated with the IGBT device comprises the following steps: attaching a film to the front surface of the wafer; thinning the back of the wafer; and removing the film. However, due to the thickness of the wafer itself and the influence of the film thickness on the thinning process, the thickness of the IGBT wafer thinned by the thinning method provided in the related art has poor consistency, for example, the requirement for the deviation of the wafer thickness is ± 3 microns, while the deviation of the wafer thickness thinned by the thinning method provided in the related art is ± 10 microns.
Referring to fig. 1, a flowchart of a thinning method of an IGBT wafer according to an exemplary embodiment of the present application is shown, where the method is applicable to manufacturing an IGBT device, and the method includes:
step 101, attaching a first thin film on the front surface of a wafer integrated with an IGBT device.
Referring to fig. 2, a cross-sectional view of a first film attached to the front side of an IGBT wafer is shown. As shown in fig. 2, the front surface of the wafer 110 is a surface on which a pattern 111 of the IGBT device is formed, and the thickness of the wafer 110 is h 1. Optionally, the first film 121 is a blue film.
Optionally, the pattern 111 includes a metal line, an interlayer dielectric formed on the metal line, and a passivation layer formed on the interlayer dielectric for reducing the stress action of the pattern 111. Illustratively, the passivation layer may be polyimide.
And 102, thinning the wafer to a first target thickness.
Referring to fig. 3, a cross-sectional view of a thinned wafer is shown. For example, as shown in fig. 3, after the wafer 110 is turned over, the back surface (i.e., the other surface of the wafer 110 opposite to the front surface) of the wafer 110 is polished by using a polishing disk to thin the wafer 110.
Optionally, the first target thickness h2 is 400 to 700 microns. After the thickness of the wafer 110 is thinned to the first target thickness through the thinning process, the influence of the thickness of the wafer 110 on the subsequent thinning process can be reduced.
Step 103, removing the first film and attaching a second film on the front surface of the wafer.
Referring to FIG. 4, a schematic cross-sectional view is shown after removal of the first film; referring to fig. 5, a cross-sectional view of attaching a second film to the front surface of the wafer is shown. As shown in fig. 4 and 5, the silicon dust on the front surface of the wafer 110 can be removed by removing the first film 121, and the second film 122 can be a blue film with a thickness H1.
And step 104, thinning the second film.
Referring to fig. 6, a schematic cross-sectional view of the thinning of the second film is shown. Illustratively, as shown in fig. 6, the surface of the second film 122 may be thinned by scraping with a diamond grinding disc, and the thickness of the thinned second film 122 is H2. By thinning the second film 122, the influence of the thickness of the second film 122 on the subsequent thinning process can be reduced.
Optionally, after the second film 122 is thinned, the sum of the thickness H2 of the second film 122 and the thickness H2 of the wafer 110 (H2+ H2) is 400 micrometers to 800 micrometers. By controlling the sum of the thicknesses of the second thin film 122 and the wafer 110 to be in the range of 400 micrometers to 800 micrometers, the influence of the thicknesses of the second thin film 122 and the wafer 110 on the subsequent thinning process can be reduced.
And 105, thinning the wafer to a second target thickness.
Referring to fig. 7, a cross-sectional view of a thinned wafer is shown. For example, as shown in fig. 7, after the wafer 110 is turned over, the back surface of the wafer 110 is ground by using a grinding disc, and the wafer 110 is thinned to the second target thickness h 3. The second target thickness h3 can be set as desired, and can typically range from 40 microns to 400 microns.
And 106, removing the second film.
Referring to fig. 8, a schematic cross-sectional view is shown after removal of the second film. Silicon dust on the front surface of the wafer 110 may be removed by removing the second film 122.
To sum up, in the embodiment of the application, through in-process of making to the wafer that integrates the IGBT device, grind to the back of wafer to the thickness that needs before, carry out the attenuate to the back of wafer and attached film openly at the wafer in proper order to reduced the influence of the thickness of wafer and film to the attenuate technology in the wafer process of grinding, thereby improved the uniformity of the thickness of the wafer after the attenuate.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (4)

1. A thinning method of an IGBT wafer is characterized by comprising the following steps:
attaching a first thin film to the front surface of a wafer integrated with an IGBT device, wherein the front surface is the surface of the wafer forming the graph of the IGBT device;
thinning the wafer to a first target thickness, wherein the first target thickness is 400-700 microns;
removing the first film, and attaching a second film to the front surface of the wafer;
thinning the second film, wherein after the second film is thinned, the sum of the thicknesses of the second film and the wafer is 400-800 micrometers;
thinning the wafer to a second target thickness, wherein the second target thickness is 40-400 microns;
and removing the second film.
2. The method of claim 1, wherein the first and second films are blue films.
3. The method of claim 1 or 2, wherein thinning the wafer comprises:
and grinding the wafer by a BG process, and thinning the wafer.
4. The method of claim 1 or 2, wherein said thinning of said second film comprises:
and scraping and thinning the surface of the second film by a diamond grinding disc.
CN202010618537.XA 2020-07-01 2020-07-01 IGBT wafer thinning method Active CN111900083B (en)

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JP2005303214A (en) * 2004-04-16 2005-10-27 Matsushita Electric Ind Co Ltd Grinding method for semiconductor wafer
EP1868231A1 (en) * 2005-04-04 2007-12-19 Shin-Etsu Handotai Co., Ltd Bonded wafer manufacturing method, bonded wafer, and plane polishing apparatus
CN105742173A (en) * 2016-03-02 2016-07-06 上海朕芯微电子科技有限公司 Processing method for ultra-thin wafer
CN106229285A (en) * 2016-08-01 2016-12-14 上海华虹宏力半导体制造有限公司 The method improving IGBT back side stress
CN106486408A (en) * 2015-08-31 2017-03-08 株式会社迪思科 The method processing chip
JP2017157749A (en) * 2016-03-03 2017-09-07 株式会社ディスコ Processing method of wafer
CN108269741A (en) * 2018-01-11 2018-07-10 上海华虹宏力半导体制造有限公司 Wafer grinding method
CN111232918A (en) * 2020-04-27 2020-06-05 中芯集成电路制造(绍兴)有限公司 Semiconductor device and method for manufacturing the same
CN111276542A (en) * 2020-02-17 2020-06-12 中芯集成电路制造(绍兴)有限公司 Groove type MOS device and manufacturing method thereof

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JP2008182015A (en) * 2007-01-24 2008-08-07 Disco Abrasive Syst Ltd Method for grinding wafer
KR20080074602A (en) * 2007-02-09 2008-08-13 주식회사 엘에스 Multifunctional backgrinding tape with the function of die adhesive film or underfill and semiconductor packaging method using the same
JP5599342B2 (en) * 2011-02-23 2014-10-01 三菱電機株式会社 Manufacturing method of semiconductor device
CN108257851A (en) * 2018-01-11 2018-07-06 上海华虹宏力半导体制造有限公司 Wafer grinding method
CN109461647A (en) * 2018-11-16 2019-03-12 德淮半导体有限公司 The manufacturing method of semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303214A (en) * 2004-04-16 2005-10-27 Matsushita Electric Ind Co Ltd Grinding method for semiconductor wafer
EP1868231A1 (en) * 2005-04-04 2007-12-19 Shin-Etsu Handotai Co., Ltd Bonded wafer manufacturing method, bonded wafer, and plane polishing apparatus
CN106486408A (en) * 2015-08-31 2017-03-08 株式会社迪思科 The method processing chip
CN105742173A (en) * 2016-03-02 2016-07-06 上海朕芯微电子科技有限公司 Processing method for ultra-thin wafer
JP2017157749A (en) * 2016-03-03 2017-09-07 株式会社ディスコ Processing method of wafer
CN106229285A (en) * 2016-08-01 2016-12-14 上海华虹宏力半导体制造有限公司 The method improving IGBT back side stress
CN108269741A (en) * 2018-01-11 2018-07-10 上海华虹宏力半导体制造有限公司 Wafer grinding method
CN111276542A (en) * 2020-02-17 2020-06-12 中芯集成电路制造(绍兴)有限公司 Groove type MOS device and manufacturing method thereof
CN111232918A (en) * 2020-04-27 2020-06-05 中芯集成电路制造(绍兴)有限公司 Semiconductor device and method for manufacturing the same

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