CN114093815A - IGBT wafer processing technology with back bonded with glass carrier plate - Google Patents
IGBT wafer processing technology with back bonded with glass carrier plate Download PDFInfo
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- CN114093815A CN114093815A CN202111341009.5A CN202111341009A CN114093815A CN 114093815 A CN114093815 A CN 114093815A CN 202111341009 A CN202111341009 A CN 202111341009A CN 114093815 A CN114093815 A CN 114093815A
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- 239000011521 glass Substances 0.000 title claims abstract description 24
- 238000005516 engineering process Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000005520 cutting process Methods 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000004642 Polyimide Substances 0.000 claims abstract description 22
- 229920001721 polyimide Polymers 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 239000000853 adhesive Substances 0.000 claims abstract description 5
- 230000001070 adhesive effect Effects 0.000 claims abstract description 5
- 238000000227 grinding Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000005496 tempering Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000000465 moulding Methods 0.000 description 10
- 239000002390 adhesive tape Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009347 mechanical transmission Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
- Laser Beam Processing (AREA)
Abstract
The invention discloses a processing technology of an IGBT wafer with a back bonded glass carrier plate, which comprises the following steps: s1, completing the process before the metal process on the front surface of the wafer; s2, etching the back of the wafer to form a gentle slope; s3, completing the back process of the wafer; s4, coating polyimide on the back surface, and bonding the glass carrier plate; s5, manufacturing a front metal process; s6, coating polyimide on the front surface, and exposing the cutting path after developing, curing and etching; s7, cutting is completed through etching and laser, and polyimide on the front side is removed; s8, attaching the glass carrier plate to the cutting die frame, debonding the glass carrier plate, and removing the adhesive; s9, removing the polyimide on the back surface to separate the crystal grains. The wafer back side is processed in a gentle slope mode, stress support can be provided at the edge, the limit of back side tempering temperature is overcome, meanwhile, polyimide is coated on the back side of the wafer and is bonded with the glass carrier plate, metal thick film stress can be buffered, and the thin wafer is prevented from being warped and damaged after thick metal coating.
Description
Technical Field
The invention relates to the field of semiconductor processing, in particular to a processing technology of an IGBT wafer with a back bonded glass carrier plate.
Background
The IGBT is a compound fully-controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), and has the advantages of both high input impedance of MOSFET (metal-oxide semiconductor field effect transistor) and low on-state voltage drop of GTR (power transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
The existing IGBT wafer production process is that the front process of a wafer is finished firstly, then a glass carrier plate is bonded on the front, then the back is thinned, and the subsequent wafer back process is finished, but because the back process has a high temperature step, the adhesive is a high molecular material and can only bear the heating process of 350 ℃, the front is finished with the metal process, AI or Cu can bear the heating process of 560 ℃ at most, the process cannot be implemented on the wafer bonded with the glass carrier plate, but the wafer after bonding is easy to break and damage.
Disclosure of Invention
In order to solve the defects mentioned in the background art, the invention aims to provide a process for processing an IGBT wafer with a back-bonded glass carrier plate, the back of the wafer is processed in a gentle slope manner, the edge of the thinned wafer is provided with stress support, so that the wafer cannot be broken or the edge is not locally cracked, the limitation of back tempering temperature is overcome, meanwhile, the back of the wafer is coated with polyimide and then bonded with the glass carrier plate, the stress generated in the processes of front metal thick film plating and electroplating and chemical plating can be buffered, and the back polyimide is removed after bonding is released, so that the thin wafer cannot be warped and damaged after thick metal coating.
The purpose of the invention can be realized by the following technical scheme:
a processing technology of an IGBT wafer with a back bonded glass carrier plate comprises the following steps:
s1, completing the process before the metal process on the front surface of the wafer;
s2, adhering a grinding adhesive tape to the front surface of the wafer, forming a gentle slope or step-shaped wafer structure on the edge of the back surface of the wafer, and removing the grinding adhesive tape;
s3, removing the grinding tape to complete the back process of the wafer;
s4, coating polyimide on the gentle slope of the back of the wafer to level the back, and then bonding the back of the wafer on the glass carrier plate;
s5, turning over the wafer front surface to make front metal process;
s6, coating polyimide on the front surface of the wafer, and exposing the cutting channels after developing, curing and etching;
s7, etching the cutting channel to the back metal layer by plasma, cutting the back metal by laser, and removing the polyimide on the front side;
s8, overturning the cut wafer to enable the front surface to be attached to the first cutting die frame, releasing the glass carrier plate on the back surface of the wafer through laser de-bonding, and removing the adhesive;
s9, removing the polyimide on the back gentle slope by oxygen plasma;
and S10, removing the peripheral annular gently-sloping edges, attaching the back of the wafer to the second cutting die frame, turning the first cutting die frame, the wafer and the second cutting die frame integrally, removing the viscosity of the first cutting die frame through ultraviolet irradiation, and taking down the first cutting die frame.
Further preferably, the processes before the front metal process in step S1 include trench, ILD and contact hole processes.
Preferably, in step S2, a wafer structure with a gentle slope or a step is formed on the edge of the back side of the wafer by polishing and etching with an edge gas ring or a protective solution, and the thickness of the thinned wafer is 40-150 um.
Further preferably, the back metal process in step S3 includes photolithography, ion implantation, annealing, and a back metal process.
The invention has the beneficial effects that:
the back of the wafer is processed in a gentle slope way, although the wafer is an ultrathin wafer, the edge can still contact with the contact point or the edge of a mechanical transmission arm of heating and metal related process equipment, so that the wafer cannot be broken or the edge is locally cracked, and the limit of the back tempering temperature is overcome; according to the invention, the polyimide is coated on the back of the wafer and then bonded with the glass carrier plate, so that the stress generated in the processes of metal thick film on the front side and electroplating and chemical plating can be buffered, and the polyimide on the back side is removed after bonding is released, so that the thin wafer can be prevented from warping and damaging after the thick metal film is coated; the invention can automatically align the front surface by exposing the cutting channel after the front surface is coated with polyimide and then developed, cured and etched, and the back surface metal is cut off by laser after the cutting channel is etched, thereby overcoming the problem that the back surface of the traditional wafer is not easy to align.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic molding diagram of step S1 of the process of the present invention;
FIG. 2 is a schematic molding diagram of step S2 of the process of the present invention;
FIG. 3 is a schematic molding diagram of step S3 of the present invention;
FIG. 4 is a schematic molding diagram of step S4 of the present invention;
FIG. 5 is a schematic molding diagram of step S5 of the present invention;
FIG. 6 is a schematic molding diagram of step S6 of the present invention;
FIG. 7 is a schematic molding diagram of step S7 of the present invention;
FIG. 8 is a schematic molding diagram of step S8 of the present invention;
FIG. 9 is a schematic molding diagram of step S9 of the present invention;
fig. 10 is a schematic molding diagram of process step S10 according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 10, a process for processing an IGBT wafer with a back-bonded glass carrier includes the following steps:
s1, completing the processes before the wafer front metal process, including trench, ILD and contact hole processes;
s2, adhering a grinding adhesive tape to the front surface of the wafer, and forming a gentle slope or step-shaped wafer structure on the edge of the back surface of the wafer by grinding and etching the edge gas ring or the protective solution, wherein the thickness of the thinned wafer is 40-150 um;
s3, removing the grinding tape to complete the back process of the wafer, including the processes of photoetching, ion implantation, tempering and back metal;
s4, coating polyimide on the gentle slope of the back of the wafer to level the back, and then bonding the back of the wafer on the glass carrier plate;
s5, turning over the wafer front surface to make front metal process;
s6, coating polyimide on the front surface of the wafer, and exposing the cutting channels after developing, curing and etching;
s7, etching the cutting channel to the back metal layer by plasma, cutting the back metal by laser, and removing the polyimide on the front side;
s8, overturning the cut wafer to enable the front surface to be attached to the first cutting die frame, releasing the glass carrier plate on the back surface of the wafer through laser de-bonding, and removing the adhesive;
s9, removing the polyimide on the back gentle slope by oxygen plasma;
and S10, removing the peripheral annular gently-sloping edges, attaching the back of the wafer to the second cutting die frame, turning the first cutting die frame, the wafer and the second cutting die frame integrally, removing the viscosity of the first cutting die frame through ultraviolet irradiation, and taking down the first cutting die frame.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (4)
1. The IGBT wafer processing technology of the back bonding glass carrier plate is characterized by comprising the following steps:
s1, completing the process before the metal process on the front surface of the wafer;
s2, adhering a grinding tape on the front surface of the wafer, and etching the back surface of the wafer to form a gentle slope-shaped wafer structure on the edge;
s3, removing the grinding tape to complete the back process of the wafer;
s4, coating polyimide on the gentle slope of the back of the wafer to level the back, and then bonding the back of the wafer on the glass carrier plate;
s5, turning over the wafer front surface to make front metal process;
s6, coating polyimide on the front surface of the wafer, and exposing the cutting channels after developing, curing and etching;
s7, etching the cutting channel to the back metal layer by plasma, cutting the back metal by laser, and removing the polyimide on the front side;
s8, overturning the cut wafer to enable the front surface to be attached to the first cutting die frame, releasing the glass carrier plate on the back surface of the wafer through laser de-bonding, and removing the adhesive;
s9, removing the polyimide on the back gentle slope by oxygen plasma;
and S10, removing the peripheral annular gently-sloping edges, attaching the back of the wafer to the second cutting die frame, turning the first cutting die frame, the wafer and the second cutting die frame integrally, removing the viscosity of the first cutting die frame through ultraviolet irradiation, and taking down the first cutting die frame.
2. The process for processing the IGBT wafer of the back-bonded glass carrier plate according to claim 1, wherein the processes before the front metal process comprise trench, ILD and contact hole processes.
3. The process of claim 1, wherein in step S2, a wafer structure with a gentle slope is formed at the edge of the back of the wafer by grinding and etching with an edge gas ring or a protective solution, and the thickness of the wafer after thinning is 40-150 μm.
4. The process for processing the IGBT wafer with the back-bonded glass carrier plate according to claim 1, wherein the back metal process comprises photolithography, ion implantation, annealing and back metal process.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111341009.5A CN114093815B (en) | 2021-11-12 | 2021-11-12 | IGBT wafer processing technology for back bonding glass carrier plate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111341009.5A CN114093815B (en) | 2021-11-12 | 2021-11-12 | IGBT wafer processing technology for back bonding glass carrier plate |
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| CN114093815A true CN114093815A (en) | 2022-02-25 |
| CN114093815B CN114093815B (en) | 2024-10-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118098933A (en) * | 2024-04-25 | 2024-05-28 | 汉轩微电子制造(江苏)有限公司 | Wafer back surface metallization method and wafer |
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|---|---|---|---|---|
| JP2008028325A (en) * | 2006-07-25 | 2008-02-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2009212440A (en) * | 2008-03-06 | 2009-09-17 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device and semiconductor manufacturing apparatus |
| CN107851561A (en) * | 2015-04-27 | 2018-03-27 | 胜高股份有限公司 | Pedestal and epitaxial growth device |
| CN111799178A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Double-sided copper-plating thick film process for ultrathin wafer |
| CN112234018A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Ultrathin large-area tin ball printing process adopting polyimide |
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2021
- 2021-11-12 CN CN202111341009.5A patent/CN114093815B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008028325A (en) * | 2006-07-25 | 2008-02-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2009212440A (en) * | 2008-03-06 | 2009-09-17 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device and semiconductor manufacturing apparatus |
| CN107851561A (en) * | 2015-04-27 | 2018-03-27 | 胜高股份有限公司 | Pedestal and epitaxial growth device |
| CN111799178A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Double-sided copper-plating thick film process for ultrathin wafer |
| CN112234018A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Ultrathin large-area tin ball printing process adopting polyimide |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118098933A (en) * | 2024-04-25 | 2024-05-28 | 汉轩微电子制造(江苏)有限公司 | Wafer back surface metallization method and wafer |
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