CN115483146A - IGBT wafer processing technology - Google Patents
IGBT wafer processing technology Download PDFInfo
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- CN115483146A CN115483146A CN202211082867.7A CN202211082867A CN115483146A CN 115483146 A CN115483146 A CN 115483146A CN 202211082867 A CN202211082867 A CN 202211082867A CN 115483146 A CN115483146 A CN 115483146A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention relates to the technical field of semiconductor processing, in particular to an IGBT wafer processing technology, which comprises S1, a technology before metal processing on the front surface of a wafer is finished; s2, thinning the back of the wafer; s3, etching the back of the wafer to form a gentle slope; s4, completing the back process of the wafer; s5, coating polyimide on the back surface, and bonding the glass carrier plate; s6, completing the front process of the wafer; s7, cutting is completed through etching and laser, and polyimide on the front side is removed; s8, cutting the edge of the wafer; s9, attaching the cut wafer to a first cutting die frame, and washing off polyimide on the back surface; the wafer back side is processed in a gentle slope mode to provide stress support at the edge, and meanwhile polyimide is coated on the wafer back side and is bonded with the glass carrier plate, so that the stress of the metal thick film can be buffered, and the thin wafer is prevented from being warped and damaged after the thick metal film is plated.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to an IGBT wafer processing technology.
Background
The IGBT is a compound fully-controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), and has the advantages of both high input impedance of MOSFET (metal-oxide semiconductor field effect transistor) and low on-state voltage drop of GTR (power transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
The existing IGBT wafer production process is that the front process of a wafer is finished firstly, then a glass carrier plate is bonded on the front, then the back is thinned, and the subsequent wafer back process is finished, but because the back process has a high temperature step, the adhesive is a high molecular material and can only bear the heating process of 350 ℃, the front is finished with the metal process, AI or Cu can bear the heating process of 560 ℃ at most, the process cannot be implemented on the wafer bonded with the glass carrier plate, but the wafer after bonding is easy to break and damage.
Disclosure of Invention
The invention aims to provide an IGBT wafer processing technology to solve the problems in the background technology.
The purpose of the invention can be realized by the following technical scheme:
an IGBT wafer processing technology comprises the following steps:
s1, completing the process before the metal processing of the front surface of the wafer;
s2, adhering a grinding adhesive tape to the front surface of the wafer, thinning the back surface of the wafer, removing the grinding adhesive tape, and adsorbing the front surface of the wafer on a first glass carrying disc with adsorption holes;
s3, edge sealing is carried out on the side wall of the wafer, then etching is carried out on the center of the front face of the wafer, and the edge of the wafer is made to form a gentle slope shape;
s4, completing the back process of the wafer;
s5, coating polyimide on the back surface of the wafer to level the back surface, adsorbing the back surface of the wafer on a second glass carrying disc with adsorption holes, cutting off the edge sealing of the wafer through laser, and removing the first glass carrying disc and the edge sealing of the cut wafer;
s6, turning over to the front side of the wafer, coating polyimide on the front side of the wafer, and exposing the PAD growth gap and the cutting channel after developing, curing and etching;
s7, firstly, manufacturing a front metal PAD process, then etching a cutting channel to the back metal layer through plasma, and cutting off the back metal through laser;
s8, coating a light resistance on the edge of the front face of the wafer, washing off polyimide at the center of the front face of the wafer, and then cutting the edge of the wafer through laser;
and S9, turning over the cut wafer to enable the front surface to be attached to the cutting die frame, removing the second glass carrying disc and the cut wafer together, and washing off polyimide on the back surface of the wafer.
Further, the processes before the front metal process in S1 include trench, ILD and contact hole processes.
Further, the edge sealing in S3 adopts an SOG technique, a CVD technique, or a carbon deposition technique.
Further, the carbon deposition technique specifically includes:
s3.1, adopting carbon deposition reaction to attach a carbon deposition layer to the back of the wafer, and bonding the front of the wafer on a first glass carrying disc;
and S3.2, coating photoresist at the edge of the back surface of the wafer, and etching carbon on the back surface of the wafer by using laser.
Furthermore, the back metal process includes photolithography, ion implantation, back metal and annealing.
The invention has the beneficial effects that:
1. the edge of the back of the wafer is sealed by the edge sealing technology, then gentle slope processing is carried out, then cutting can be carried out through laser, the edge of the wafer is directly cut off, the wafer is convenient to take out, meanwhile, although the wafer is ultrathin, the edge can still contact with a contact point or an edge of a mechanical transmission arm of heating and metal related process equipment, so that the wafer cannot be broken or the edge is not locally cracked, and meanwhile, the limitation of the back tempering temperature is overcome;
2. the back of the wafer is coated with polyimide and then bonded with the glass carrier plate, the bonding part of the back is mainly the edge part of the wafer, the front metal thick film and the stress generated in the processes of electroplating and chemical plating can be buffered, then the edge of the wafer is directly cut off by cutting, the separation of the wafer and the carrier disc is convenient, and the back polyimide is removed, so that the thin wafer can be prevented from warping and damaging after the thick metal film is coated;
3. the invention can automatically align the front side by exposing the cutting channel after the front side is coated with polyimide and then developed, cured and etched, and the back side metal is cut off by laser after the cutting channel is etched, thereby overcoming the problem that the back side of the traditional wafer is not easy to align when being cut.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without creative efforts;
FIG. 1 is a schematic diagram of the formation of step S1 of the process of the present invention;
FIG. 2 is a schematic view of the forming of step S2 of the process of the present invention;
FIG. 3 is a schematic view of the process of step S3 of the present invention;
FIG. 4 is a schematic diagram of the formation of process step S4 of the present invention;
FIG. 5 is a schematic view of the process of step S5 of the present invention;
FIG. 6 is a schematic view of the forming of step S6 of the process of the present invention;
FIG. 7 is a schematic diagram of the formation of process step S7 of the present invention;
FIG. 8 is a schematic forming diagram of process step S8 of the present invention;
FIG. 9 is a schematic diagram of the forming process of step S9 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 9, an IGBT wafer processing process includes the following steps:
s1, completing processes before a wafer front metal process, including a groove process, an ILD process and a contact hole process;
s2, adhering a grinding adhesive tape to the front surface of the wafer, thinning the back surface of the wafer, removing the grinding adhesive tape, and adsorbing the front surface of the wafer on a first glass carrying disc which can be provided with adsorption holes so as to fix the wafer;
s3, edge sealing is carried out on the side wall of the wafer, then etching is carried out on the center of the front face of the wafer, and the edge of the wafer is made to be in a gentle slope shape;
the edge sealing technology mainly comprises an SOG technology, a CVD technology, a carbon deposition technology and the like.
Wherein if the carbon deposition technology is adopted, the method specifically comprises the following steps:
s3.1, adopting carbon deposition reaction to attach a carbon deposition layer to the back of the wafer, and bonding the front of the wafer on a first glass carrying disc;
and S3.2, coating photoresist at the edge of the back surface of the wafer, and etching carbon on the back surface of the wafer by using laser.
S4, completing wafer back surface processes including photoetching, ion implantation, back surface metal and tempering;
the edge of the back of the wafer is sealed through the edge sealing technology, then gentle slope processing is carried out, then cutting can be carried out through laser, the edge of the wafer is directly cut off, the wafer is convenient to take out, meanwhile, although the wafer is ultrathin, the edge can still contact with a contact point or an edge of a mechanical transmission arm of heating and metal related process equipment, the wafer cannot be broken or the edge cannot be locally cracked, and meanwhile, the limitation of the back tempering temperature is overcome.
S5, coating polyimide on the back surface of the wafer to level the back surface, adsorbing the back surface of the wafer on a second glass carrying disc with adsorption holes, cutting off the edge sealing of the wafer through laser, and removing the first glass carrying disc and the edge sealing of the cut wafer;
s6, turning over to the front side of the wafer, coating polyimide on the front side of the wafer, and exposing the PAD growth gap and the cutting channel after developing, curing and etching;
s7, firstly, manufacturing a front metal PAD process, then etching a cutting channel to the back metal layer through plasma, and cutting off the back metal through laser;
the front metal PAD process is completed in the growth gap firstly by exposing the PAD growth gap and the cutting channel after the front is coated with polyimide and then developing, curing and etching; the cutting channels can be automatically aligned on the front side, the back metal is cut off by laser after the cutting channels are etched, and the problem that the back of the traditional wafer is not easy to align in cutting is solved.
S8, coating a light resistance on the edge of the front face of the wafer, washing off polyimide at the center of the front face of the wafer, and then cutting the edge of the wafer through laser;
the back of the wafer is coated with polyimide and then is bonded with the glass carrier plate, the bonding part is mainly the edge part of the wafer, the stress generated in the processes of front metal thick film and electroplating and chemical plating can be buffered, then the edge of the wafer is directly cut off by cutting, the separation of the wafer and the carrier plate is convenient, and the back polyimide is removed, so that the thin wafer can be prevented from being warped and damaged after the thick metal coating.
And S9, overturning the cut wafer to enable the front surface of the wafer to be attached to the cutting die frame, removing the second glass carrying disc together with the cut wafer, and washing off polyimide on the back surface of the wafer.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. The IGBT wafer processing technology is characterized by comprising the following steps:
s1, completing a process before a front metal process of a wafer;
s2, adhering a grinding adhesive tape to the front surface of the wafer, thinning the back surface of the wafer, removing the grinding adhesive tape, and adsorbing the front surface of the wafer on a first glass carrying disc with adsorption holes;
s3, edge sealing is carried out on the side wall of the wafer, then etching is carried out on the center of the front face of the wafer, and the edge of the wafer is made to form a gentle slope shape;
s4, completing the back process of the wafer;
s5, coating polyimide on the back surface of the wafer to level the back surface, adsorbing the back surface of the wafer on a second glass carrying disc with adsorption holes, cutting off the edge sealing of the wafer through laser, and removing the first glass carrying disc and the edge sealing of the cut wafer;
s6, turning over to the front side of the wafer, coating polyimide on the front side of the wafer, and exposing the PAD growth gap and the cutting channel after developing, curing and etching;
s7, firstly, manufacturing a front metal PAD process, then etching a cutting channel to the back metal layer through plasma, and cutting off the back metal through laser;
s8, coating a light resistance on the edge of the front face of the wafer, washing off polyimide at the center of the front face of the wafer, and then cutting the edge of the wafer through laser;
and S9, overturning the cut wafer to enable the front surface of the wafer to be attached to the cutting die frame, removing the second glass carrying disc together with the cut wafer, and washing off polyimide on the back surface of the wafer.
2. The IGBT wafer processing technology of claim 1, wherein the processes before the front metal process in S1 comprise trench, ILD and contact hole processes.
3. The IGBT wafer processing technology of claim 1, wherein the edge sealing in S3 adopts SOG technology, CVD technology or carbon deposition technology.
4. The IGBT wafer processing technology of claim 3, wherein the carbon deposition technique specifically comprises:
s3.1, adopting carbon deposition reaction to attach a carbon deposition layer to the back of the wafer, and bonding the front of the wafer on a first glass carrying disc;
and S3.2, coating photoresist at the edge of the back surface of the wafer, and etching carbon on the back surface of the wafer by using laser.
5. The IGBT wafer processing process according to claim 1, wherein the back side metal process comprises photolithography, ion implantation, back side metal and annealing processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211082867.7A CN115483146A (en) | 2022-09-06 | 2022-09-06 | IGBT wafer processing technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211082867.7A CN115483146A (en) | 2022-09-06 | 2022-09-06 | IGBT wafer processing technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115483146A true CN115483146A (en) | 2022-12-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211082867.7A Pending CN115483146A (en) | 2022-09-06 | 2022-09-06 | IGBT wafer processing technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115483146A (en) |
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- 2022-09-06 CN CN202211082867.7A patent/CN115483146A/en active Pending
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