CN105721136A - Y-power-containing Lorenz type hyperchaotic system circuit based on memristor - Google Patents
Y-power-containing Lorenz type hyperchaotic system circuit based on memristor Download PDFInfo
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- CN105721136A CN105721136A CN201610089203.1A CN201610089203A CN105721136A CN 105721136 A CN105721136 A CN 105721136A CN 201610089203 A CN201610089203 A CN 201610089203A CN 105721136 A CN105721136 A CN 105721136A
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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Abstract
The invention relates to a y-power-containing Lorenz type hyperchaotic system circuit based on a memristor. An operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a resistor and a capacitor are utilized to achieve addition, anti-phase and integration operation; a multiplier U4 and a multiplier U5 are utilized to achieve multiplication operation in the system; an operational amplifier U6, a multiplier U7 and a multiplier U8 are utilized to achieve a memristor model in the invention; the operational amplifier U1 is connected with the operational amplifier U2, the operational amplifier U6, the multiplier U4, the multiplier U5 and the multiplier U8; the operational amplifier U2 is connected with the operational amplifier U3 and the multiplier U4; the operational amplifier U3 is connected with the multiplier U5; the operational amplifier U6 is connected with the multiplier U7 and the multiplier U8; and the multiplier U7 is connected with the multiplier U8. Based on the y-power-containing Lorenz type hyperchaotic system, the memristor element is utilized to increase one dimension to form a four-dimensional hyperchaotic system, thus a new method for applying the memristor to the hyperchaotic system is provided.
Description
Technical field
The present invention relates to a kind of chaos system and circuit realiration, particularly to a kind of Lorenz type hyperchaotic system circuit containing y side based on memristor.
Background technology
Currently, construct the method for four dimension ultra-chaos mainly on the basis of three-dimensional chaotic system, increase the four-dimensional hyperchaotic system of one-dimensional composition, memristor was as the newfound physical component in HP Lab in 2008, can substitute for the Cai Shi diode in cai's circuit and constitute four dimensional chaos system, cai's circuit to constitute hyperchaos and then needs 2 memristor elements, it is thus desirable to five dimensions or five tie up above system, the circuit system realizing hyperchaos in the four-dimensional system with memristor element is also fewer, memristor is applied to the method for four-dimensional hyperchaotic system but without being suggested, this is the deficiencies in the prior art parts.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Lorenz type hyperchaotic system circuit containing y side based on memristor:
1. based on the Lorenz type hyperchaotic system circuit containing y side of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, operational amplifier U6 and multiplier U7 and multiplier U8 is utilized to realize the memristor model in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N；
1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin is directly connected to the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1；
1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin is directly connected to the 1st pin and the 3rd pin of multiplier U5,13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4；
1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, the 1st pin of the 3rd pin concatenation operation amplifier U3, the 5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3；
1st pin of described multiplier U5 and the 8th pin of the 3rd pin concatenation operation amplifier U2, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1；
1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 7th pin by resistance R8 concatenation operation amplifier U1,7th pin is directly connected to the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC；
1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin is directly connected to the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.
Beneficial effect: the present invention, on the basis of the Lorenz type chaos system containing y side, utilizes a memristor element to increase the four-dimensional hyperchaotic system of one-dimensional composition, it is proposed that memristor is applied to the new method of hyperchaotic system.
Accompanying drawing explanation
Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.
Fig. 2 realizes in the present invention recalling the actual connection figure of the circuit leading device.
Fig. 3 is the actual connection figure of circuit of operational amplifier U1.
Fig. 4 is the actual connection figure of circuit of multiplier U4 and operational amplifier U2.
Fig. 5 is the actual connection figure of circuit of multiplier U5 and operational amplifier U3.
Detailed description of the invention
Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, referring to Fig. 1-Fig. 5.
1. based on the Lorenz type hyperchaotic system circuit containing y side of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, operational amplifier U6 and multiplier U7 and multiplier U8 is utilized to realize the memristor model in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N；
1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin is directly connected to the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1；
1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin is directly connected to the 1st pin and the 3rd pin of multiplier U5,13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4；
1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, the 1st pin of the 3rd pin concatenation operation amplifier U3, the 5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3；
1st pin of described multiplier U5 and the 8th pin of the 3rd pin concatenation operation amplifier U2, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1；
1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 7th pin by resistance R8 concatenation operation amplifier U1,7th pin is directly connected to the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC；
1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin is directly connected to the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.
Certainly, described above not restriction to invention, the present invention is also not limited to the example above, the change made in the essential scope of the present invention of those skilled in the art, remodeling, interpolation or replacement, falls within protection scope of the present invention.
Claims (1)
1. based on the Lorenz type hyperchaotic system circuit containing y side of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, operational amplifier U6 and multiplier U7 and multiplier U8 is utilized to realize the memristor model in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N；
1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin is directly connected to the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1；
1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin is directly connected to the 1st pin and the 3rd pin of multiplier U5,13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4；
1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, the 1st pin of the 3rd pin concatenation operation amplifier U3, the 5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3；
1st pin of described multiplier U5 and the 8th pin of the 3rd pin concatenation operation amplifier U2, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1；
1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 7th pin by resistance R8 concatenation operation amplifier U1,7th pin is directly connected to the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC；
1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin is directly connected to the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.
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| CN201610089203.1A CN105721136A (en) | 2014-12-03 | 2014-12-03 | Y-power-containing Lorenz type hyperchaotic system circuit based on memristor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620647A (en) * | 2019-10-14 | 2019-12-27 | 江苏理工学院 | Three-dimensional chaotic secret communication circuit |
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Non-Patent Citations (1)
| Title |
|---|
| 胡诗沂, 尹升: "《忆阻在混沌电路中的应用综述》", 《电子制作》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620647A (en) * | 2019-10-14 | 2019-12-27 | 江苏理工学院 | Three-dimensional chaotic secret communication circuit |
| CN110620647B (en) * | 2019-10-14 | 2023-03-07 | 江苏理工学院 | Three-dimensional chaotic secret communication circuit |
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Application publication date: 20160629 |