CN105705990B - 包含有机材料的电子装置 - Google Patents

包含有机材料的电子装置 Download PDF

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CN105705990B
CN105705990B CN201480055852.9A CN201480055852A CN105705990B CN 105705990 B CN105705990 B CN 105705990B CN 201480055852 A CN201480055852 A CN 201480055852A CN 105705990 B CN105705990 B CN 105705990B
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B·兹默尔曼
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Fleck Innabur Technology Co.,Ltd.
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Abstract

一种方法，包括：在一个共用的支撑体(6)上形成一个或多个系列的多层电子装置(分别覆盖区域2a、2b)，然后分离该电子装置；其中，该装置包括一个或多个有机层(9)，并且该方法包括将一个或多个有机层(9)沉积为相应的连续层，该连续层至少从该一个或多个系列装置的一端延伸至该一个或多个系列装置的另一端。

Description

包含有机材料的电子装置
有机材料被越来越多地用于电子装置中的电子功能元件。例如，有机材料被越来越多地用于半导体和晶体管阵列的绝缘体/电介质元件。
用以制作包含有机材料的电子装置的一种技术包括在支撑衬底上沉积有机材料，并使用掩模处理，以避免在该支撑衬底的部分区域内的一个或多个位置中的有机材料的沉积保留在最终的装置中，从而在该装置的一个或多个周边区域留下无有机材料的区域。
本申请的发明人已留意到这种技术所制造的装置的缺陷，并且已认识到进一步减少缺陷的出现的挑战。
本发明的一个目的在于进一步减少在包含有机材料的装置中的缺陷的出现。
因此，本发明提供一种方法，包括：在一个共用的支撑体上形成一个或多个系列的多层电子装置，然后分离该电子装置；其中，该装置包括一个或多个有机层，且该方法包括将一个或多个有机层沉积为相应的连续层，所述连续层至少从该一个或多个系列装置的一端延伸至该一个或多个系列装置的另一端。
根据一个实施例，每个电子装置均包括晶体管阵列，以及沉积为连续层的一个或多个有机层，所述一个或多个有机层包括一个或多个：限定晶体管的半导体沟道的半导体层；限定晶体管的栅极电介质的电介质层；及导体层之间的一个或多个绝缘体层。
根据一个实施例，该电子装置包括至少一个导体层，该导体层限定经由一个或多个驱动器芯片的相应的输出端子驱动的导体阵列；该方法包括将所述一个或多个驱动器芯片的接点定位在被沉积为连续层的所述一个或多个有机层的上方，其中，接点通过所述被沉积为连续层的一个或多个有机层连接至所述导体中的相应的导体。
根据一个实施例，该电子装置包括处于相应层级的至少三个导体层，并且其中所述方法还包括挤压被沉积为连续层的所述一个或多个有机层的周边区域；以及经由在所述周边区域和所述周边区域向内的区域之间延伸的下导体层的一个或多个部分，在所述周边区域中的上导体层的一个或多个部分与在所述周边区域向内的中间导体层的一个或多个部分之间建立一个或多个导电连接。
根据一个实施例，所述上导体层形成晶体管阵列的栅极和源极接点，且所述中间导体的一个或多个部分包括为所述晶体管阵列提供栅电极的一个或多个栅极导体和/或为所述晶体管阵列提供源电极的一个或多个源极导体。
根据一个实施例，该方法还包括：在所述被沉积为连续层的一个或多个有机层中的一个或多个的下方的导体层内设置至少一个链接一组导体的短接导体；设置至少一个层间导电连接，所述层间导电连接在所述短接导体通过所述一个或多个有机层至设置在被沉积为连续层的所述一个或多个有机层的上方的接点之间；经由所述接点的进行电学测试；以及随后通过移除所述导体层的一个或多个部分及覆盖在所述导体层的所述一个或多个部分上的所述一个或多个有机层的一个或多个部分，将所述短接导体与该组导体隔离。
下面将参照附图，仅通过示例的方式描述根据本发明实施例的技术的示例，所述附图中：
图1示意性地示出了形成包含有机材料的多个电子装置的层的沉积区域的示例；
图2示意性地示出了用于多个电子装置的堆叠层的示例；
图3示出了在导体层间的层间导电连接的位置的示例；以及
图4示出了用于利于顶导体层下方的导体的电学测试的技术的示例。
以下将以电子装置为例描述根据本发明实施例的技术的示例；该电子装置包括被设计用于控制光学显示媒介的多个晶体管的晶体管阵列。然而，同样的技术也适用于其他类型的电子装置，以及包括与附图所示的不同的晶体管阵列设计的装置。在本说明书的末尾描述了在本发明范围内对附图中所示的装置进行修改的其他示例。
本示例涉及多个电子装置的制造，所述电子装置在部分制造过程期间共享共用的支撑材料片体6。在制造过程中随后的阶段中，该多个电子装置彼此分离，附图标记2示出了分离后的各电子装置的区域。各电子阵列包括附图标记5所示的晶体管阵列区域，以及用于例如将所述晶体管阵列周围的栅极和源极导体路由(routing)至一个或多个驱动器芯片接点的周边区域。附图标记4指示在制造过程期间在支撑材料片体上沉积导体、半导体、绝缘体/电介质材料的连续层的区域。如所示，该沉积区域4连续延伸布满整个其周边与该装置区域2a-2i中靠外者的外部边缘重合的矩形区域且超过该矩形区域。
支撑材料的示例包括具有平坦化的上表面的柔性的塑料膜。在制造过程期间，该柔性塑料膜可临时附着到刚性的母板(未示出)。
参考图2，制造过程的一个示例包括：在支撑片体6上沉积连续的第一导体层8，接着图案化第一导体层以限定形成用于各电子装置的源极和漏极导体的阵列。在本示例中，第一导体层的图案化还限定栅极导体延伸部和临时短接条，这将在下文中更详细地讨论。源极导体提供用于晶体管的源电极，而漏极导体提供用于相应晶体管的漏极极。根据一个示例，每个源极导体提供用于晶体管阵列中相应行的晶体管的源电极。
然后，在图案化的第一导体层8上沉积有机半导体材料9(诸如一种半导体聚合物)的连续层。该半导体层8形成所有晶体管阵列的所有晶体管的半导体沟道。
然后，在半导体层9上沉积连续的电介质材料层(或连续的电介质材料层的堆叠)10。该电介质层10形成用于所有晶体管阵列的所有晶体管的栅极电介质。
在本示例中，半导体层9和电介质层10随后被图案化以形成用于层间导电连接的通孔，所述层间导电连接从第一导体层8所限定的栅极导体延伸部到要在生产过程的下一个阶段形成的相应的栅极导体。在所述电介质层(一个或多个)10上沉积连续的第二导体材料层12。第二导体层的沉积填充形成于半导体层9和电介质层10中的通孔。第二导体层12然后被图案化以限定用于每个晶体管阵列的栅极导体阵列，其中，该栅极导体为晶体管提供栅电极。在本示例中，每个栅极导体为晶体管阵列的相应列的晶体管提供栅电极，栅极导体通过形成于半导体层9和电介质层10中的通孔连接至由图案化的第一导体层限定的相应的栅极导体延伸部。在本示例中，第二导体层12的图案化也限定了：(a)栅极导体中的用于容纳要在漏极导体和处于更高层级的相应的像素导体之间形成的层间导电连接的通孔；(b)临时短接条，其用于提供栅极导体之间的临时连接，这将在下文中更详细地讨论；以及(c)用于容纳要在上导体层20和由图案化的第一导体层8限定的临时短接条40之间形成的层间连接的通孔。
然后，在图案化的第二导体层13上沉积连续的绝缘材料层(或连续的堆叠材料层的堆叠)14。该(一个或多个)绝缘体层14用于防止在第二导体层12和下文将提到的第三导体层16之间的电短接。
然后，连续的第三导体材料层16沉积在绝缘体14上方，并被图案化从而限定通孔以容纳：(i)在漏极导体和由更高的导体层20限定的相应像素导体之间的层间导电连接，(ii)在栅极导体延伸部和由被图案化的第一导体层限定的源极导体之间至由更高的导体层20限定的相应的驱动器芯片接点的层间导电连接28，以及(iii)用于容纳在由图案化的第一和第二导体层限定的临时短接条和更高的导体层20之间的层间导电互连的通孔。第三导体层16作为屏蔽层来抑制下方的导体的电位对由更高的导体层20限定的像素导体处的电位的影响。
然后，在图案化的第三导体层16上沉积连续的绝缘材料层(或连续的绝缘材料层的堆叠)18。该绝缘材料层18用于防止第三导体层16和更高的导体层20之间的电短接。半导体层9和绝缘体层10、14及18的组合随后被图案化来限定：(i)向下延伸至各漏极导体的通孔，(ii)向下延伸至各栅极导体延伸部的通孔，(iii)向下延伸至各源极导体的通孔；以及(iv)向下延伸至由图案化的第一导体层8和第二导体层12限定的各临时短接条的通孔。
然后，在绝缘体18上沉积连续的第四导体材料层20。该连续的第四导体材料层20填充上一段所提到的通孔(i)、(ii)、(iii)和(iv)。该第四导体材料层20随后被图案化以至少限定：(i)像素导体的阵列，每个像素导体由一个或多个相应的层间导电互连(未示出)连接至相应的漏极导体，(ii)栅极接点，其由一个或多个层间导电连接28连接至由图案化的第一导体层8限定的相应的栅极导体延伸部；(iii)源极接点，其由一个或多个层间导电连接28连接至由图案化的第一导体层8限定的相应的源极导体；及短接条接点，其连接至由图案化的第一导体层8和第二导体层12限定的相应的短接条。由图案化的第四导体层20限定的栅极接点和源极接点用于形成到根据塑料上芯片(COP)技术的一个或多个驱动器芯片的相应输出端子的连接，或形成到一个或多个柔性板上芯片(COP)封装的一个或多个输出端子的连接；以及如下文所述的，短接条接点用于源极和栅极导体的中间电学测试。
如上所述，在本示例中，图案化的第一导体层限定源极导体32的阵列，每个源极导体为相应行的晶体管提供源电极。第一导体层8的图案化包括限定链接图案化的第一导体层8内相应组的源极导体32的一个或多个导体短接条34。所述一个或多个临时短接条40位于源极导体32和图案化的第四导体层20之间的层间导电连接28的位置之外。一个或多个额外的层间导电连接36、38被形成为从各短接条40到一个或多个上层级。在本示例中，这些额外的层间导电连接包括：(a)一个或多个层间连接36，其在各短接条40和由图案化的第二导体层12限定的一个或多个相应的接点之间，以利于在形成栅极导体后及沉积覆盖的绝缘体层14前的阶段进行测试；(b)一个或多个层间连接38，其在各短接条40和由图案化的另一导体层20限定的一个或多个相应的接点之间，以利于在形成像素导体和栅极/源极接点等之后进行测试。完成电学测试之后，通过在短接条与层间连接28(在源极导体32和图案化的第四导体层20之间)的位置之间的一个或多个位置40处形成凹槽，来断开短接条40和第一导体层8内的源极导体32之间的所有导体链接。这些凹槽向下延伸穿过所有堆叠的层到达支撑衬底6。激光烧蚀是形成这些凹槽的技术的一个示例。在本示例中，第二、第三和第四导体层被图案化，使得无需切穿这三个图案化的导体层12、16、20的任何导体材料即可形成这些凹槽，以更可靠地防止在这四个导体层的任意导体层之间出现的不期望的电短接。图4仅示出了7个源极导体，但装置可包括超过一千个源极导体，每个源极导体均为超过一千行的晶体管中的相应行提供源电极。在本示例中，该提供临时短接条的技术类似地应用于栅极导体。在由图案化的第二导体层12限定的各短接条和由图案化的另一导体层20限定的一个或多个相应接点之间设置一个或多个层间互连。
在完成经由图案化的第四导体层20的最终电学测试，并已经隔离临时短接条40后，随后通过切穿层堆叠和支撑片体6，将得到的结构分成单个装置。在本示例中，每个单个装置随后被层压在相应的光学媒介组件上，其中通过控制在由图案化的第四导体层20限定的像素导体的阵列的相应像素导体处的电位，光学媒介22(如电泳媒介)的相应像素部分每一个都可以独立地在两个或更多个状态间切换。
在本示例中，层压过程包括在光学媒介组件和位于晶体管阵列区域5向外的一个或多个区域的控制组件之间设置一个或多个可挤压的接合焊盘26，以在由图案化的第四导体层20限定的一个或多个COM接点和光学媒介组件的共用电极层24之间建立电连接。一个或多个接合焊盘26在光学媒介层压至堆叠的顶部期间被强力挤压，以确保在光学媒介组件的共用电极层24和由图案化的第四导体层20限定的一个或多个COM接点之间导电连接良好且可靠。
在本示例中，用于由图案化的第四导体层20限定的栅极和源极接点两者的层间导电连接28向下延伸至由图案化的第一导体层8限定的源极导体和栅极导体延伸部；并且位于栅极导体和源极导体延伸部之间的层间导电连接30形成在接合焊盘位置内部的位置处(如图3示意性地示出的)。已发现，这种经由被图案化第一导体层20在图案化的第四导体层20和位于接合焊盘位置内侧的中间导体层的部分之间的布线连接技术可减少装置故障的发生。这种装置故障的减少归因于避免通过第二、第三及第四图案化的导体层区域的横向布线，这样的横向布线在挤压位于光学媒介组件和包括在一个或多个绝缘体/半导体层(包含相对柔软的有机材料)上的第二、第三和第四导体层的堆叠顶部之间的接合焊盘26时，可能容易变形。该制造程序可包括额外的工艺步骤，诸如包封。
该电子装置可包含未在附图示出或未在上文中提到的一个或多个元件。例如，可以例如在塑料支撑膜和用于平坦化该塑料支撑膜的上表面的平坦化层之间、和/或在平坦化层和第一图案化的导体层之间、和/或在塑料支撑膜层的与平坦化层相对的一侧设置一个或多个附加功能层。
在本示例中，半导体层9和所有的电介质/绝缘体层10、14、18包括有机聚合材料，并且通过液体处理(柔性版印刷和/或狭缝涂覆)或气相沉积沉积为连续层，即，没有用任何用以防止在晶体管阵列区域5周围的任何区域上沉积的掩模处理。本申请的发明人已发现在阵列被用于控制显示光学媒介时，减少使用掩模可以使晶体管阵列区域上的光学非均匀性较少。
在本示例中，可通过激光烧蚀方式来实现上述有机材料层的图案化。
在本示例中，所有的四个导体层可通过溅射来沉积，并通过光刻法来图案化。用于导体层的导体材料的示例包括金属和金属合金。导体层可具有多层结构。例如，已发现对导体层使用双层金属结构可改善导体层和下方的有机材料之间的粘着性。例如，已发现通过首先沉积钛(Ti)并然后沉积具有高导电性的金属(诸如，金)形成各导体层可产生对于下方有机材料具有更好的粘着性以及良好的导电性的层。还发现在沉积覆盖金属之前直接使有机层经受氩等离子处理，可改善有机材料与覆盖的金属之间的粘着性。还发现在沉积覆盖有机电介质/绝缘材料之前直接使金属层经受紫外线预处理，可改善金属层对相应的覆盖有机材料的粘着性。
在源极导体封装密度可能最高的情况下，可以在沉积栅极电介质层10前，以减少在相邻的源极导体之间(特别是在垂直互连28附近)的泄漏电流的方式进一步将半导体层9图案化。激光烧蚀是用于执行这种进一步图案化的技术的示例。减少泄漏电流(如有必要的话)的技术的另一个示例包括：在沉积半导体材料9前，在图案化的第一导体层上沉积连续的绝缘材料(例如绝缘光刻胶材料)层，并将该绝缘层图案化以使该绝缘层保持在半导体层9的那些需要关注泄漏电流的区域的下方。另一个替代的技术示例是永久降低在半导体层9的那些需要关注泄漏电流的区域中的半导体材料的导电性。另一个替代技术的示例是在图案化的导体层中限定一个或多个附加导体，其在半导体层中的需要关注泄漏电流的区域上，并对该附加导体施加电压，所述电压通过场效应机制降低下方的半导体的导电性。
也已发现，上述减少利用掩模来沉积有机材料的技术有利于导体层的高分辨率图案化。
上述说明涉及顶栅极晶体管阵列的示例。然而，上述技术同样可适用于晶体管阵列装置以外的电子装置的制造，以及也可适用于包括其他类型的晶体管阵列(诸如，底栅极晶体管阵列)的装置的制造。例如，上述技术也可适用于包括叠层(包含一个或多个有机材料)的其他类型的装置。另一种不包括半导体层的装置的示例是直接驱动单元装置，该装置中，各像素导体直接(即，不通过晶体管)连接至控制器的相应输出端子。包括半导体层的装置的另一个示例是诸如辐射传感器的传感器装置。
上述说明涉及一个示例，其中，栅极和源极导体在TFT阵列的覆盖区域(footprint)内占据不同层级，并且源极导体或者栅极导体被绕着TFT阵列的一个角被连线至驱动器芯片接点。然而，上述技术也可与其中栅极导体或源极导体被经由在阵列的覆盖区域内的位于栅极和源极导体中的另一方之间的处于与栅极和源极导体中的所述另一方相同的层级的位置被连线至驱动器芯片接点的技术组合使用。
上述说明涉及装置架构的一个示例，其中由顶导体层限定的像素导体经由栅极导体中的通孔连接至下导体层限定的相应漏极导体，并且第四、屏蔽导体层设置在限定栅极导体的导体层和限定像素导体的导体层之间。然而，上述技术也适用于例如其他架构，在所述其他架构中：各漏极导体包括不在任何栅极导体下的接合焊盘，并且可以不需栅极导体中的通孔就能连接到相应的像素导体；和/或不需要第四屏蔽导体层。
除了以上明确的修改外，对于本领域技术人员明显的是，可在本发明范围内可对所描述的实施例的进行各种其他修改。
本文中申请人分开地公开了本文所述的各个单独的特征和两个或多个这些特征的任意组合，因而，按照本领域技术人员的一般认识，基于本说明书的整体能够实施这种特征或其组合，不论所述特征或者特征的组合是否解决本文所公开的任何问题，并且不限制本权利要求书的范围。申请人指出本发明的方面可以由任何这种单独的特征或特征的组合构成。

Claims (10)

1.一种电子装置的制造方法，所述方法包括：在一个共用的支撑体上形成在一个行之内的相邻装置之间具有区域的一个或多个行的多层电子装置，然后将所述多层电子装置彼此分离并且还将所述多层电子装置与在一个行之内的相邻装置之间的所述区域分离；其中所述电子装置各自包括用于控制显示光学媒介的晶体管阵列，并且所述电子装置包括一个或多个有机层，以及所述方法包括将所述有机层中的一个或多个沉积为相应的连续层，所述连续层至少从所述一个或多个行的装置中的一端延伸至所述一个或多个行的装置的另一端并且覆盖一个行之内的相邻装置之间的所述区域，其中形成所述电子装置包括：(i)在沉积所述一个或多个有机层之前，形成至少一个导体层，所述至少一个导体层限定经由一个或多个驱动器芯片的相应的输出端子来驱动的导体的阵列；(ii)在所述一个或多个有机层中向下至所述导体的阵列形成通孔；和(iii)之后，在所述一个或多个有机层上方形成导体层，其中所述一个或多个有机层上方的所述导体层限定用于连接至所述一个或多个驱动器芯片的接点，所述接点经由所述通孔连接至所述导体的阵列中的相应的导体。
2.根据权利要求1所述的方法，其中，其中所述被沉积为连续层的一个或多个有机层包括下列中的一个或多个：限定所述晶体管的栅极电介质的电介质层，以及导体层之间的一个或多个绝缘体层。
3.一种电子装置的制造方法，包括：在一个共用的支撑体上形成一个或多个系列的多层电子装置，然后将所述多层电子装置彼此分离；其中所述装置包括一个或多个有机层，所述方法包括将所述有机层中的一个或多个沉积为相应的连续层，所述连续层至少从所述一个或多个系列的装置中的一端延伸至所述一个或多个系列装置的另一端，其中所述装置包括处于相应的层级的至少三个导体层，并且其中所述方法还包括：经由在周边区域和所述周边区域横向向内的区域之间延伸的下导体层的一个或多个部分，在所述周边区域中的上导体层的一个或多个部分与在所述周边区域横向向内的中间导体层的一个或多个部分之间建立一个或多个导电连接。
4.根据权利要求3所述的方法，其中，所述电子装置各自包括晶体管阵列，并且其中所述被沉积为连续层的一个或多个有机层包括下列中的一个或多个：限定所述晶体管的半导体沟道的半导体层，限定所述晶体管的栅极电介质的电介质层，以及导体层之间的一个或多个绝缘体层。
5.根据权利要求3所述的方法，其中所述电子装置包括至少一个导体层，所述至少一个导体层限定经由一个或多个驱动器芯片的相应的输出端子来驱动的导体的阵列；并且其中所述方法包括将用于所述一个或多个驱动器芯片的接点定位在所述被沉积为连续层的一个或多个有机层上，其中所述接点通过所述被沉积为连续层的一个或多个有机层连接至所述导体的阵列中的相应的导体。
6.根据权利要求3所述的方法，还包括将接合焊盘定位在所述周边区域中以用于所述上导体层和光学媒介组件的共用电极层之间的导电连接；以及挤压所述光学媒介组件的所述共用电极层和所述上导体层之间的所述接合焊盘。
7.根据权利要求3所述的方法，其中所述上导体层限定晶体管阵列的棚极和源极接点，并且所述中间导体层的所述一个或多个部分包括为所述晶体管阵列提供栅电极的一个或多个栅极导体和/或为所述晶体管阵列提供源电极的一个或多个源极导体。
8.根据权利要求3所述的方法，还包括：在所述被沉积为连续层的一个或多个有机层中的一个或多个的下方设置的导体层内设置链接一组导体的至少一个短接导体；设置至少一个层间导电连接，所述层间导电连接从所述短接导体到设置在所述被沉积为连续层的一个或多个有机层的上方的接点；经由所述接点进行电学测试；以及随后通过移除所述导体层的一个或多个部分及在所述导体层的所述一个或多个部分上的所述一个或多个有机层的一个或多个部分，将所述短接导体与该组导体隔离。
9.根据权利要求4所述的方法，其中所述下导体层是第一导体层，所述中间导体层是第二导体层，所述上导体层是第四导体层；其中所述装置包括在所述第二导体层和所述第四导体层之间的第三导体层；并且其中所述周边区域中的所述上导体层的所述一个或多个部分包括所述晶体管阵列的棚极接点，所述周边区域横向向内的所述中间导体层的所述一个或多个部分包括为所述晶体管阵列提供栅电极的棚极导体，以及在所述周边区域和所述周边区域横向向内的所述区域之间延伸的所述下导体层的所述一个或多个部分包括栅极导体延伸部。
10.根据权利要求3所述的方法，其中所述至少三个导体层和一个或多个导体延伸部包括金属或金属合佥。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2556313B (en) * 2016-02-10 2020-12-23 Flexenable Ltd Semiconductor patterning
GB2563191A (en) * 2017-03-15 2018-12-12 Flexenable Ltd Cross-linked polymers
GB2567871B (en) * 2017-10-27 2022-02-02 Flexenable Ltd Electronic device for pressure sensors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870235A (zh) * 2005-05-27 2006-11-29 三星Sdi株式会社 有机tft,其制造方法以及平板显示器件
JP2007041386A (ja) * 2005-08-04 2007-02-15 Seiko Epson Corp 電気泳動表示モジュール、電子機器及び電気泳動表示モジュールの製造方法。
CN101295680A (zh) * 2007-04-25 2008-10-29 精工爱普生株式会社 有源矩阵基板、其制造方法、电光装置、其制造方法及电子设备
US7718453B2 (en) * 2000-11-02 2010-05-18 Seiko Epson Corporation Organic electroluminescent device, method of manufacturing the same, and electronic apparatus
WO2010092891A1 (ja) * 2009-02-10 2010-08-19 ブラザー工業株式会社 有機半導体素子、及びその製造方法
CN103155193A (zh) * 2010-06-04 2013-06-12 造型逻辑有限公司 电子开关器件的制造

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4115158B2 (ja) * 2002-04-24 2008-07-09 シャープ株式会社 半導体装置およびその製造方法
JP4325479B2 (ja) * 2003-07-17 2009-09-02 セイコーエプソン株式会社 有機トランジスタの製造方法、アクティブマトリクス装置の製造方法、表示装置の製造方法および電子機器の製造方法
JP3909601B2 (ja) * 2004-07-29 2007-04-25 セイコーエプソン株式会社 フレキシブルプリント基板の実装方法及び、電気光学装置の製造方法
US9000418B2 (en) * 2004-11-19 2015-04-07 Panasonic Corporation Field effect transistor, method of manufacturing the same, and electronic device using the same
KR101219035B1 (ko) * 2005-05-03 2013-01-07 삼성디스플레이 주식회사 유기 박막 트랜지스터 표시판 및 그 제조 방법
JP5107596B2 (ja) * 2007-03-13 2012-12-26 三菱電機株式会社 液晶表示装置、及びその製造方法
DE102007062944B4 (de) * 2007-12-21 2016-03-17 Leonhard Kurz Stiftung & Co. Kg Elektronische Schaltung
KR101738531B1 (ko) * 2010-10-22 2017-05-23 삼성디스플레이 주식회사 유기 발광 디스플레이 장치의 제조 방법 및 이에 따라 제조된 유기 발광 디스플레이 장치
KR20120042365A (ko) * 2010-10-25 2012-05-03 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
GB2485828B (en) * 2010-11-26 2015-05-13 Plastic Logic Ltd Electronic devices
KR102133433B1 (ko) * 2013-05-24 2020-07-14 삼성디스플레이 주식회사 유기 발광 표시 장치, 이를 포함하는 전자 기기, 및 유기 발광 표시 장치의 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7718453B2 (en) * 2000-11-02 2010-05-18 Seiko Epson Corporation Organic electroluminescent device, method of manufacturing the same, and electronic apparatus
CN1870235A (zh) * 2005-05-27 2006-11-29 三星Sdi株式会社 有机tft,其制造方法以及平板显示器件
JP2007041386A (ja) * 2005-08-04 2007-02-15 Seiko Epson Corp 電気泳動表示モジュール、電子機器及び電気泳動表示モジュールの製造方法。
CN101295680A (zh) * 2007-04-25 2008-10-29 精工爱普生株式会社 有源矩阵基板、其制造方法、电光装置、其制造方法及电子设备
WO2010092891A1 (ja) * 2009-02-10 2010-08-19 ブラザー工業株式会社 有機半導体素子、及びその製造方法
CN103155193A (zh) * 2010-06-04 2013-06-12 造型逻辑有限公司 电子开关器件的制造

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