CN105702724A - Semiconductor device and formation method thereof - Google Patents
Semiconductor device and formation method thereof Download PDFInfo
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- CN105702724A CN105702724A CN201410707067.9A CN201410707067A CN105702724A CN 105702724 A CN105702724 A CN 105702724A CN 201410707067 A CN201410707067 A CN 201410707067A CN 105702724 A CN105702724 A CN 105702724A
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Abstract
The invention provides a semiconductor device and a formation method thereof. The formation method includes: a substrate is formed; a grid electrode structure is formed on the substrate; the substrate and the grid electrode structure are covered by a protective layer used for protecting the grid electrode structure; grooves are formed in the substrate at two sides of the grid electrode structure; the grooves are filled with semiconducting materials to form stress layers; ion doping of the semiconducting materials is performed to form source regions and drain regions; and after the step of the covering of the protective layer and before the step of forming the stress layers via the filling of the semiconducting materials, the formation method of the semiconductor device also includes: performing dry cleaning of the semiconductor device by employing fluorine-containing gas. According to the semiconductor device and the formation method thereof, a lot of defects generated after epitaxial growth can be avoided, the yield in the manufacturing process of the devices can be effectively increased, and the manufacturing cost of the device is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly to a kind of semiconductor device and forming method thereof。
Background technology
In existing process for fabrication of semiconductor device, the mode of the channel region introducing stress being typically employed in MOS device improves carrier mobility, and then improves the performance of MOS device。
For PMOS device, adopt embedded germanium silicon technology to form source region and drain region, produce compressive stress with the channel region at device, and then improve carrier mobility。So-called embedded germanium silicon technology refers to need to be formed in the region in source region and drain region in Semiconductor substrate and forms groove, fills germanium silicon material afterwards as stressor layers, utilize the lattice mismatch between silicon and germanium silicon that channel region is produced compressive stress in described groove。In concrete technology, the generally original position doped with boron ion when epitaxial growth Ge-Si, to form source region and the drain region of transistor。
But, prior art is after the boron doped germanium silicon technology of epitaxial growth, and semiconductor device surface easily produces residual, thus forming defect。The contact between easy block device in follow-up technique of this defect, therefore, device yield, yields are had a great impact by these defects。
Summary of the invention
The problem that this invention address that is to provide a kind of semiconductor device and forming method, to reduce the defect of semiconductor device surface。
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor device, including:
Form substrate；
Substrate is formed grid structure；
Described substrate and described grid structure cover the protective layer for protecting described grid structure；
Groove is formed in the substrate of grid structure both sides；
Filling semiconductor material in described groove, to form stressor layers；
Described semi-conducting material is carried out ion doping, forms source region and drain region；
After the step of protective mulch, before filling semiconductor material forms the step of stressor layers, the forming method of described semiconductor device also includes: adopt fluoro-gas that described semiconductor device is carried out dry method cleaning。
Optionally, the step of described formation substrate includes: provide substrate；Groove is formed in described substrate；The first laying is covered at described channel bottom and sidewall；Covering the second laying on described first laying surface, described second backing layer material is set to during described fluoro-gas dry method is cleaned the removal rate of the second laying less than the removal rate of described first laying；Being formed with fill insulant in the described groove of the first laying and the second laying, to form isolation structure。
Optionally, the material of described first laying is silicon oxide, and the material of described second laying is silicon nitride。
Optionally, the thickness of described second laying existsAbove。
Optionally, the step of described formation the second laying includes: adopt chemical vapour deposition (CVD), the mode of ald forms described second laying。
Optionally, described protective layer includes the oxide skin(coating) and the nitride layer that sequentially form。
Optionally, the described step forming groove in the substrate of grid structure both sides includes: with described grid structure for mask, and the protective layer of described grid structure both sides is carried out the first etching, forms the opening that can expose described substrate surface in described protective layer；The substrate that described opening is exposed carries out the second etching, forms groove in substrate；The forming method of described semiconductor device includes: forming protective layer, the first etching, performing, between the second etching and any two step of filling semiconductor material, the step that fluoro-gas dry method described in one or many is cleaned。Described fluoro-gas dry method is cleaned the gas adopted and is included NF3And NH3。
Optionally, NF described in the cleaning of described fluoro-gas dry method3The flow of gas is 35～100sccm, described NH3Flow be 10～400sccm, scavenging period is 1～60s, and radio-frequency power is 5～100W, clean environment air pressure range be 0.5～20Torr；Temperature range is 20～170 DEG C。
Optionally, described fluoro-gas dry method cleaning step includes: produce the abluent of plasma state in the reactor chamber；Utilize described abluent that semiconductor device is carried out；At the temperature more than 100 DEG C, the semiconductor device through cleaning is heated；Semiconductor device through heating is annealed。The temperature that semiconductor device is carried out by described abluent is utilized to maintain 35 DEG C。
Optionally, after described formation groove, in described groove before the step of filling semiconductor material, the forming method of described semiconductor device also includes: described groove is carried out prerinse；After prerinse step, carry out described fluoro-gas dry method clean。
Optionally, described to the technique of filling semiconductor material in described groove be selective epitaxial growth process。
Optionally, the described step that described semi-conducting material carries out doping formation source region and drain region includes: carries out original position ion doping in the process of selective epitaxial growth process and forms source region and drain region。
Correspondingly, present invention also offers a kind of semiconductor device structure, described semiconductor device is formed by described forming method, including:
Substrate, is formed with multiple groove in described substrate；
It is positioned at the first laying on channel bottom and sidewall；
It is positioned at the second laying on described first laying；
It is filled in described groove and is formed at the isolation structure on the second laying；
Being positioned at the grid structure on substrate, described grid structure surface and sidewall are coated with protective layer；
The stressor layers in substrate between described isolation structure and grid structure, is used as source region and drain region doped with ion in described stressor layers。
Optionally, the forming process of described semiconductor device includes the step adopting fluoro-gas dry method to clean, and described second backing layer material is set to during described fluoro-gas dry method is cleaned the removal rate of the second laying less than the removal rate of described first laying。
Optionally, the material of the first described laying is silicon oxide, and the material of described second laying is silicon nitride。
Optionally, the thickness of the second described laying existsAbove。
Compared with prior art, technical scheme has the advantage that
The present invention is after protective mulch; before carrying out being epitaxially-formed the step of stressor layers; add the step that fluoro-gas dry method is cleaned; polymer and pollutant are had very strong removal effect by fluorine-containing abluent; the quantity of the nuclei of crystallization can be reduced; it is thus possible to effectively reduce the defect produced in subsequently epitaxial growing materials process, and then improve the yields in device manufacturing processes, reduce device manufacturing cost。
Alternatively, in the forming process of isolation structure, the first laying of trenched side-wall covers the second laying。Fluoro-gas dry method cleans the removal rate to the second laying less than the removal rate to the first laying; therefore increase by the second laying and can be effectively protected the sidewall of isolation structure in cleaning process; can effectively eliminate or reduce the loss of isolated side wall; thus preventing isolation structure in cleaning process by excessive etching, the appearance preventing electric leakage or short circuit phenomenon, and then the yields in device manufacturing processes can be effectively improved, reduce device manufacturing cost。
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the schematic diagram of a kind of method for forming semiconductor devices of prior art；
Fig. 3 to Fig. 8 is the schematic diagram of each step in method for forming semiconductor devices first embodiment provided by the present invention；
Fig. 9 to Figure 13 is the schematic diagram of each step in method for forming semiconductor devices the second embodiment provided by the present invention；
Figure 14 is the microscopic comparison of the semiconductor device that method for forming semiconductor devices provided by the present invention is formed with prior art。
Detailed description of the invention
By background technology it can be seen that in prior art, can semiconductor device be carried out after epitaxial growth stressor layers, described cleaning step easily forms many small defects at semiconductor device surface, in conjunction with the reason that device forming process analyzing defect is formed:
As shown in Figure 1; epitaxial growth boron doped germanium silicon is as in the technique of stressor layers; substrate 10 is formed after isolation structure 11; before carrying out stressor layers epitaxial growth; semiconductor device sequentially passes through: deposition protective layer 12 and etched substrate form the steps such as groove 13; any of step all easily produces pollutant and etch residue (pollutant 14), and these pollutant are deposited in protective layer 12 surface, forms defect。
As in figure 2 it is shown, pollutant 14 are in the process being epitaxially-formed stressor layers 15, become the nuclei of crystallization of epitaxial grown material。Due to nucleation, it is big that pollutant 14 can grow change in epitaxially grown process。Thus after epitaxial growth, numerous small pollutant all can become the bigger defect of volume 24。In follow-up technique, described defect 24 can affect the connection conducting between device, affects properties of product。
In prior art, the method reducing above-mentioned epitaxial growth defect mainly has following two: one is addition HCl gas in boron doped germanium siliceous deposits process, to increase etching selection ratio, so pollutant is carried out epitaxially grown simultaneously。But this method is since it is desired that increase HCl gas, therefore can reduce thruput, make Material growth slow；Another kind of method is wet-cleaning flow process, and to remove pollutant, but the effect of this method is very limited。
For solving described technical problem, the invention provides a kind of semiconductor device and forming method thereof, comprise the steps:
Form substrate；
Substrate is formed grid structure；
Described substrate and described grid structure cover the protective layer for protecting described grid structure；
Groove is formed in the substrate of grid structure both sides；
Filling semiconductor material in described groove, to form stressor layers；
Described semi-conducting material is carried out ion doping, forms source region and drain region；
After the step of protective mulch, before filling semiconductor material forms the step of stressor layers, the forming method of described semiconductor device also includes: adopt fluoro-gas that described semiconductor device is carried out dry method cleaning。
The present invention is by the process that semiconductor device is formed, add the step that fluoro-gas dry method is cleaned, pollutant were removed before material epitaxy grows as far as possible, so that the nuclei of crystallization of pollutant reduce in material epitaxy growth course as far as possible, avoid pollutant in epitaxial process, grow up into defect, thus the defects count of device surface after decreasing epitaxial growth, improving device performance, and then improve the yields in device manufacturing processes。
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail。
Fig. 3 to Fig. 8 be semiconductor device provided by the present invention forming method first embodiment in the schematic diagram of each step。It should be noted that the present embodiment illustrates for cmos device, the present invention should do not limited with this。
With reference to Fig. 3, it is provided that substrate 1000, in described substrate 1000, it is formed with multiple isolation structure 110。
Described semiconductor base 1000 is the work platforms of subsequent technique。Described semiconductor base 1000 material is selected from monocrystal silicon, polysilicon or non-crystalline silicon；Described semiconductor base 1000 can also be selected from silicon, germanium, GaAs or silicon Germanium compound；Described semiconductor base 1000 is also selected from having epitaxial layer or epitaxial layer silicon-on；Described semiconductor base 1000 can also is that other semi-conducting materials, and this is not limited in any way by the present invention。The material of substrate 1000 described in the present embodiment is silicon。
With reference to Fig. 4, described substrate 1000 forms grid structure 102。
Described grid structure 102 includes gate dielectric layer (not indicating) and the gate electrode layer (not indicating) being positioned on gate dielectric layer。The material of gate dielectric layer is silicon oxide or high dielectric constant material, and described gate electrode layer material is polysilicon or metal。In the present embodiment, the material of the gate dielectric layer of described grid structure 102 is silicon oxide, and gate electrode layer material is polysilicon。
With reference to Fig. 5, protective mulch 120 in described substrate 1000 and on described grid structure 102, described protective layer 120 includes the oxide skin(coating) 121 and the nitride layer 122 that sequentially form。
Described protective layer 120 for protecting described substrate and grid from damage in subsequent etching processes, and concrete, described protective layer 120 includes the oxide skin(coating) 121 and the nitride layer 122 that sequentially form。Described oxide skin(coating) 121 material is silicon oxide, it is possible to obtained by the oxidation technology that described substrate 1000 and described grid structure 102 surface are carried out。It addition, described nitride layer 122 selects layer when subsequently epitaxial growing germanium silicon material as extension, concrete, described nitride layer 122 material is silicon nitride。Additionally, described oxide skin(coating) 121 and described nitride layer 122 form grid curb wall subsequently through etching, play the effect of protection grid and isolation source region (or drain region) and grid。
It should be noted that; the forming process of described protective layer 120 easily forms pollutant 131, and pollutant 131 can become the nuclei of crystallization of Material growth in the process of follow-up crystal growth, in epitaxial process; it is big that pollutant 131 can grow change, forms the defect that volume is bigger。In follow-up technique, the connection conducting between device can be affected, affect properties of product。Described device, after forming described oxide skin(coating) 121 and described nitride layer 122, is carried out fluoro-gas dry method cleaning by the present embodiment。
Concrete, described fluoro-gas dry method cleaning step includes:
First, in reaction chamber, produce the abluent of plasma；
Second step, utilizes described abluent, in reaction chamber, semiconductor device is carried out, and the temperature of described cleaning process maintains 35 DEG C,；
3rd step, is heated the semiconductor device through cleaning at the temperature more than 100 DEG C；
4th step, is annealed the quasiconductor through heating。
In the present embodiment, the gas that described dry method cleaning adopts is containing NF3And NH3Gas。Inventor finds through test, and described pollutant main component is metal ion, and the fluorion in purgative gas body can react with metal ion, forms the fluoride of easy cleaning, it is achieved thereby that the removal to pollutant。
Concrete, in described cleaning process, NF3The flow of gas is 35～100sccm, described NH3Flow be 10～400sccm, described NF3And NH3Flow make to form sufficient concentrations of plasma clean agent in reaction chamber and remove described pollutant。Scavenging period is 1～60s, and described scavenging period enables abluent to have time enough and pollutant reaction, removes pollutant。In cleaning process, radio-frequency power is 5～100W, and the pressure limit cleaning environment is 0.5～20Torr；Temperature range is 20～170 DEG C。Described lower powered plasma system has benefited from NF3And NH3Gas can dissociate under Low emissivity energy, and described temperature range then ensure that the generation that abluent reacts。
With reference to Fig. 6, described protective layer 120 is carried out the first etching, described protective layer 120 is formed the opening 103 that can expose described substrate 1000。
In the present embodiment, adopt conventional dry etching that described protective layer 120 is carried out the first etching, described protective layer 120 is formed the opening 103 exposing described substrate 1000。
It should be noted that the first etching technics to protective layer 120, it is easy to there is etch residue 132 to exist。Optionally, after the first etching technics, described semiconductor device being also carried out fluoro-gas dry method and cleans, specifically, fluoro-gas dry method cleaning is identical with the step that the fluoro-gas dry method carried out after above-mentioned formation protective layer is cleaned herein, does not repeat them here。
With reference to Fig. 7, the substrate 1000 that described opening 103 is exposed carries out the second etching, forms groove 104 in substrate 1000 region in source region to be formed and drain region。
In the present embodiment, adopt the groove being shaped as Sigma shape in the technique of wet etching in described substrate 1000, there is the protrusion pointing to channel region most advanced and sophisticated in the middle part of described Sigma connected in star 104, follow-up in Sigma connected in star 104 extension fill boron-doping germanium silicon material time, germanium silicon material fills full whole groove, at the most advanced and sophisticated place that described groove 104 protrudes, germanium silicon material, closer to channel region, will introduce bigger compressive stress at channel region。
The technique forming described Sigma connected in star is: first carrying out plasma etching, described plasma etching parameter includes: etching gas includes HBr, O2、He、Cl2And NF5, described HBr flow is 100～1000sccm, O2Flow is 2～20sccm；He flow is 100～1000sccm, Cl2Flow is 2～200sccm, NF5Flow is 2～200sccm, and etching air pressure is 10～200mTorr, and bias is 0～400V, and the time is 5～60 seconds；Carrying out wet etching after plasma etching, described wet-etching technology adopts TMAH (Tetramethylammonium hydroxide) solution, and the temperature of TMAH is 15 DEG C～70 DEG C, and the time is 20～500 seconds。Optionally, described wet-etching technology can also adopt potassium hydroxide solution or ammonia spirit。
Similar; the second time etching of Sigma connected in star 104 is formed in substrate 1000; it is also possible to leave etch residue 203 on the surface of nitride layer 122; therefore; optionally, semiconductor device fluoro-gas dry method is cleaned, specifically; fluoro-gas dry method cleaning is identical with the step that the fluoro-gas dry method carried out after above-mentioned formation protective layer is cleaned herein, does not repeat them here。
It should be noted that after groove 104 is formed, described dry method is cleaned and can also be removed the natural oxidizing layer that groove 104 surface is formed while removing pollutant 203, provides clean surface for subsequently epitaxial growing semi-conducting material。Concrete, described fluoro-gas dry method is cleaned the step removing natural oxidizing layer and is included: first, produce the abluent of plasma in reaction chamber:
The chemical reaction producing abluent is:
NF3+NH3→NH4F+NH4F.HF
Second step, utilizes described abluent, in reaction chamber, semiconductor device is carried out；
The temperature of described cleaning process maintains 35 DEG C, and the chemical reaction of cleaning process is:
NH4F+SiO2→(NH4)2SiF6(solid)+H2O
Or NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O
3rd step, is heated the semiconductor device through cleaning at the temperature more than 100 DEG C；
4th step, is annealed the quasiconductor through heating。
The chemical reaction of its annealing process is:
(NH4)2SiF6(solid)→SiF4(gas)+NH3(gas)+HF(gas)
It can further be stated that, in the present embodiment, after groove 104 is formed, fluoro-gas dry method is cleaned before removing etch residue 203, also include semiconductor device is carried out prewashed step, it is therefore an objective to provide cleaner surface for epitaxial growth in successive recesses 104。
With reference to Fig. 8, filling semiconductor material in described groove 104, to form stressor layers, in described stressor layers, dopant ion is to form source region or drain region 105。
In the present embodiment, the transistor of formation is PMOS, and described semi-conducting material is germanium silicon material, for providing compressive stress to the channel region of PMOS。
Specifically, also can original position doped p-type ion in germanium silicon material while epitaxial growth germanium silicon material。Such as, described P type ion is boron ion, and the formation process of selective epitaxial growth can be adopted to form stressor layers。There is the protrusion pointing to channel region most advanced and sophisticated in the middle part of Sigma shape stressor layers, protruding the germanium silicon material located at tip closer to channel region, bigger compressive stress will be introduced at channel region, can be more beneficial for improving the mobility of channel region carriers。
It should be noted that optional, perform the described fluoro-gas dry method cleaning step of one or many between any two step in protective mulch, the first etching, the second etching and epitaxial growth。Concrete includes after forming protective layer, before the first etching; or after first etches, before the second etching; or after second etches, before epitaxial growth, three time points select wherein any one or more addition fluoro-gas dry method cleaning steps。
Fig. 9 to Figure 13 be semiconductor device provided by the present invention forming method the second embodiment in the schematic diagram of each step。
The present embodiment part that is basically the same as those in the first embodiment repeats no more, and the present embodiment and first embodiment are different in that, the step that described quasiconductor forming method forms substrate is different。In conjunction with reference to Fig. 9 to Figure 12, it is shown that method for forming semiconductor devices the second embodiment of the present invention is formed each step schematic diagram of substrate 2000。
Concrete, the step forming substrate 2000 includes:
With reference to Fig. 9, it is provided that Semiconductor substrate 200, in described Semiconductor substrate 200, form groove 211。
Optionally, before forming groove 211 in described substrate 200, it is additionally included in formation barrier layer, substrate 200 surface (not indicating in figure), to protect substrate 200 from the damage of etching technics。
With reference to Figure 10, sequentially forming the first laying 212 and the second laying 213 in described groove 211, described first laying 212 covers bottom and the sidewall of described groove 211, and described second laying 213 is covered on described first laying 212。
The effect of described first laying 212 is to improve the interfacial characteristics between described groove 211 and the follow-up megohmite insulant being filled in groove 211。In the present embodiment, the material of the first laying 212 is silicon oxide, and described first laying 212 can pass through to aoxidize the sidewall of described groove 211 and bottom formation。It addition, described oxidizing process can also repair etch semiconductor substrates 200 forms the damage that groove 211 sidewall and bottom are caused by the process of groove 211。
The effect of described second laying 213 is to reduce the loss in follow-up fluoro-gas dry cleaning process of groove 211 sidewall。Concrete, described second laying 213 material is set to during described fluoro-gas dry method is cleaned the removal rate of the second laying 213 less than the removal rate of described first laying 212。
Semiconductor device provided by the present invention forms flow process and adds the step that fluoro-gas dry method is cleaned, and the fluoro-gas dry method cleaning adopted is a kind of based on NF3And NH3The cleaning that gas carries out, is a kind of etching technics for oxide。Compared with the method adopting diluted hydrofluoric acid to be carried out in prior art, formed in flow process at semiconductor device and add the step that institute's fluoro-gas dry method cleans and easily make the loss of isolation structure sidewall relatively more, isolation structure in fluoro-gas dry cleaning process likely by overetch。
In the present embodiment; the material of described second laying 213 is nitride; compared with oxide; nitride has less etch rate in fluoro-gas dry cleaning process; with material be nitride the second laying 213 for stop-layer; etch cleaner can be made to stop on the second laying 213, it is possible to efficiently reduce the loss of isolation structure sidewall such that it is able to be effectively protected the sidewall of isolation structure in cleaning process。
Concrete, in the present embodiment, the second laying 213 material is silicon nitride, and described second laying 213 can be formed by the mode such as chemical vapour deposition (CVD) and ald。In fluoro-gas dry method cleaning, the etching selection ratio of silicon oxide and silicon nitride is in the scope of 6:1 to 10:1。In the present embodiment, the etching selection ratio of silicon oxide the first laying 212 and silicon nitride the second laying 203 is 7.06:1。
If it should be noted that the thickness of the second laying 213 is too small, it is difficult to form effective protective effect in follow-up cleaning process。The thickness of optionally described second laying existsAbove。In the present embodiment, the thickness of the second laying 213 of silicon nitride material is
With reference to Figure 11, being formed with fill insulant 214 in the groove 211 of the first laying 212 and the second laying 213。
The effect of insulant 214 is to realize the electric isolution between different components region。In the present embodiment, described insulant is silicon oxide。
It should be noted that, in groove 211, fill insulant 214 not only to be limited by the impact of fill process, it is additionally subjected to the impact of groove 211 pattern, when especially the groove of high-aspect-ratio (depth-to-width ratio is more than 10) being filled with, it is easy in insulant, form space。Therefore, optionally, after insulant has been filled, an annealing process is carried out, it is possible to reduce the space formed during fill insulant in groove 211。
With reference to Figure 12, described insulant 214 is carried out planarization process, form isolation structure 210, remove the barrier layer (not identifying in figure) on Semiconductor substrate 200 surface, form substrate 2000。
Concrete, adopt the method for cmp that described insulant 214 is carried out planarization process。In chemical mechanical planarization process, with the surface of exposing Semiconductor substrate 200 for terminating。Afterwards, remove barrier layer (not identifying in figure) unnecessary in Semiconductor substrate 200, thus forming the substrate 2000 being subsequently used for forming grid structure, source region, drain region and stressor layers。
With reference to Figure 13, forming device grids structure 202 in described substrate 2000, form described stressor layers, source region and drain region 205 in described substrate 2000, concrete steps are consistent with first embodiment, do not repeat them here。
With reference to Figure 14, it is shown that the microscopic comparison of the semiconductor device that semiconductor device provided by the present invention is formed with prior art。Wherein shown in A1, A2 be existing technique formed semiconductor epitaxial growth after case of surface defects；Shown in B1, B2 is the device adopting technical solution of the present invention to be formed, the defect situation of the rear surface of epitaxial growth。In figure, black circle is wafer, and white portion is the region that device is formed。In white portion, black splotch is after germanium and silicon epitaxial growth, the quantity of defect。Compared with the semiconductor device that prior art is formed, adopting in the device that the technical scheme that the present invention includes the cleaning of fluoro-gas dry method is formed, defect situation is significantly improved。After testing, semiconductor device provided by the present invention can reduce the defects count of 60%。
Accordingly, the present invention also provides for a kind of semiconductor device, please continue to refer to Figure 13, it is shown that the schematic diagram of semiconductor device one embodiment of the present invention。
Described semiconductor device includes:
Substrate 200, is formed with multiple groove (not indicating in figure) in described substrate；
It is positioned at the first laying 212 of described channel bottom and sidewall；
It is positioned at the second laying 213 on described first laying 212；
Filling the isolation structure 210 that described groove is formed, described isolation structure 210 is positioned on the second laying；
It is positioned at grid structure 202 on described substrate 200；
Described grid structure 202 surface and sidewall are coated with protective layer 220。
It is formed between isolation structure and the stressor layers in substrate 200 between grid structure, described stressor layers is used for forming source-drain area 205 doped with ion。
Described substrate 200 is the work platforms of subsequent technique。Described substrate 200 material is selected from monocrystal silicon, polysilicon or non-crystalline silicon；Described substrate 200 can also be selected from silicon, germanium, GaAs or silicon Germanium compound；Described substrate 200 is also selected from having epitaxial layer or epitaxial layer silicon-on；Described substrate 200 can also is that other semi-conducting materials, and this is not limited in any way by the present invention。The material of substrate 200 described in the present embodiment is silicon。
The effect of described first laying 212 is to improve the interfacial characteristics between described trenched side-wall and isolation structure 210。In the present embodiment, the material of the first laying 212 is silicon oxide。Described first laying 212 can pass through to aoxidize the sidewall of described groove and bottom formation。Described oxidizing process can also be repaired and be formed, at etching the first laying 212, the etching interface damage in the process of groove, sidewall and the bottom of groove caused。
The effect of described second laying 213 is to reduce trenched side-wall loss in follow-up fluoro-gas dry cleaning process。It should be noted that, adding the fluoro-gas dry method cleaning step of fluoro-gas in the forming process of described semiconductor device, the material of described second laying 213 and the first laying 212 is set to: described in described fluoro-gas dry cleaning process, the removal rate of the second laying 213 is less than the removal rate of described first laying 212。Being formed in flow process at Subsequent semiconductor device, the fluoro-gas dry method cleaning that the fluoro-gas dry method cleaning step of addition adopts is a kind of based on NF3And NH3Gas, be a kind of etching technics for oxide。Adding described fluoro-gas dry method cleaning step when device is formed in flow process, the loss of isolation structure sidewall can be more than the conventional cleaning process adopting diluted hydrofluoric acid, isolation structure in cleaning process likely by excessive etching。
The present embodiment is on the first laying 212 of oxide forming material, and the material arranging the second laying 213 and described second laying 213 is nitride。Compared with oxide; nitride has less etch rate; with material be nitride the second laying 213 for stop-layer; etch cleaner is made to stop on the second laying 213; can effectively reduce the loss of isolation structure sidewall, it is possible in cleaning process, be effectively protected the sidewall of isolation structure。
In the present embodiment, the material of the second laying 213 is silicon nitride, and in fluoro-gas dry method cleaning, the etching selection ratio of silicon oxide and silicon nitride is in the scope of 6:1 to 10:1。Concrete, described second laying 213 can be through the silicon nitride that the mode such as chemical vapour deposition (CVD) and ald is formed。
If it should be noted that the thickness of the second laying 213 is too small, it is difficult to form effective protective effect in follow-up cleaning process。The thickness of optionally described second laying 213 existsAbove。In the present embodiment, the thickness of the second laying 213 of silicon nitride material is
The material of isolation structure 210 is insulant, it is possible to for the one in silicon oxide, fluorine silica glass, the silicate glass of Fluorin doped and tetraethyl orthosilicate, what adopt in the present embodiment is oxide。
Described grid structure 202 includes gate dielectric layer (not indicating) and the gate electrode layer (not indicating) being positioned on gate dielectric layer。The material of gate dielectric layer is silicon oxide or high dielectric constant material, and described gate electrode layer material is polysilicon or metal。In the present embodiment, the material of the gate dielectric layer of described grid structure 202 is silicon oxide, and gate electrode layer material is polysilicon。
Described protective layer 220 for protecting described grid and substrate from damage in subsequent etching processes, and concrete, described protective layer 220 includes the oxide layer 221 and the nitride layer 222 that sequentially form。Described oxide skin(coating) 221 material is silicon oxide, it is possible to by described substrate 2000 and described grid structure 211 surface oxidation technique are obtained。It addition, described nitride layer 222 selects layer when subsequently epitaxial growing germanium silicon material as extension, concrete described nitride layer 222 material is silicon nitride。Additionally, described oxide layer 221 and described nitride layer 222 form grid curb wall subsequently through etching, play the effect of protection grid and isolation source and drain and grid。
In the present embodiment, described semiconductor device is transistor is PMOS, also doped p-type ion in germanium silicon material while epitaxial growth germanium silicon material, concrete, described P type ion is boron ion, the formation process that can adopt selective epitaxial growth forms stressor layers, and doped with boron ion forms source region and drain region 205 in the process of epitaxial growth stressor layers。
Specifically, in the present embodiment, stressor layers is Sigma shape stressor layers, there is the protrusion pointing to channel region most advanced and sophisticated in the middle part of described Sigma shape stressor layers, protruding the germanium silicon material at tip place closer to channel region, bigger compressive stress will be introduced at channel region, can be more beneficial for improving the mobility of channel region carriers。
It should be noted that described semiconductor device provided by the invention can but be not intended to be formed by forming method provided by the present invention。
Although present disclosure is as above, but the present invention is not limited to this。Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range。
Claims (18)
1. the forming method of a semiconductor device, it is characterised in that including:
Form substrate；
Substrate is formed grid structure；
Described substrate and described grid structure cover the protective layer for protecting described grid structure；
Groove is formed in the substrate of grid structure both sides；
Filling semiconductor material in described groove, to form stressor layers；
Described semi-conducting material is carried out ion doping, forms source region and drain region；
After the step of protective mulch, before filling semiconductor material forms the step of stressor layers, the forming method of described semiconductor device also includes: adopt fluoro-gas that described semiconductor device is carried out dry method cleaning。
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described formation substrate
Step include:
Substrate is provided；
Groove is formed in described substrate；
The first laying is covered at described channel bottom and sidewall；
Covering the second laying on described first laying surface, described second backing layer material is set to during described fluoro-gas dry method is cleaned the removal rate of the second laying less than the removal rate of described first laying；
Being formed with fill insulant in the described groove of the first laying and the second laying, to form isolation structure。
3. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the material of described first laying is silicon oxide, and the material of described second laying is silicon nitride。
4. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the thickness of described second laying existsAbove。
5. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the step forming the second laying includes: adopt chemical vapour deposition (CVD), the mode of ald forms described second laying。
6. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described protective layer includes the oxide skin(coating) and the nitride layer that sequentially form。
7. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the described step forming groove in the substrate of grid structure both sides includes:
With described grid structure for mask, the protective layer of described grid structure both sides is carried out the first etching, described protective layer is formed the opening that can expose described substrate surface；
The substrate that described opening is exposed carries out the second etching, forms groove in substrate；
The forming method of described semiconductor device includes: forming protective layer, the first etching, performing, between the second etching and any two step of filling semiconductor material, the step that fluoro-gas dry method described in one or many is cleaned。
8. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described fluoro-gas dry method is cleaned the gas adopted and included NF3And NH3。
9. the forming method of semiconductor device as claimed in claim 8, it is characterised in that NF described in the cleaning of described fluoro-gas dry method3The flow of gas is 35～100sccm, described NH3Flow be 10～400sccm, scavenging period is 1～60s, and radio-frequency power is 5～100W, clean environment air pressure range be 0.5～20Torr；Temperature range is 20～170 DEG C。
10. the forming method of semiconductor device as claimed in claim 1, it is characterised in that fluoro-gas dry method cleaning step includes:
Produce the abluent of plasma state in the reactor chamber；
Utilize described abluent that semiconductor device is carried out；
At the temperature more than 100 DEG C, the semiconductor device through cleaning is heated；
Semiconductor device through heating is annealed。
11. the forming method of semiconductor device as claimed in claim 10, it is characterised in that the described temperature utilizing described abluent that semiconductor device is carried out maintains 35 DEG C。
12. the forming method of semiconductor device as claimed in claim 1, it is characterized in that, after described formation groove, in described groove before the step of filling semiconductor material, the forming method of described semiconductor device also includes: described groove is carried out prerinse；After prerinse step, carry out described fluoro-gas dry method clean。
13. method for forming semiconductor devices as claimed in claim 1, it is characterised in that described to the technique of filling semiconductor material in described groove be selective epitaxial growth process。
14. method for forming semiconductor devices as claimed in claim 13, it is characterized in that, the described step that described semi-conducting material carries out doping formation source region and drain region includes: carries out original position ion doping in the process of selective epitaxial growth process and forms source region and drain region。
15. a semiconductor device, it is characterised in that including:
Substrate, is formed with multiple groove in described substrate；
It is positioned at the first laying on channel bottom and sidewall；
It is positioned at the second laying on described first laying；
It is filled in described groove and is formed at the isolation structure on the second laying；
Being positioned at the grid structure on substrate, described grid structure surface and sidewall are coated with protective layer；
The stressor layers in substrate between described isolation structure and grid structure, is used as source region and drain region doped with ion in described stressor layers。
16. semiconductor device as claimed in claim 15, it is characterized in that, the forming process of described semiconductor device includes the step adopting fluoro-gas dry method to clean, and described second backing layer material is set to during described fluoro-gas dry method is cleaned the removal rate of the second laying less than the removal rate of described first laying。
17. semiconductor device as claimed in claim 15, it is characterised in that the material of the first described laying is silicon oxide, and the material of described second laying is silicon nitride。
18. semiconductor device as claimed in claim 15, it is characterised in that the thickness of the second described laying existsAbove。
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994370A (en) * | 2019-03-04 | 2019-07-09 | 上海华力集成电路制造有限公司 | The method stained in the manufacturing method and removal nitride film of MOS transistor |
| CN110010683A (en) * | 2018-01-04 | 2019-07-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6007641A (en) * | 1997-03-14 | 1999-12-28 | Vlsi Technology, Inc. | Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch |
| US20060141803A1 (en) * | 2004-12-29 | 2006-06-29 | Dongbuanam Semiconductor Inc. | Method of cleaning silicon nitride layer |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
| US20130052809A1 (en) * | 2011-08-25 | 2013-02-28 | United Microelectronics Corporation | Pre-clean method for epitaxial deposition and applications thereof |
| US20130280878A1 (en) * | 2012-04-19 | 2013-10-24 | Tsai-Yu Wen | Semiconductor process |
-
2014
- 2014-11-27 CN CN201410707067.9A patent/CN105702724B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6007641A (en) * | 1997-03-14 | 1999-12-28 | Vlsi Technology, Inc. | Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch |
| US20060141803A1 (en) * | 2004-12-29 | 2006-06-29 | Dongbuanam Semiconductor Inc. | Method of cleaning silicon nitride layer |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
| US20130052809A1 (en) * | 2011-08-25 | 2013-02-28 | United Microelectronics Corporation | Pre-clean method for epitaxial deposition and applications thereof |
| US20130280878A1 (en) * | 2012-04-19 | 2013-10-24 | Tsai-Yu Wen | Semiconductor process |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010683A (en) * | 2018-01-04 | 2019-07-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110010683B (en) * | 2018-01-04 | 2022-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109994370A (en) * | 2019-03-04 | 2019-07-09 | 上海华力集成电路制造有限公司 | The method stained in the manufacturing method and removal nitride film of MOS transistor |
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