CN104465518A - Manufacturing method of grid electrode - Google Patents
Manufacturing method of grid electrode Download PDFInfo
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- CN104465518A CN104465518A CN201310439144.2A CN201310439144A CN104465518A CN 104465518 A CN104465518 A CN 104465518A CN 201310439144 A CN201310439144 A CN 201310439144A CN 104465518 A CN104465518 A CN 104465518A
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- layer
- gate dielectric
- scope
- sacrifice layer
- grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Abstract
A manufacturing method of a grid electrode is characterized by comprising the steps that a substrate is provided, a gate medium layer is formed on the surface of the substrate, baking of reducing gas is carried out on the surface of the gate medium layer, the surface of the gate medium layer is blown, a sacrificial layer is formed on the gate medium layer, the sacrificial layer is removed, a grid electrode layer is formed on the surface of the gate medium layer without the sacrificial layer, and graphical operation is carried out on the grid electrode layer to form the grid electrode. By means of the technical scheme, the manufacturing method of the grid electrode has the advantages that after baking of the reducing gas and blowing are carried out on the surface of the gate medium layer, the sacrificial layer is formed on the surface of the gate medium layer, the sacrificial layer is removed to remove impurities on the surface of the gate medium layer, and therefore the possibility of the defect of protrusions produced when the grid electrode layer is formed on the surface of the gate medium layer in the subsequent steps is reduced.
Description
Technical field
The present invention relates to semiconductor fabrication, be specifically related to a kind of grid making method.
Background technology
Along with the continuous innovation of ic manufacturing technology, the size of the various elements in integrated circuit constantly reduces, and functionalization density constantly increases simultaneously.Under scaled principle, the ic manufacturing technology of development improves production efficiency, reduces manufacturing cost; Meanwhile, the problem of high power consumption is also brought.Had the semiconductor device of low-power consumption feature by application, such as, complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) device has lower power consumption.
In the middle of the process forming grid layer on the semiconductor device, grid layer easily produces bump defects (Bump Defect).
Be the method that existing semiconductor device forms grid as depicted in figs. 1 and 2, this method formed semiconductor material layer 4(as shown in Figure 1 before this on the substrate 1 of semiconductor device), the semiconductor material layer 4 that this method is formed is easy to produce bump defects 3, and then causes on the last grid 5 formed also with described bump defects 3(as shown in Figure 2).
Because feature sizes of semiconductor devices diminishes, the impact of described bump defects on semiconductor device will be more obvious, especially can have influence on the finished product yield of semiconductor device; Now, the requirement for grid layer also uprises accordingly.
At the same time, the uniformity control of thickness between the wafer adopted semiconductor device, the thickness of wafer, the control of size and the condition control overflow such as temperature forming grid layer also become more and more stricter.
Summary of the invention
The problem that the present invention solves is to provide a kind of grid making method, to reduce the bump defects on formed grid layer, comprises the following steps:
Substrate is provided;
Gate dielectric layer is formed at described substrate surface;
Described gate dielectric layer forms sacrifice layer;
Remove described sacrifice layer;
Gate dielectric layer after removing described sacrifice layer forms grid layer on the surface;
Graphical described grid layer is to form grid.
Optionally, the step forming gate dielectric layer comprises, and adopts high dielectric constant material to make described gate dielectric layer.
Optionally, before described gate dielectric layer forms sacrifice layer, also comprise: to described gate dielectric layer surface carry out reducing gas bake, described gate dielectric layer surface is purged in one or multinomial.
Optionally, the step that reducing gas bakes comprises, and adopts hydrogen or the surface of deuterium to described gate dielectric layer to bake.
Optionally, baking temperature, the scope of 400 ~ 800 degrees Celsius, bakes the scope of pressure in 0.1 ~ 700 holder.
Optionally, comprise the step that the surface of gate dielectric layer purges, one or more adopting in hydrogen chloride gas or dichloroethanes gas purge the surface of gate dielectric layer.
Optionally, temperature during purging is the scope of 400 ~ 800 degrees Celsius, and pressure is in the scope of 0.1 ~ 700 holder.
Optionally, the step forming sacrifice layer comprises, and described sacrifice layer is amorphous silicon sacrifice layer or polysilicon sacrificial layer.
Optionally, the step forming sacrifice layer comprises, and adopts silane gas or b silane gas or dichlorosilane gas to form described sacrifice layer.
Optionally, the step forming sacrifice layer comprises, and adopts the method for low-pressure chemical vapor deposition to form described sacrifice layer.
Optionally, adopt the step of low-pressure chemical vapor deposition to comprise, depositing temperature during low-pressure chemical vapor deposition is the scope of 450 ~ 750 degrees Celsius, and deposition pressure is in the scope of 0.1 ~ 300 holder.
Optionally, form the step of sacrifice layer and comprise, the thickness of described sacrifice layer is in the scope of 50 ~ 300 dusts.
Optionally, the step removing described sacrifice layer comprises, and adopts wet etching to remove described sacrifice layer.
Optionally, adopt tetramethyl ammonium hydroxide solution to remove described sacrifice layer, the concentration of described tetramethyl ammonium hydroxide solution is 2.37%, and etch temperature is the scope of 60 ~ 70 degrees Celsius, and etching period was at 10 ~ 60 seconds.
Optionally, adopt ammonium hydroxide to remove described sacrifice layer, etch temperature is the scope of 60 ~ 70 degrees Celsius, and etching period was the scope of 10 ~ 60 seconds.
Optionally, adopt hydrogen chloride to remove described sacrifice layer, etch temperature, the scope of 450 ~ 750 degrees Celsius, etches the scope of pressure in 0.1 ~ 300 holder.
Optionally, described grid layer is formed on wafer, and the step forming grid layer comprises: in cavity, arrange single wafer, described single wafer forms grid layer; Or, multiple wafer is set in cavity or boiler tube, described multiple wafer forms grid layer simultaneously.
Optionally, the step forming grid layer comprises, and adopts silane gas or b silane gas or dichlorosilane gas to form described grid layer.
Optionally, form the step of grid layer and comprise, adopt the method for low-pressure chemical vapor deposition to form described sacrifice layer, temperature during deposition is the scope of 450 ~ 750 degrees Celsius, and deposition pressure is in the scope of 0.1 ~ 300 holder.
Optionally, described grid layer is amorphous silicon grid layer or polycrystalline silicon gate layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form one deck sacrifice layer on the surface of described gate dielectric layer, and remove described sacrifice layer, the impurity on the surface of gate dielectric layer is removed, reduce the probability producing bump defects in subsequent step when described gate dielectric layer surface forms grid layer.
Further, adopt hydrogen or deuterium to bake described gate dielectric layer surface, the impurity such as carbon, oxygen on described gate dielectric layer surface can be removed.
Further, adopt hydrogen chloride gas or dichloroethanes gas to purge described gate dielectric layer surface, the metal impurities on described gate dielectric layer surface can be removed.
Further, reducing gas is carried out to the surface of gate dielectric layer and bakes and purge, thus remove the residual impurity on described gate dielectric layer surface further.
Further, wet etching is good for the selectivity of described sacrifice layer, adopts wet etching to remove described sacrifice layer can remove described sacrifice layer quick and completely, and little for the damage of the gate dielectric layer below sacrifice layer.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the schematic diagram that prior art makes grid;
Fig. 3 is the schematic flow sheet of grid making method one embodiment of the present invention;
Fig. 4 to Figure 10 is the schematic diagram that grid making method one embodiment of the present invention forms grid.
Embodiment
The method of existing making grid easily forms bump defects on grid layer, and then the performance of the last semiconductor device formed of impact.
By analysis, in the process forming described grid layer, on the growing surface forming grid layer, described bump defects is formed in the position remaining impurity more, reason is that these residual impurity easily make sedimental nucleation speed accelerate and produce accumulation, and then produces described bump defects.
Further, described bump defects, by the middle of the patterning step of the grid layer after bringing into, makes the final grid formed also with described bump defects, has had a strong impact on the performance of whole semiconductor device.
In order to solve the problems of the technologies described above, the invention provides a kind of grid making method.
Be illustrated in figure 3 the flow chart of grid making method one embodiment of the present invention:
Step S1, provides substrate;
Step S2, forms gate dielectric layer at described substrate surface;
Step S3, carries out reducing gas to described gate dielectric layer surface and bakes;
Step S4, purges described gate dielectric layer surface;
Step S5, described gate dielectric layer forms sacrifice layer;
Step S6, removes described sacrifice layer;
Step S7, the gate dielectric layer after removing described sacrifice layer forms grid layer on the surface;
Step S8, graphical described grid layer is to form grid.
Step and purge step is baked by above-mentioned reducing gas, the impurity remaining in described gate dielectric layer surface can be removed comparatively thoroughly, by described and form the step of described sacrifice layer, the impurity remaining in described gate dielectric layer surface can be adsorbed further, impurity can be removed together with described sacrifice layer one is logical by removing described sacrifice layer, for the growth of the described grid layer of subsequent step provides condition, and then reduce the probability producing described bump defects when forming grid layer in subsequent step.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
See Fig. 4, perform step S1, substrate 100 is provided.
In the present embodiment, described substrate 100 adopts silicon substrate, but described substrate 100 can also adopt other semi-conducting material, does not do any restriction to this present invention.
In the present embodiment, also comprise step by step following:
At described substrate 100 through shallow-trench isolation technology (Shallow Trench Isolation, STI) processing, form shallow trench isolation areas, be filled with spacer medium material 101 in described area of isolation, to form shallow groove isolation structure.
It should be noted that, described step by step only for providing condition for forming semiconductor device in the present embodiment, the present invention does not limit step by step to described, can also be directly to carry out follow-up step without shallow-trench isolation.
Continue, with reference to Fig. 4, to perform step S2, form gate dielectric material at described substrate surface;
After graphical to described gate dielectric material, remove the part gate dielectric material covered above described spacer medium material 101, and then obtain as shown in Figure 4, only covering the gate dielectric layer 110 on described substrate 100 surface.
In the present embodiment, described gate dielectric layer 110 adopts the oxide material titanium nitride (TiN) with high-k.But described gate dielectric layer 110 can also adopt the oxide material of other high-k, and the present invention does not limit this.
Meanwhile, whether the present invention does not limit adopting the material with high-k to form described gate dielectric layer 110.
As shown in Figure 5, step S3, carries out reducing gas 130 to the surface of described gate dielectric layer 110 and bakes.Reducing gas 130 reacts with the impurity of described gate dielectric layer 110 remained on surface, to remove these impurity, for the growth of grid layer in subsequent step provides a comparatively clean surface.
Described impurity comes from the process equipment (as etching machine, cleaning machine etc.) formed before substrate usually, or comes from surrounding environment, and described impurity mainly comprises:
The impurity such as carbon, oxonium ion;
Described gate dielectric layer 110 surface is owing to being oxidized the natural oxidizing layer (native oxide) produced;
The impurity such as trace metal ion (trace metal) and metal oxide.
In the present embodiment, described reducing gas 130 is hydrogen, the benefit adopting hydrogen 130 to bake described gate dielectric layer 110 is, described hydrogen has stronger reproducibility and good carrier gas characteristic (Carrier Gas), adopt hydrogen as reducing gas, the surperficial above-mentioned impurity of described gate dielectric layer 110 can be removed than more completely.
But described reducing gas 130 is not limited in hydrogen, can also be as deuterium (D
2) etc. the stronger gas of reproducibility.
In the present embodiment, temperature when baking remains in the scope of 400 ~ 800 degrees Celsius, baking pressure remains in the scope of 0.1 ~ 700 holder, too low or the too little pressure of temperature will cause reducing degree not enough, and temperature is too high or pressure is excessive, may have influence on the characteristic of substrate 100 and gate dielectric layer 110 itself.
With reference to Fig. 6, perform step S4, the surface of described gate dielectric layer 110 is purged, to remove the impurity being attached to described gate dielectric layer 110 surface further; These impurity are some trace metal ion impurity mainly, these trace metal ion impurity and purge gas 140 react, change metallic compound into and taken away by described purge gas 140, providing a comparatively clean growing surface for subsequent step forms grid layer.
In the present embodiment, hydrogen chloride gas (HCL) surface to gate dielectric layer is adopted to purge, to remove described trace metal ion comparatively rapidly and thoroughly.Described trace metal ion impurity and hydrogen chloride gas precursor reactant, such as, sodium ion and hydrogen chloride gas precursor reactant generate sodium chloride, and are taken away by described hydrogen chloride gas.
But the present invention does not limit purge gas kind, described purge gas can also be that other gas that can react with described trace metal ion is as dichloroethylene gas (DCE, Si
2-H
2cl
2).
In the present embodiment, maintain the temperature in the scope of 400 ~ 800 degrees Celsius in purge, keep pressure in the scope in 0.1 ~ 700 holder, so that comparatively fully remove the trace metal ion (trace metal) remaining in described gate dielectric layer 110 surface simultaneously.
Especially, it should be noted that, describedly step S3 that reducing gas bakes is carried out to described gate dielectric layer surface and the described order to the step S4 that described gate dielectric layer surface purges can be exchanged mutually, that is, can be the present embodiment first carry out step S3, carry out step S4 again, also can be first carry out step S4, carry out step S3.Because the object of these two steps is the impurity removed on described gate dielectric layer 110 surface, the order of exchanging two step S3 and S4 can not affect the formation of subsequent gate layer.
As shown in Figure 7, perform step S5, described gate dielectric layer is formed sacrifice layer 150, and described sacrifice layer 150 is for adsorbing the impurity remained on described gate dielectric layer 110.
In the present embodiment, silane (SiH is adopted
4) gas forms described sacrifice layer 150, in addition, in other embodiments of the invention, can also adopt disilane (Si
2h
6) or dichlorosilane (H
2cl
2si, DCS) gas forms described sacrifice layer 150.
In the present embodiment, the sacrifice layer 150 of formation is polysilicon (poly-Si) sacrifice layer, but the present invention is not restricted this, and described sacrifice layer 150 can also be the sacrifice layer as other semi-conducting materials such as amorphous silicon (a-Si) sacrifice layers.
Owing to carrying out to described gate dielectric layer 110 surface step (step S3) that reducing gas bakes before and removing the impurity on described gate dielectric layer 110 surface the step (step S4) that gate dielectric layer 110 surface purges, but still likely there is the impurities left of minority on described gate dielectric layer 110 surface, described sacrifice layer 150 is when being formed, the impurity of these minorities can enter into described sacrifice layer 150 and have an impact to the formation of described sacrifice layer 150, the nucleation rate of described sacrifice layer 150 is accelerated, and then produce accumulation, therefore, bump defects 50 as shown in Figure 7 may be formed on the surface of sacrifice layer 150.
Shown in figure 8, perform step S6, remove described sacrifice layer 150(and comprise the bump defects 50 that sacrifice layer 150 is formed), with the Impurity removal adsorbed by sacrifice layer 150, make that the surface of described gate dielectric layer 110 does not have residual impurity.
In the present embodiment, remove described sacrifice layer 150 by wet etching, wet etching has good selectivity, can remove flood sacrifice layer 150 fast, and very little for the damage of the gate dielectric layer 110 of below.
But the present invention does not limit for the method removing described sacrifice layer 150, sacrifice layer 150 as described in the removals such as additive method (as dry etching) can also be adopted.
In the present embodiment, the etchant of wet etching adopts tetramethyl ammonium hydroxide solution (TMAH), and the concentration of described tetramethyl ammonium hydroxide solution is 2.37%, and temperature during etching remains on the scope of 60 ~ 70 degrees Celsius, and etching period was at 10 ~ 60 seconds.
Adopt the benefit of tetramethyl ammonium hydroxide solution to be, tetramethyl ammonium hydroxide solution has strong basicity, and etching process is comparatively stable, and can remove described sacrifice layer 150 fast and effectively.
But the present invention does not limit etchant and etch temperature and etching period, in other embodiments of the invention, can adopt but be not limited to following methods:
Adopt ammonium hydroxide (NH
4oH) remove described sacrifice layer 150, temperature during etching remains on the scope of 60 ~ 70 degrees Celsius, and etching period was the scope of 10 ~ 60 seconds.
Adopt hydrogen chloride (HCL) to remove described sacrifice layer, temperature during etching remains on the scope of 450 ~ 750 degrees Celsius, and etching pressure remains on the scope of 0.1 ~ 300 holder.
As shown in Figure 9, perform step S5, the gate dielectric layer 110 after removing described sacrifice layer 150 forms grid layer 120 on the surface.
In the present embodiment, the step forming grid layer 120 can be carried out in the cavity being provided with single-wafer.But, in other embodiments also can by batch instrument as boiler tube (furnace) etc., multiple wafer is set simultaneously and on these wafers on form described grid layer 120, the present invention is not restricted this.
In the present embodiment, silane (SiH is adopted
4) gas forms described grid layer 120, in addition, in other embodiments of the invention, can also adopt disilane (Si
2h
6) or dichlorosilane (H
2cl
2si, DCS) gas forms described grid layer 120, and the present invention is not restricted this.
In the present embodiment, the described grid layer 120 of formation is polysilicon (Poly-Si), but the present invention does not limit this, and the described grid layer 120 of formation can also be other grid layer as other semi-conducting materials such as amorphous silicons (a-Si).
Continue reference with reference to figure 9, in the present embodiment, adopt low-pressure chemical vapor deposition (Low PressureChemical Vapor Deposition, LPCVD) method forms described grid layer 120, and what adopt the benefit of LPCVD to be can be formed under lower air pressure has good stepcoverage performance and the grid layer 120 of electrology characteristic.
But, the present invention does not limit for the deposition process forming described grid layer, described grid layer 120 can also be formed by other deposition processs such as Films Prepared by APCVDs (Atmospheric, Pressure Chemical VaporDeposition, APCVD).
In the present embodiment, temperature during deposition remains in the scope of 450 ~ 750 degrees Celsius, and deposition pressure remains in the scope of 0.1 ~ 300 holder, carries out depositing the grid layer 120 being beneficial to and being formed and be evenly distributed in described temperature and pressure range.
Owing to having carried out to described gate dielectric layer 110 surface the preliminary treatment that reducing gas bakes and purge in step before, and form sacrifice layer 150 and adsorb the impurity remained on gate dielectric layer 150, after the described sacrifice layer 150 of removal, the remained on surface impurity of gate dielectric layer 110 is removed, and then the probability that the grid layer 120 making deposition be formed occurs in crystal grain accumulation reduces, and grid layer 120 will significantly reduce with the probability of described bump defects 50.
Shown in Figure 10, perform step S6, graphical described grid layer 120 is to form grid 121.
But the present invention does not do any restriction to this, other graphic methods can also be adopted to form described grid 121.
It should be noted that in addition, above step can be carried out in same chamber, and also can carry out at different chamber respectively, the present invention does not limit this.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a grid making method, is characterized in that, comprises the following steps:
Substrate is provided;
Gate dielectric layer is formed at described substrate surface;
Described gate dielectric layer forms sacrifice layer;
Remove described sacrifice layer;
Gate dielectric layer after removing described sacrifice layer forms grid layer on the surface;
Graphical described grid layer is to form grid.
2. the method for claim 1, is characterized in that, the step forming gate dielectric layer comprises, and adopts high dielectric constant material to make described gate dielectric layer.
3. the method for claim 1, is characterized in that, before described gate dielectric layer forms sacrifice layer, also comprises: to described gate dielectric layer surface carry out reducing gas bake, described gate dielectric layer surface is purged in one or multinomial.
4. method as claimed in claim 3, it is characterized in that, the step that reducing gas bakes comprises, and adopts hydrogen or the surface of deuterium to described gate dielectric layer to bake.
5. method as claimed in claim 4, is characterized in that, baking temperature, the scope of 400 ~ 800 degrees Celsius, bakes the scope of pressure in 0.1 ~ 700 holder.
6. method as claimed in claim 3, is characterized in that, comprise the step that the surface of gate dielectric layer purges, and one or more adopting in hydrogen chloride gas or dichloroethanes gas purge the surface of gate dielectric layer.
7. method as claimed in claim 6, is characterized in that, temperature during purging is the scope of 400 ~ 800 degrees Celsius, and pressure is in the scope of 0.1 ~ 700 holder.
8. the method for claim 1, is characterized in that, the step forming sacrifice layer comprises, and described sacrifice layer is amorphous silicon sacrifice layer or polysilicon sacrificial layer.
9. method as claimed in claim 8, is characterized in that, the step forming sacrifice layer comprises, and adopts silane gas or b silane gas or dichlorosilane gas to form described sacrifice layer.
10. the method as described in any one of claim 1 or 8 or 9, is characterized in that, the step forming sacrifice layer comprises, and adopts the method for low-pressure chemical vapor deposition to form described sacrifice layer.
11. methods as claimed in claim 10, is characterized in that, adopt the step of low-pressure chemical vapor deposition to comprise, and depositing temperature during low-pressure chemical vapor deposition is the scope of 450 ~ 750 degrees Celsius, and deposition pressure is in the scope of 0.1 ~ 300 holder.
12. methods stated as claim 1, is characterized in that, form the step of sacrifice layer and comprise, and the thickness of described sacrifice layer is in the scope of 50 ~ 300 dusts.
13. the method for claim 1, is characterized in that, the step removing described sacrifice layer comprises, and adopt wet etching to remove described sacrifice layer.
14. methods as claimed in claim 13, is characterized in that, adopt tetramethyl ammonium hydroxide solution to remove described sacrifice layer, the concentration of described tetramethyl ammonium hydroxide solution is 2.37%, and etch temperature is the scope of 60 ~ 70 degrees Celsius, and etching period was at 10 ~ 60 seconds.
15. methods as claimed in claim 13, is characterized in that, adopt ammonium hydroxide to remove described sacrifice layer, and etch temperature is the scope of 60 ~ 70 degrees Celsius, and etching period was the scope of 10 ~ 60 seconds.
16. methods as claimed in claim 13, is characterized in that, adopt hydrogen chloride to remove described sacrifice layer, and etch temperature, the scope of 450 ~ 750 degrees Celsius, etches the scope of pressure in 0.1 ~ 300 holder.
17. the method for claim 1, is characterized in that, described grid layer is formed on wafer, and the step forming grid layer comprises: in cavity, arrange single wafer, described single wafer forms grid layer; Or, multiple wafer is set in cavity or boiler tube, described multiple wafer forms grid layer simultaneously.
18. the method for claim 1, is characterized in that, the step forming grid layer comprises, and adopt silane gas or b silane gas or dichlorosilane gas to form described grid layer.
19. the method for claim 1, it is characterized in that, the step forming grid layer comprises, and adopts the method for low-pressure chemical vapor deposition to form described sacrifice layer, temperature during deposition is the scope of 450 ~ 750 degrees Celsius, and deposition pressure is in the scope of 0.1 ~ 300 holder.
20. methods as described in any one of claim 1 or 19, it is characterized in that, described grid layer is amorphous silicon grid layer or polycrystalline silicon gate layer.
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| CN201310439144.2A CN104465518B (en) | 2013-09-24 | 2013-09-24 | Grid making method |
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| CN201310439144.2A CN104465518B (en) | 2013-09-24 | 2013-09-24 | Grid making method |
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| CN104465518B CN104465518B (en) | 2017-09-22 |
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| CN106444365A (en) * | 2015-08-12 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Wafer etching control method and wafer manufacturing method |
| CN115157680A (en) * | 2022-06-24 | 2022-10-11 | 芯体素(杭州)科技发展有限公司 | 3D printing-based grating preparation method and 3D printing equipment |
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| CN115157680A (en) * | 2022-06-24 | 2022-10-11 | 芯体素(杭州)科技发展有限公司 | 3D printing-based grating preparation method and 3D printing equipment |
| CN115157680B (en) * | 2022-06-24 | 2023-09-12 | 芯体素(杭州)科技发展有限公司 | Grating preparation method based on 3D printing and 3D printing equipment |
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|---|---|
| CN104465518B (en) | 2017-09-22 |
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