CN105655321A - 电子封装及其制作和使用方法 - Google Patents

电子封装及其制作和使用方法 Download PDF

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Publication number
CN105655321A
CN105655321A CN201510863302.6A CN201510863302A CN105655321A CN 105655321 A CN105655321 A CN 105655321A CN 201510863302 A CN201510863302 A CN 201510863302A CN 105655321 A CN105655321 A CN 105655321A
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CN
China
Prior art keywords
layer
micro
hole
conformal
electronic packaging
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CN201510863302.6A
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English (en)
Inventor
S.史密斯
C.J.卡普斯塔
G.A.福曼
E.P.戴维斯
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General Electric Co
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General Electric Co
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Application filed by General Electric Co filed Critical General Electric Co
Publication of CN105655321A publication Critical patent/CN105655321A/zh
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Abstract

本发明题为电子封装及其制作和使用方法。提供电子封装及其制作方法。该电子封装包含介电层以及设置在介电层的至少一部分上的共形掩蔽层。该电子封装进一步包含设置在掩蔽层的至少一部分上的布线层以及至少部分设置在共形掩蔽层和布线层中的微通孔。此外，布线层的至少一部分形成微通孔的至少一部分中的共形导电层。另外，共形掩蔽层配置成限定微通孔的尺寸。该电子封装进一步包含操作上耦合到微通孔的半导体小片。

Description

电子封装及其制作和使用方法
技术领域
本发明是在空军研究实验室所授予的授权号FA9453-09-C-0305下以政府支持进行。政府具有本发明中的某些权利。
背景技术
本说明书的实施例涉及电子封装，以及更具体来说涉及形成电子封装中的微通孔和互连。
电子装置领域中的技术进步在近年来已经历了巨大增长。例如，虽然蜂窝电话变得更小并且更轻，但是它们的特征和能力同时不断扩大。这已引起这类装置中所发现的电气组件的复杂性和操作的增加以及可用于这类组件的空间量的减小。若干难题起因于电气组件的复杂性的这种增加以及可用空间量的减小。例如，基于空间限制，电路板的尺寸减小到板的布线密度可被约束和限制成低于所希望量的程度。随着集成电路变得日益更小并且产生更好的操作性能，用于集成电路(IC)封装的封装技术对应地从引线封装演进到基于层压的球栅阵列(BGA)封装，并且最终演进到芯片级封装(CSP)。IC芯片封装技术的进步通过对于实现更好性能、更大小型化和更高可靠性的不断增加的需要来驱动。新的封装技术必须进一步为了大规模制造的目的提供批量生产的可能性，由此允许规模经济。
此外，由于IC封装的小尺寸和复杂性，用于制作IC封装的过程通常费用高并且费时。另外，用来创建所希望的双面输入/输出(I/O)系统的附加再分布层的使用增加处理步骤的数量，从而进一步增加制造过程的成本和复杂性。此外，增加每一装置的I/O增加每一装置所要求的布线密度和通孔数量。
发明内容
按照本说明书的方面，提供一种电子封装。该电子封装包含介电层以及设置在介电层的至少一部分上的共形掩蔽层。该电子封装进一步包含设置在共形掩蔽层的至少一部分上的布线层以及至少部分设置在共形掩蔽层和布线层中的微通孔。此外，布线层的至少一部分形成微通孔的至少一部分中的共形导电层。另外，共形掩蔽层配置成限定微通孔的尺寸。该电子封装进一步包含操作上耦合到微通孔的半导体小片。
按照本说明书的另一个方面，提供一种具有电子封装的电子系统。电子封装包含介电层、设置在介电层的至少一部分上的共形掩蔽层以及设置在共形掩蔽层的至少一部分上的布线层。此外，电子封装包含至少部分设置在共形掩蔽层和布线层中的多个微通孔。此外，布线层的至少一部分形成多个微通孔的微通孔的至少一部分中的共形导电层。该电子系统进一步包含多个半导体小片，其中多个半导体小片的一个或多个半导体小片耦合到多个微通孔的对应微通孔。
按照本说明书的又一个方面，包含一种制作电子封装的方法。该方法包含提供设置在处理框架上的介电层，其中介电层包含第一侧和第二侧。此外，该方法包含提供设置在介电层的第二侧上的共形掩蔽层，其中共形掩蔽层包含与一个或多个微通孔对应的一个或多个图案。此外，该方法包含将半导体小片耦合到介电层的第一侧的一部分，使得半导体小片与一个或多个图案对齐。另外，该方法包含有选择地去除与共形掩蔽层中的一个或多个图案对应的介电层的部分。另外，该方法包含将共形导电层设置在与一个或多个微通孔对应的一个或多个图案的至少一部分中以形成一个或多个微通孔，其中共形掩蔽层配置成限定一个或多个微通孔的尺寸。此外，该方法包含有选择地去除介电层的部分，以形成一个或多个微通孔。
技术方案1：一种电子封装，包括：
介电层；
共形掩蔽层，设置在所述介电层的至少一部分上；
布线层，设置在所述共形掩蔽层的至少一部分上；
微通孔，至少部分设置在所述共形掩蔽层和所述布线层中，其中所述布线层的至少一部分形成所述微通孔的至少一部分中的共形导电层，并且其中所述共形掩蔽层配置成限定所述微通孔的尺寸；以及
半导体小片，耦合到所述微通孔。
技术方案2：如技术方案1所述的电子封装，其中，所述共形掩蔽层包括导电材料。
技术方案3：如技术方案1所述的电子封装，其中，所述导电材料包含铜、钛、铝、镍、金、钨铬钽或者其组合。
技术方案4：如技术方案1所述的电子封装，其中，所述微通孔的至少一部分设置在所述共形掩蔽层、所述布线层和所述介电层中。
技术方案5：如技术方案1所述的电子封装，其中，所述微通孔是盲微通孔。
技术方案6：如技术方案1所述的电子封装，其中，所述微通孔的直径在从大约5微米到大约50微米的范围中。
技术方案7：如技术方案1所述的电子封装，其中，所述布线层配置成设置在所述共形掩蔽层上。
技术方案8：如技术方案1所述的电子封装，其中，所述布线层包括钛、铜、镍、金、铬、铝、钛-钨或者其组合。
技术方案9：如技术方案1所述的电子封装，其中，所述共形掩蔽层和所述布线层形成布线互连。
技术方案10：一种电子系统，包括：
电子封装，包括：
介电层；
共形掩蔽层，设置在所述介电层的至少一部分上；
布线层，设置在所述共形掩蔽层的至少一部分上；
多个微通孔，至少部分设置在所述共形掩蔽层和所述布线层中，其中所述布线层的至少一部分形成所述多个微通孔的微通孔的至少一部分中的共形导电层；以及
多个半导体小片，其中所述多个半导体小片的一个或多个半导体小片耦合到所述多个微通孔的对应微通孔。
技术方案11：如技术方案10所述的电子系统，其中，所述多个微通孔是盲微通孔。
技术方案12：如技术方案10所述的电子系统，其中，所述共形掩蔽层和所述布线层的组合形成所述电子系统中所配置的布线互连。
技术方案13：如技术方案10所述的电子系统，其中，所述多个微通孔的平均直径在从大约5微米到大约100微米的范围中。
技术方案14：一种制作电子封装的方法，包括：
提供设置在处理框架上的介电层，其中所述介电层包括第一侧和第二侧；
提供设置在所述介电层的所述第二侧上的共形掩蔽层，其中所述共形掩蔽层包括与一个或多个微通孔对应的一个或多个图案；
将半导体小片耦合到所述介电层的所述第一侧的一部分，使得所述半导体小片与所述一个或多个图案对齐；
有选择地去除所述介电层的部分；以及
将共形导电层设置在与所述一个或多个微通孔对应的所述一个或多个图案的至少一部分中，以形成所述一个或多个微通孔，其中所述共形掩蔽层配置成限定所述一个或多个微通孔的尺寸。
技术方案15：如技术方案14所述的方法，其中，提供所述共形掩蔽层的步骤包括：
将所述共形掩蔽层的材料的层设置在所述介电层的所述第二侧的至少一部分上；以及
对所述共形掩蔽层的所述材料的所述层进行构图，以形成所述共形掩蔽层。
技术方案16：如技术方案14所述的方法，进一步包括：
将经构图抗蚀层设置在所述共形掩蔽层的所述材料的所述层的至少一部分上；以及
去除与所述一个或多个微通孔的所述一个或多个图案对应的所述共形掩蔽层的所述材料的所述层的暴露部分。
技术方案17：如技术方案14所述的方法，其中，有选择地去除所述介电层的所述部分包括对所述介电层的所述部分进行激光钻孔。
技术方案18：如技术方案14所述的方法，进一步包括去除所述抗蚀层。
技术方案19：如技术方案14所述的方法，其中，将所述共形导电层设置在与所述一个或多个微通孔对应的所述一个或多个图案的至少一部分中包括在所述共形掩蔽层上电镀所述共形导电层。
技术方案20：如技术方案14所述的方法，进一步包括对所述共形导电层进行构图以形成布线层，并且有选择地去除所述共形掩蔽层和所述布线层的部分以形成布线互连。
附图说明
在参照附图阅读以下详细的描述，将会更好地了解本公开的这些及其他特征、方面和优点，附图中，相似标号贯穿附图表示相似部件，附图包括：
图1-9是按照本说明书的方面、制作具有微通孔的电子封装的示范方法中所涉及的步骤的示意表示；
图10是按照本说明书的方面、电子封装中所采用的微通孔的顶视图，其中微通孔使用图1-9所表示的方法来制作；
图11是按照本说明书的方面、图10的电子封装中的电气布线的顶视图；
图12是按照本说明书的方面、具有微通孔的示范电子封装的一部分的截面图；以及
图13是按照本说明书的方面、具有多个小片的电子系统的一部分的截面图。
具体实施方式
本说明书的实施例涉及具有共形掩蔽层的电子封装及制作其的方法。在某些实施例中，电子封装的共形掩蔽层的至少一部分与电子封装中存在的一个或多个微通孔的至少一部分一致。此外，共形掩蔽层可由导电材料来制成，并且配置成形成电子封装中的电子电路或热通路的一部分。一旦共形掩蔽层限定通孔尺寸，共形掩蔽层可集成到电子封装中，以形成其他结构。作为示例，共形掩蔽层可配置成充当地线层（ground plane）、电源、信号源、屏蔽层或者其组合。在其中共形掩蔽层配置成充当屏蔽层的情况下，共形掩蔽层可配置成提供针对射频和/或电磁辐射的至少一部分的局部屏蔽。
在某些实施例中，电子封装可用来将一个或多个半导体装置(例如半导体小片)耦合到一个或多个电子组件。在一个示例中，电子封装可易于耦合到印刷电路板(PCB)，用于提供印刷电路板与其他电子组件之间的电气连接。在一个实施例中，电子封装可用来根据微通孔的小尺寸和间距来提供高密度电气连接。在某些实施例中，微通孔的平均直径可在从大约5微米到大约50微米的范围中。在其他某些实施例中，微通孔的平均直径可在从大约5微米到大约25微米或者从大约10微米到大约50微米的范围中。此外，在一些实施例中，两个相邻设置微通孔之间的平均间距可在从大约10微米到大约100微米的范围中。此外，在一个实施例中，微通孔可以是贯穿微通孔或者盲微通孔。如本文所使用的术语“贯穿微通孔”用来指的是通过一层并且没有底端的微通孔。此外，如本文所使用的术语“盲微通孔”用来指的是具有与相邻设置的或者基础层或集成电路(IC)焊盘电气接触的底端的微通孔。在一个实施例中，微通孔可不具有设置在半导体装置的对应焊盘与微通孔之间的任何壁或层。在一些实施例中，微通孔可按照线性布置、阵列或者任何其他几何或非几何布置来布置。在某些实施例中，采用微通孔的电子封装可与常规小片接合技术(例如但不限于丝焊、倒装芯片技术以及将半导体小片的电子输入/输出(I/O)焊盘连接到电子封装的其他方法)兼容。
图1-9是示出按照本说明书的方面、制作具有共形掩蔽层的电子封装的方法的步骤的示意图。图1是设置在处理框架104上的高密度电子封装(图1中未示出)的电介质或介电层102的示意表示100。此外，在一些实施例中，介电层102可由柔性的聚合材料来制成。在一个实施例中，介电层102可由诸如但不限于聚酰亚胺或者基于聚酰亚胺的材料的介电材料来形成。在具体示例中，介电层102可由Kapton®来制成。在某些实施例中，例如，介电层102可具有大约25微米的厚度。此外，处理框架104可由导电材料(例如铝、铜、陶瓷金属合成物、镍、银、不锈钢或其他适合材料或者其组合)来制成。在一个示例中，处理框架104可由Kovar®来制成。另外，处理框架104可以或者可以不形成所产生电路或电子封装的一部分。
可选地，如图2的示意表示200所图示，粘合材料的层(未示出)可应用到介电层102的第一侧108的至少一部分上。另外，地层109可设置在介电层102的第二侧110上。地层109可由导电层来制成。在非限制性示例中，地层109可由铜制成。此外，地层109可以是构图层。此外，在一些实施例中，相同或不同的粘合剂的另一层可应用在地层109和/或介电层102的第二侧110的暴露部分上。在一个示例中，粘合层可由非导电环氧树脂来制成。可注意，可在介电层102上形成共形掩蔽层之前或之后设置地层109。
另外，共形掩蔽层112(参见图4)可设置在介电层102的第一侧108上。备选地，在其中粘合层设置在介电层102上的情况下，共形掩蔽层112可设置在粘合层上。此外，共形掩蔽层112可在粘合层的固化之后设置在粘合层上。在下文描述涉及其中共形掩蔽层112直接设置在介电层102上的情况。在某些实施例中，可通过首先将共形掩蔽层112的材料的层113设置在介电层102的至少一部分上，将共形掩蔽层112设置在介电层102上。随后，可处理共形掩蔽层112的材料的层113，以形成共形掩蔽层112。在一个示例中，层113可构图，以有选择地去除层113的部分，以形成共形掩蔽层112。此外，图案可在层113中使用诸如但不限于光刻、蚀刻(例如激光蚀刻)或者它们两者的技术来形成。虽然未图示，但是可注意，共形掩蔽层112可设置在介电层102的第一侧108和第二侧110上。在某些实施例中，可通过诸如但不限于涂层、电镀、溅射、喷射、金属化、气相沉积、粘贴、浸涂或者其组合的技术，在介电层102的部分上沉积共形掩蔽层112的材料层113。共形掩蔽层112的材料的非限制性示例可包含一个或多个导电材料，例如但不限于铜、银、铝、镍、铬、钛、钽或者其组合。
现在参照图3的示意表示300，可通过将层113构图来将层113变换成共形掩蔽层112(参见图4)，以形成层113和介电层102中的微通孔122(参见图9)的至少一部分。要形成与层113中的微通孔122对应的图案，可提供具有图案116的抗蚀层114。在一个实施例中，可通过将抗蚀层114放置在层113上，在层113上提供抗蚀层114，其中抗蚀层114包含图案116。此外，抗蚀层114可使用诸如喷射、涂抹、物理气相沉积、化学气相沉积、溅射、浸涂等的已知沉积技术来沉积。此外，抗蚀层114可包含图案116，使得图案116与预计在层113和介电层102中形成的微通孔的图案类似。具体来说，抗蚀层114中的图案116可对应于在所产生电子封装、例如电子封装900(参见图9)中是合乎需要的微通孔122的位置和尺寸。在一个实施例中，抗蚀层114可配置成在光刻期间充当光致抗蚀剂掩模，以将抗蚀层114的图案116转化到层113。
接下来，如图4的示意表示中400所图示，层113可借助于抗蚀层114、使用蚀刻来构图。因此，可有选择地去除与抗蚀层114的图案116对应的层113的至少一部分，以形成层113中的图案117。具有图案117的这个层113称为共形掩蔽层112。此外，图案117构成在共形掩蔽层112和介电层102中形成的微通孔的一部分。此外，如图5的示意表示500所图示，在形成层113中的图案117之后，可去除抗蚀层114。在一个示例中，抗蚀层114可通过干式或湿式蚀刻被去除。
另外，如图6的示意表示600所图示，具有半导体小片118的有源表面120内附连或包含的多个接触结点或焊盘(未示出)的半导体小片118可耦合或附连到介电层102的第二侧110。具体来说，半导体小片118可附连到具有图案117的介电层102的部分。作为示例，如图6所图示，半导体小片118与共形掩蔽层112中形成的图案117对齐。在一些实施例中，半导体小片118可使用设置在半导体小片118与介电层102之间的粘合层来耦合到介电层102。
虽然图6-9将半导体小片118图示为耦合到介电层102，但是预想除了半导体小片118之外的其他电子组件、例如有源或无源电子装置也可附连到介电层102和/地层109的一部分。此外，虽然针对单个小片来解释图6-9，但是本说明书的方法可扩展到耦合多个小片，包含小片阵列，其中小片阵列的一个或多个小片可耦合到电子封装中的相应微通孔。因此，虽然未图示出，但是预期多个这类电子组件可附连到介电层102，使得可形成多组件模块或层。此外，在其中采用多个小片的实施例中，小片的接触焊盘可与表示将来微通孔位置的位置的图案117对齐，以供微通孔与半导体小片之间的电连接。
可理解，随着半导体小片、例如专用集成电路芯片(ASIC)的成本和复杂性增加，存在设计、取得资格（qualifying）和制作这些装置的封装的成本的对应增加。有利地，本说明书的方法允许共形掩蔽层112中的图案117的预备以在将半导体小片118耦合到介电层102之前形成。因此，该方法促进介电层102中的其他预构图布线互连和/或有缺陷的或损坏的图案117的测试。在一个实施例中，图案117可使用目视检查或者使用自动化测试设备和探测装置的自动化方法来测试，如本领域的技术人员众所周知。在一个示例中，可通过检查共形掩蔽层112和布线层136(参见图9)来测试图案117。在一些实施例中，一旦识别有缺陷的或损坏的微通孔图案117，则所识别的有缺陷的或损坏的图案117微通孔可被免除与半导体小片、例如半导体小片118耦合，由此使昂贵半导体小片免于由于有其连接到有故障的微通孔的优点而变成不起作用。
此外，如图7的示意表示所图示，在将半导体小片118耦合到介电层102的第二侧110之后，可去除介电层102的所选部分121(参见图6)。具体来说，可去除所选部分121，以扩展图案117并且形成微通孔122(参见图8)。在一个实施例中，介电层102的部分121可使用干式蚀刻、湿式蚀刻、消融、溶解、钻孔、激光消融或者其组合来去除。此外，可注意，连同介电层102的所选部分121一起，可去除介电层的一侧或两侧108、110上的粘合层。
在介电层102的激光消融的情况下，构图光束(图7未示出)可用来去除介电层102和粘合层(未示出)的所确定部分，以形成介电层102中与共形掩蔽层112中形成的图案117(参见图5)对应的图案。此外，在激光消融的情况下，介电层102的部分121可使用构图光束来去除。可注意，共形掩蔽层112配置成限定微通孔的尺寸。具体来说，微通孔的尺寸可通过共形掩蔽层112中形成的图案117来限定。在一个实施例中，构图光束可包含激光束。在示范实施例中，构图光束的尺寸可大于或等于将要在介电层102中形成的微通孔的尺寸。在其中构图光束的尺寸大于微通孔122的尺寸的实施例中，共形掩蔽层112的存在仅允许与微通孔122的所希望的尺寸(参见图8)对应的构图光束的一部分入射到介电层102上。此外，一旦形成与层112中的图案117对应的图案121，激光消融可在半导体小片118或者介电层102与半导体小片118之间所设置的粘合层(或者在地层109)处停止。在一个实施例中，共形掩蔽层的材料的层113的厚度可以是这样的：层113配置成耐受构图光束的能量而没有经受不希望的分裂。在某些实施例中，微通孔122可以是盲微通孔，其配置成提供半导体小片118与电子组件、例如芯片之间的电连接，其中半导体小片118和芯片使用电子封装900(参见图9)来耦合。可注意，本说明书的方法实现形成微通孔、例如微通孔122，其尺寸比使用激光构图通常形成的通孔要小。具体来说，微通孔122的尺寸甚至可小于用来形成微通孔122的构图光束的尺寸。有利地，因为共形掩蔽层112的材料配置成阻挡构图光束的至少一部分，实现微通孔122的较小尺寸，由此防止去除设置在共形掩蔽层112的材料下面的介电层102的部分。因此，微通孔122的尺寸通过共形掩蔽层112中存在的图案117的尺寸来确定，而不是通过用来形成有选择地去除介电层102的材料的构图光束或激光束的尺寸来确定。
另外，如图8的示意表示800所图示，共形导电层130可沉积在共形掩蔽层112的至少一部分上以及至少沉积在微通孔122中。共形导电层130可按照共形方式设置在微通孔122中。参考数字131指的是电子封装900(参见图9)的一部分的放大视图，以更清楚地描绘至少在微通孔122中的共形导电层130的共形性质。具有共形导电层130的微通孔122称为微通孔122。此外，共形导电层130提供微通孔122与半导体小片118之间的电联系。共形导电层130可包含以电气方式和以热的方式传导材料，以及按照示范实施例，可由诸如铜、银或镍的金属材料来形成。此外，在一个实施例中，共形导电层130可包含单层或者层的组合。此外，还预想合成材料可用来形成共形导电层130。在一些实施例中，金属预浸环氧树脂或金属填充涂料可用作共形导电层。在一些其他实施例中，共形导电层130可使用溅射、电镀、非电解镀或者其组合来沉积。
可选地，在一些实施例中，在沉积共形导电层130之前，附加电连接层可沉积在与微通孔122对应的半导体小片118的部分上。用于共形导电层130的材料的非限制性示例可包含钛、钛-钨、铬或者其组合。此外，在相同或不同的实施例中，除了共形导电层130之外，还可如需要沉积附加层。
图9是电子封装900的示意表示。如图9所图示，可去除所选部分、例如在共形导电层130的位置134的部分，以在共形掩蔽层112的至少一部分上形成布线层136。此外，还可去除相邻设置的共形掩蔽层112中的对应部分，以隔离用于布线的迹线。因此形成的布线层136可包含迹线，其将微通孔122连接到电子封装900或者半导体小片118和/或芯片(图9中未示出)中的其他组件。共形掩蔽层112和布线层136共同提供芯片和/或电子封装900之间的电连接。可注意，布线层136提供微通孔112与共形掩蔽层112之间的电连接。共形掩蔽层112和布线层136共同形成电子封装900的布线互连138。此外，布线层136可由钛、铜、镍、金、铬、铝、钛-钨或者其组合的一个或多个来形成。
此外，可在需要去除电子封装900的一层或多层的至少一部分的任何步骤之后引入一个或多个清洁步骤。作为示例，清洁步骤可在图3所示的步骤之后执行，其中去除共形掩蔽层112(参见图6-9)的材料的层113的部分。类似地，可至少在执行图4、图5、图7和图9所示的步骤之后执行清洁步骤或蚀刻步骤。可执行这类清洁步骤，以从配置成形成电子封装900的层的叠层中去除任何过剩材料。可注意，也可执行附加清洁步骤。作为示例，可执行清洁步骤，以在沉积共形导电层130之前清洁设置在微通孔122内部、微通孔122外部或者两者的共形掩蔽层112的表面的至少一部分。在一些实施例中，在设置共形导电层130之前可采用清洁共形掩蔽层112的可选步骤。在一个示例中，清洁步骤可用来去除任何不希望的材料，例如将要从共形掩蔽层112的表面去除的氧化物、金属、电介质、粘合剂，由此促进共形掩蔽层112与共形导电层130之间的增强附着。
在某些实施例中，可使用丝焊、球栅阵列、倒装芯片组合件或者任何其他已知耦合技术或者其组合将电子封装900(参见图9)安装在电子板、例如印刷电路板(PCB)上。作为示例，对于与电子封装900中的相对大接触焊盘尺寸和较低输入/输出(I/O)密度的低成本简单接合，可采用丝焊。此外，电子封装900上的电子焊盘可使用导电线来耦合到电子板上的对应电气迹线或电子焊盘，以形成丝焊。
在另一个示例中，对于半导体小片118或电子封装900中的低成本、相对高的I/O密度，倒装芯片技术可用来将电子封装900电耦合到电子板。此外，在一些实施例中，金属凸点、金属短柱或球(本文中统称为“凸点类型”互连)可按照二维(2D)阵列图案直接应用到电子封装900的有源表面。备选地，在一个实施例中，导电粘合剂可用来将电子封装900耦合到电子电路。
现在转到图10，图示本说明书的电子封装的一部分1000的顶视图。部分1000包含本说明书的共形掩蔽层1001中限定的微通孔1002以及共形掩蔽层1001。微通孔可使用针对图1-9所示的方法来形成。此外，参考数字1004表示使用常规方法所形成的常规微通孔。如所图示，与更大并且相互间隔更远的常规通孔1004相比，微通孔1002更小并且密集地封装。因此，本说明书的微通孔1002配置成耦合到具有较高密度的接触焊盘的较小尺寸的小片。
图11是本说明书的电子封装1100的一部分的顶视图。在所图示实施例中，部分1100图示微通孔1104的阵列1102。此外，阵列1102的微通孔1104的一部分可使用电子封装1100的布线层1108中存在的电气迹线1106电耦合到电子封装1100之内或之外的其他电子组件。作为示例，微通孔1104可使用电气迹线1106电耦合到外部电气装置、例如半导体小片。另外，一些其他微通孔1104可使用布线互连1112来耦合到电子封装的介电层上的其他布线层、接触焊盘或者其他通孔1110。另外，电气迹线1112可用作外部装置相互之间或者与下地线层(未示出)的电互连。这些电气迹线1106和/或1112可在布线层1108中通过有选择地去除共形导电层130和共形掩蔽层112的部分来形成，如针对图1-9所描述。
在一些实施例中，本说明书的电子封装用作提供一个或多个电气组件与板级电路组件（例如但不限于印刷电路板上的焊料焊盘、接触焊盘、插座或者如本领域的技术人员众所周知)之间的电接口。在非限制性示例中，一个或多个电气组件可包含一个或多个半导体芯片小片、也称作“小片”。此外，板级电路组件可包含印刷电路板上的插座或焊盘。此外，电子组件配置成到半导体小片的第一批多个电连接以及适合于到板级电路组件的第二批多个电连接。
在某些实施例中，本说明书的电子封装可具有多级。在一个示例中，多级可包含一个或多个共形掩蔽层和/或一个或多个布线层和介电层。多级的层可用来有选择地引导信号来往于半导体小片的接触焊盘和/或电子封装的接触焊盘或电气迹线。
参照图12的示意表示，电子封装1200的一部分使用半导体小片焊盘1207在操作上耦合到半导体小片1202。电子封装1200包含微通孔1204。此外，微通孔1204包含通过壁1211所限定的井型结构1212。此外，微通孔1204的壁1211延伸通过粘合层1206、介电层1208以及共形掩模层和布线互连(均通过参考数字1210以组合方式所表示)的组合。微通孔1210的壁1211上的共形层可在操作上耦合到半导体小片1202。可注意，壁1211上的共形层可设置在壁1211之间存在的整个体积中。备选地，共形层可仅在壁1211与半导体小片1202之间所限定的体积的一部分中设置。
此外，可注意，针对单个小片图示和描述制作高密度电子封装的方法。但是，该方法也可用于制作具有多个小片的电子封装。在一个实施例中，多个小片可以阵列配置来排列。此外，多个小片可使用拾取和放置机器人装置和一个或多个基准参考点相对于微通孔的位置来对齐。此外，在一些实施例中，该方法也可用于制作每个处理框架的多个电子封装。在这些实施例中，各电子封装可具有一个或多个半导体小片。
图13表示具有耦合到介电层1304的多个半导体小片1302的示范电子封装1300。此外，电子封装1300包含共形掩蔽层1306和布线层1308。另外，共形掩蔽层1306和布线层1308共同形成电子封装1300的布线互连1314。此外，多个微通孔1310设置在共形掩蔽层1306和布线层1308的至少一部分中。布线层1308的部分形成多个微通孔1310中的导电层，以提供微通孔1310与多个半导体小片1302之间的电连接。此外，多个半导体小片1302可布置在介电层1304上，使得半导体小片1302的每个上的电连接、例如接触焊盘与多个微通孔1310的对应微通孔1310对齐。此外，虽然未图示出，但是多个微通孔1310的微通孔1310的一部分可被免除与半导体小片1302或任何其他电气装置耦合。作为示例，在检查是否确定某些微通孔1310有缺陷时，有缺陷的微通孔134可以不耦合到半导体小片1302。此外，在所图示实施例中，电子封装1300可在公共处理框架(未示出)上形成。但是，在一些其他实施例中，电子封装1300可包含多个这类处理框架。此外，在这些实施例中，多个处理框架的每个可包含一个或多个半导体小片。可注意，在本说明书的范围之内预想包括多个电子封装、例如电子封装900、电子封装1300等的堆叠结构及其制作方法。
有利地，本说明书的电子封装配置成提供至少一个或多个电气组件之间的布线，同时适应空间限制、减小的间距和增加的布线密度。作为示例，包括具有从大约5微米到大约50微米的范围中的平均直径以及从大约10微米到大约100微米的范围中的间距的微通孔实现在操作上耦合可要求更高布线密度的更小电路。
虽然本公开仅图示和描述了本发明的某些特征，但本领域的技术人员将会想到许多修改和变更。因此要理解，所附权利要求书预计涵盖落入本公开的真实精神之内的所有这类修改和变更。

Claims (10)

1.一种电子封装，包括：
介电层；
共形掩蔽层，设置在所述介电层的至少一部分上；
布线层，设置在所述共形掩蔽层的至少一部分上；
微通孔，至少部分设置在所述共形掩蔽层和所述布线层中，其中所述布线层的至少一部分形成所述微通孔的至少一部分中的共形导电层，并且其中所述共形掩蔽层配置成限定所述微通孔的尺寸；以及
半导体小片，耦合到所述微通孔。
2.如权利要求1所述的电子封装，其中，所述共形掩蔽层包括导电材料。
3.如权利要求1所述的电子封装，其中，所述导电材料包含铜、钛、铝、镍、金、钨铬钽或者其组合。
4.如权利要求1所述的电子封装，其中，所述微通孔的至少一部分设置在所述共形掩蔽层、所述布线层和所述介电层中。
5.如权利要求1所述的电子封装，其中，所述微通孔是盲微通孔。
6.如权利要求1所述的电子封装，其中，所述微通孔的直径在从大约5微米到大约50微米的范围中。
7.如权利要求1所述的电子封装，其中，所述布线层配置成设置在所述共形掩蔽层上。
8.如权利要求1所述的电子封装，其中，所述布线层包括钛、铜、镍、金、铬、铝、钛-钨或者其组合。
9.如权利要求1所述的电子封装，其中，所述共形掩蔽层和所述布线层形成布线互连。
10.一种电子系统，包括：
电子封装，包括：
介电层；
共形掩蔽层，设置在所述介电层的至少一部分上；
布线层，设置在所述共形掩蔽层的至少一部分上；
多个微通孔，至少部分设置在所述共形掩蔽层和所述布线层中，其中所述布线层的至少一部分形成所述多个微通孔的微通孔的至少一部分中的共形导电层；以及
多个半导体小片，其中所述多个半导体小片的一个或多个半导体小片耦合到所述多个微通孔的对应微通孔。
CN201510863302.6A 2014-12-01 2015-12-01 电子封装及其制作和使用方法 Pending CN105655321A (zh)

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