CN105612610B - 结合负热膨胀材料的导电互连结构及相关系统、装置及方法 - Google Patents
结合负热膨胀材料的导电互连结构及相关系统、装置及方法 Download PDFInfo
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Abstract
本发明揭示具有结合负热膨胀NTE材料的互连件的半导体装置。在一个实施例中,半导体装置包含衬底,所述衬底具有至少部分延伸穿过所述衬底的开口。具有正热膨胀系数CTE的导电材料部分充填所述开口。具有负CTE的负热膨胀NTE材料也部分充填所述开口。在一个实施例中,所述导电材料包含铜,且所述NTE材料包含钨酸锆。
Description
技术领域
本技术涉及半导体装置互连件,例如包含具有负热膨胀系数(CTE)的材料的通孔、迹线及其它接触结构。
背景技术
形成半导体装置通常包含使半导体衬底或组合件经受用于添加、移除及/或更改材料的一系列处理步骤。这些处理步骤可逐渐精确地形成非常高密度的电组件,例如晶体管、电容器及二极管。所述电组件可通过通常在多个层上延伸且延伸穿过所述多个层的复杂网络连接而连接。从一个层到另一层的此类网络连接可为通过按所需图案选择性地在半导体材料中蚀刻出孔且用导电材料充填所述孔而形成的通孔。硅通孔(TSV)为一个类型的通孔,其延伸穿过整个半导体衬底。TSV通过电介质间隔件与衬底隔离,且电互耦合在衬底的相反两侧处的接触件或其它导电特征部。
附图说明
图1A为具有根据本技术的实施例所配置的TSV的半导体装置的横截面侧视图。
图1B及1C为根据本技术的实施例的分别处于初始温度水平及处于升高温度水平的图1A的TSV的横截面俯视图。
图2A到2C为展示具有根据本技术的选定实施例所配置的不同体积比的负热膨胀材料的TSV的横截面侧视图。
图3A到3E为说明在根据本技术的选定实施例的制造方法中的选定步骤处的图1A的半导体装置的横截面图。
图4A及4B为具有根据本技术的另一实施例所配置的TSV的半导体装置的横截面侧视图。
图5A到5C为根据本技术的其它实施例所配置的互连结构的等角视图。
图6为说明结合根据本技术的实施例的半导体装置的系统的框图。
具体实施方式
本技术的若干实施例的特定细节涉及结合负热膨胀(NTE)材料的半导体装置中的电极。术语“半导体装置”大体上是指包含半导体材料的固态装置。半导体装置尤其可为逻辑装置、存储器装置及二极管。半导体装置还可包含发光半导体装置,例如发光二极管(LED)、激光二极管及其它固态换能器装置。此外,术语“半导体装置”可指成品装置或在成为成品装置前的各种处理阶段中的组合件或其它结构。术语“互连件”可指垂直延伸穿过及/或横向跨过半导体装置或衬底的一部分的各种导电结构中的任一者。互连件的实例包含通孔、迹线、接触垫、导线及其它导电结构。取决于其使用背景,术语“衬底”可指晶片级衬底及/或经单切的裸片级衬底。另外,除非上下文另有指示,否则本文所揭示的结构可使用常规半导体制造技术来形成。(例如)可使用化学气相沉积、物理气相沉积、原子层沉积、旋转涂布及/或其它适当技术来沉积材料。类似地,(例如)可使用等离子蚀刻、湿式蚀刻、化学机械平坦化(CMP)或其它适当技术来移除材料。同样地,可(例如)通过使用一或多个掩模材料(例如光致抗蚀剂材料、硬掩模材料或其它适当材料)添加及/或移除材料来图案化材料。
常规互连材料(例如,金属材料)的一个问题是其响应于在许多制造工艺及操作中发生的温度改变的膨胀及收缩超过衬底中的许多其它材料。一般来说,互连件基于其体积及热膨胀系数(CTE)而在尺寸上膨胀,且通常,许多互连材料的CTE显著大于衬底中的材料的CTE。举例来说,铜可具有约1.7 x 10-5 1/K(线性)的CTE,而硅可具有约2.3 x 10-6 1/K(线性)的CTE。在升高温度下,CTE的此差异使互连件膨胀到大于相邻衬底材料的范围。此膨胀将应力强加到周围材料且在衬底中引起裂痕。这些裂痕最终可导致晶片破裂、装置故障(归因于硅晶格损伤)、装置失效及产率损失。然而,根据本技术的若干实施例所配置的互连件解决了常规互连件的这些及其它限制。
图1A为根据本技术的实施例所配置的半导体装置100的横截面侧视图。半导体装置100包含衬底102及电组件103(示意性展示)。衬底102可包含(例如)硅衬底、外延结构、半导体材料堆叠或其它适当结构。电组件103可为(例如)晶体管、二极管、LED、电容器、集成电路等等。
半导体装置100进一步包含经配置以将电信号路由到内部组件(例如,电组件103)及/或外部组件(例如,芯片外组件)的导电互连件105的网络。互连件105可包含(例如)通孔106、接触结构108及使通孔106与接触结构108连接的迹线109。在图1A的实施例的一个方面中,互连件105还包含形成于穿孔112中的TSV 110,所述穿孔112在第一侧113a(例如,顶部或作用侧)与第二侧113b(例如,底部或背侧)之间延伸穿过衬底102。如展示,TSV 110通过间隔件材料(在图1A中不可见)与衬底102隔离,且包含至少一个外部导电材料115及至少一个NTE材料116。外部材料包含正CTE材料,例如铝、铜、银、铂、钌、钛、钴等等。另一方面,NTE材料116包含负CTE材料。在一个实施例中,NTE材料116可包含金属氧化物结晶材料。举例来说,钨酸锆(Zr(WO4)2)为一种此材料,其具有约-4.9 x 10-6 1/K的负CTE。不同于大多数结晶材料,钨酸锆具有“弹性铰接”的晶格组分(ZrO6及WO4),其通过自身再排序及/或旋转成为晶格内的更紧凑配置而响应于热量增加。其它NTE材料可具有当被加热时展现类似收缩机制的晶格组分。举例来说,ZrW2O8为结晶材料,其可具有约-11.4 x 10-6 1/K的负CTE。
如在本文所使用,术语“NTE材料”是指响应于温度的增加而体积收缩的材料。类似正CTE材料,NTE材料具有与其在特定温度范围内的膨胀/收缩量值相关的CTE。然而,不同于正CTE材料,NTE材料具有在特定温度范围(例如,-50℃到250℃)内的负CTE。与NTE材料相关的其它材料性质、特征及组成描述于以下文献中,例如:T.A.玛丽(T.A.Mary)等人所著的“ZrW2O8的从0.3到1050开尔文的负热膨胀(Negative Thermal Expansion from 0.3 to1050 Kelvin in ZrW2O8)”科学(Science)272.5258(1996):90-92;D.基恩(D.Keen)等人所著的“钨酸锆的负热膨胀(Negative thermal expansion in zirconium tungstate)”物理评论快报(Phys.Rev.Lett.)96(2005);H.刘(H.Liu)等人所著的“通过射频磁控管溅射制备的ZrW2O8薄膜上的后沉积退火效应(Effect of post-deposition annealing on ZrW2O8thin films prepared by radio frequency magnetron sputtering)”表面和涂层技术(Surface and Coatings Technology).201.9-11(2007):5560-5563;M.S.萨顿(Sutton)等人所著的“用于光学涂层的基于钨酸锆(ZrW2O8)的负热膨胀膜的沉积相关性(Depositiondependence of zirconium tungstate(ZrW2O8)based negative thermal expansionfilms for optical coatings)”光学干涉涂层(Optical Interference Coatings(OIC))图森(Tucson),亚利桑那,2004年6月27日,光学涂层的沉积III(ME)(Deposition ofOptical Coatings III(ME));S.森格马内尼(S.Singamaneni)等人所著的“超薄等离子中的负热膨胀(Negative Thermal Expansion in Ultrathin Plasma)”聚合膜化学材料(Polymerized Film Chm.Mater.)19(2007):129-131;科拉·利德(Cora Lind)所著的“二十年来的负热膨胀研究:我们进展如何?(Two Decades of Negative Thermal ExpansionResearch:Where Do We Stand?)”材料(Materials)2012,5,1125-1154;W.斯莱特(W.Sleight)所著的“负热膨胀(Negative Thermal Expansion)”材料研究学会研讨学报(Mat.Res.Soc.Symp.Proc.),755卷,2003,材料研究学会(Materials Research Society)。
根据本技术的实施例,图1B为在初始温度水平T1(例如,室温)下的TSV 110的横截面俯视图,且图1C展示在升高温度水平T2(例如,制造或操作温度)下的TSV 110。在初始温度水平T1下(图1B),导电材料115及NTE材料116在第一圆周层位C1处与彼此界面连接。在升高温度水平T2下(图1C),导电材料115已膨胀且NTE材料116已收缩而暴露敞开空间)。因此,导电材料115的一部分可膨胀到敞开空间中以松弛由热膨胀造成的应力。
尽管在图1C中不可见,但导电材料115可在垂直方向上膨胀(即,到页面平面中),且NTE材料116可在第一侧113a与第二侧113b之间在垂直方向上收缩(图1A)。一般来说,垂直方向上的膨胀/收缩并不造成典型的(衬底)破裂,及与上文所讨论的常规横向膨胀/收缩相关的其它类型的损伤。在一些实施例中,垂直方向上的膨胀/收缩可在TSV100的任一端处产生敞开空间(类似于归因于横向方向上的膨胀/收缩所产生的敞开空间)。
NTE材料116的体积改变可(至少部分)基于其负CTE值、初始体积及温度改变(即,T2-T1)。在一个实施例中,NTE材料的体积改变(ΔVNTE)可由如下等式1近似得出:
ΔVNTE=α1xVNTE(T2-T1) (I)
其中α1表示NTE材料116的负CTE,且VNTE表示在初始温度水平T1下NTE材料116的初始体积。
导电材料115的外体积的改变可(至少部分)基于其正CTE值、初始体积及温度改变。在一个实施例中,外部材料的体积的改变(ΔVO)可由如下等式2近似得出:
ΔVO=α2xVO(T2-T1) (2)
其中α2表示导电材料115的正CTE,且VO表示在初始温度水平T1下导电材料115的初始体积。
根据本技术的各种实施例,TSV 110可具有复合CTE,其(至少部分)基于TSV 110中每一材料的CTE以及TSV 110中每一材料的体积。在一个实施例中,复合CTE(αc)可由如下等式3近似得出:
αc=βxα1xVNTE+(1-β)xα2xVO (3)
其中β为与NTE材料116相关的体积比。体积比β可由如下等式4近似得出:
β=VNTE/VT (4)
其中VT为TSV 110的总体积(即,TSV 110中每一材料的体积的合计)。
在一些实施例中,通过选择某些类型的导电材料及/或NTE材料,复合CTE可经定制或经工程设计以具有特定值。举例来说,当导电材料115由金而非铜组成时,由于金具有小于铜的CTE,所以复合CTE具有较小值。如在下文描述,配置复合CTE的另一方式为改变与NTE材料116相关的体积比β。
图2A到2C为展示根据本技术的选定实施例具有不同体积比β的NTE材料116的TSV210(被个别地识别为第一TSV 210a到第三TSV 210c)的横截面侧视图。首先参考图2A,第一体积比β1提供具有零值(αc=0)的复合CTE。在图2B中,第二体积比β2(<β1)提供具有正值(αc>0)的复合CTE。在图2C中,第三体积比β3(>β1)提供具有负值(αc<0)的复合CTE。
同时参考图2A到2C,当被加热时,第一TSV 210a可与其复合CTE成比例地膨胀或收缩。举例来说,当其具有第一体积比β1(即,当αc=0时)时,第一TSV 210a当其被加热时实质上不会膨胀或收缩。然而,当具有第二体积比β2时(即,当αc<0时),第二TSV 210b大体上将在被加热时膨胀,虽然小于导电材料115单独的体积膨胀。另一方面,当具有第三体积比β3时(即,当αc<0时),第三TSV 210c在被加热时收缩。在一些配置中,第三TSV 210c可按与另一材料膨胀相同的比率收缩。举例来说,第三TSV 210c可按与相邻衬底102膨胀相同的比率收缩。
图3A到3E为说明根据本技术的选定实施例的在制造方法中的选定步骤处的半导体装置100的横截面图。如在图3A中所展示,电介质材料321(例如,氧化物、碳化硅、氮化硅等等)已形成于衬底102上,且已形成穿过衬底102的第一侧113a及电介质材料321的开口320。在一些实施例中,电介质材料321可在TSV隔离期间的CMP工艺中用作停止材料。开口320包含凹入表面322及延伸到衬底102内的中间深度(但非完全穿过)的侧壁323。在所说明的实施例中,开口320具有圆形(或长圆)形状(从(例如)半导体装置100的第一侧113a观看)。然而,在其它实施例中,开口320可具有不同配置。举例来说,开口320可为沟槽。图3B展示在已分别在开口320中形成电介质衬垫324(例如,氧化物衬垫)及导电材料315后的半导体装置100。在所说明的实施例中,朝向开口320的底部的导电材料315比朝向开口320中的侧壁的导电材料厚。在一个实施例中,从下而上的电镀工艺可用于在开口的底部处形成相对较厚的金属(例如,铜),接着一旦已形成较厚金属,则沿侧壁进行更均匀电镀。导电材料315可包含(例如)铜、钨、金、银、铂、铝等等。在一些实施例中,导电材料315为电镀材料,其内衬凹入表面322、侧壁323及衬底102的外表面325。半导体装置100还可包含在导电材料315与衬底102的部分之间的势垒及/或晶种材料327。势垒及/或晶种材料327可包含(例如)钽、氮化钽、钨、钌、铜、钛、氮化钛或其它适当材料。
图3C展示在NTE材料316已沉积于导电材料315上之后的半导体装置100。可(例如)使用化学气相沉积或其它适当技术来沉积NTE材料316。如在上文讨论,NTE材料316可包含金属氧化物,例如钨酸锆。另一适当NTE材料可包含ZrV2O7。在其它实施例中,适当NTE材料可包含‘A’‘M’2O8族化合物及/或‘A’2(‘M’O4)3族化合物的成员,其中‘A’可包含锆或铪,且‘B’可包含钼或钨。
图3D展示在形成其它装置特征部后的半导体装置100。在所说明的实施例中,额外导电材料329形成将导电材料315与接触件106连接的互连结构。如展示,额外电介质材料311已形成于电介质材料321及NTE材料316上,电介质材料的一部分已经移除(例如,经蚀刻)以在电介质材料311、321中形成开口,且在电介质材料311、321中形成的开口已用导电材料329的部分充填。在一些实施例中,导电材料329可经沉积于第一侧113a处的NTE材料316的至少一部分上。
图3E展示在移除导电材料315及衬底102的部分以暴露在第二侧113b处的导电材料315的部分后的半导体装置100。可通过(例如)背面研磨、蚀刻、CMP及/或其它适当移除方法来移除材料。同样地,可在第二侧113b处使用各种钝化材料(未在图3E中展示)来保护衬底102且防止污染(例如,金属污染)。在一个实施例中,薄化工艺可使用在第二侧113b处的衬垫324的电介质材料的暴露来检测应何时停止移除工艺(例如端点检测)以增强后续处理中的工艺控制。在另一实施例中,导电材料(例如,导电材料315及/或势垒晶种材料327)可提供端点检测。在暴露导电材料315的部分后,处理可继续(例如)以形成其它特征部(例如,接触结构108(图1A)以及进行装置单切、测试及/或封装。
图4A展示在衬底102已经薄化以暴露第二侧113b处的电介质衬垫324使得电介质衬垫324及导电材料315的部分在第二侧113b处凸出超过衬底材料后的包含导电材料315及NTE材料316(例如,在图3D的阶段后)的TSV 410。电介质材料417接着经形成于第二侧113b处。电介质材料417可为保形或非保形材料,其包含最初在第二侧113b处覆盖TSV 410的低温电介质。后续材料移除工艺(具有较高可控性)可通过移除厚电介质材料417及电介质衬垫324的部分而暴露导电材料315(或替代地,导电材料315以及NTE材料316的一部分)。
图4B展示沉积于图4A的电介质材料417及暴露的导电材料315上的厚电介质材料440(例如,低温氧化物、氮化物、碳化物等等)。在所说明的实施例中,额外导电材料419可形成电接触件。举例来说,厚电介质材料440及导电材料419可形成镶嵌结构。
图5A到5C为根据本技术的其它实施例所配置的互连结构的等角视图。类似于上文所讨论的TSV,图5A到5C的互连结构可经配置以结合NTE材料。图5A为展示导电迹线530a的实例,导电迹线530a包含布置于并行线532中的外导电材料515a及在并行线532之间的内NTE材料516a。图5B展示接触垫530b的实例,接触垫530b具有布置于正方形图案533中的外导电材料515b及在正方形533的中心的内NTE材料516b。图5C为层间电介质535的实例,层间电介质535具有外电介质材料517(例如,氧化物)及配置为通孔530c的内NTE材料516c。不同于上文讨论的TSV,通孔530c并不包含外导电材料。在一个实施例中,NTE材料516c经配置使得在提高的温度下,NTE材料516c按与外电介质材料517膨胀相同的比率收缩(且反之亦然)。
具有上文参考图1A到5所描述的特征部的半导体装置中的任何一者可经结合到大量更大及/或更复杂的系统的任一者中,其代表性实例为在图6中示意性展示的系统690。系统690可包含处理器692、存储器694(例如,SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置696及/或其它子系统或组件698。上文参考图1A到5C所描述的半导体组合件、装置及装置封装可包含到图6中展示的元件中的任一者中。产生的系统690可经配置以执行多种适当计算、处理、存储、感测、成像及/或其它功能中的任一者。因此,系统690的代表性实例包含(但不限于)计算机及/或其它数据处理器,例如桌面计算机、膝上型计算机、因特网设备、手持式装置(例如,掌上计算机、可穿戴式计算机、蜂窝式或移动电话、个人数字助理、音乐播放器等等)、平板计算机、多处理器系统、基于处理器或可编程消费性电子产品、网络计算机及小型计算机。系统690的额外的代表性实例包含灯、相机、车辆等等。就这些及其它实例来说,系统690可容纳于单一单元中或分布于多个互连单元内(例如,通过通信网络)。系统690的组件可因此包含本地及/或远程存储器存储装置及多种适当计算机可读媒体中的任一者。
从前文,将了解本文已出于说明的目的而描述本技术的特定实施例,但可在不脱离本发明的情况下做出各种修改。在各种实施例中,上述互连件的形状、大小、数目及其它特性可变化。举例来说,NTE材料116(图1)可经形成使得间隙或空隙结合(或自然地出现)在TSV 100(图1)的中心内。并且,在一些实施例中,NTE材料116可经沉积使得其覆盖或囊封导电材料115(图1)。举例来说,在一些实施例中,导电材料115可形成TSV 100的内部部分,且NTE材料116可用作覆盖材料。另外,在其它实施例中,在特定实施例的背景中描述的本发明的特定方面可被组合或消除。此外,虽然已在所述实施例的背景中描述与特定实施例相关的优点,但其它实施例也可展现这些优点。并非所有实施例都有必要展现此类优点以落入本发明的范围中。因此,本发明及相关技术可涵盖未在本文中清晰展示或描述的其它实施例。
Claims (33)
1.一种半导体装置,其包括:
衬底,其具有至少部分延伸穿过所述衬底的开口;
导电材料,其部分充填所述开口;及
负热膨胀NTE材料,其也部分充填所述开口;
其中所述导电材料安置于所述衬底与所述负热膨胀NTE材料之间。
2.根据权利要求1所述的半导体装置,其进一步包括延伸穿过所述开口的硅通孔TSV,其中:
所述TSV包含所述导电材料及所述NTE材料,
所述NTE材料包含Zr(WO4)2,及
所述导电材料包含铜。
3.根据权利要求1所述的半导体装置,其中所述NTE材料包含ZrV2O。
4.根据权利要求1所述的半导体装置,其中所述NTE材料包含ZrMo2O8、ZrW2O8、HfMo2O8或HfW2O8或其组合。
5.根据权利要求1所述的半导体装置,其中所述NTE材料包含Zr2(MoO4)3、Zr2(WO4)3、Hf2(MoO4)3、Hf2(WO4)3或其组合。
6.根据权利要求1所述的半导体装置,其中所述NTE材料包含Zr(WO4)2。
7.根据权利要求1所述的半导体装置,其中所述导电材料包含铜、铝、钨、银、金、铂、钌、钛及钴中的至少一者。
8.一种通孔结构,其包括:
至少第一材料,其至少部分延伸穿过半导体装置;及
至少第二材料,其至少部分延伸穿过所述第一材料,其中
所述第一材料具有大于零的第一热膨胀系数CTE,
所述第二材料具有小于零的第二CTE,及
所述第一材料及所述第二材料一起具有复合CTE,其小于所述第一热膨胀系数CTE但大于所述第二CTE。
9.根据权利要求8所述的通孔结构,其中所述复合CTE小于零。
10.根据权利要求8所述的通孔结构,其中所述复合CTE等于零。
11.根据权利要求8所述的通孔结构,其中:
所述半导体装置包括半导体衬底;及
至少所述第一材料完全延伸穿过所述半导体衬底。
12.根据权利要求11所述的通孔结构,其中所述第二材料完全延伸穿过所述半导体衬底。
13.根据权利要求8所述的通孔结构,其中:
所述第一材料具有第一体积;
所述第二材料具有第二体积;及
所述第一体积及所述第二体积经配置使得所述复合CTE小于零。
14.根据权利要求8所述的通孔结构,其中:
所述第一材料具有第一体积;
所述第二材料具有第二体积;及
所述第一体积及所述第二体积经配置使得所述复合CTE等于零。
15.根据权利要求8所述的通孔结构,其中所述第一材料围绕所述第二材料。
16.一种半导体装置,其包括延伸穿过衬底且具有复合热膨胀系数CTE的互连结构,其中所述互连结构包含:
导电材料,其具有大于所述复合CTE的第一CTE;及
结晶材料,其与所述导电材料界面连接,其中所述结晶材料位于所述衬底内且具有小于零的第二CTE,
其中,所述导电材料的至少一部分经安置于所述衬底与所述结晶材料之间。
17.根据权利要求16所述的半导体装置,其中:
所述衬底包含凹入表面;及
所述导电材料的所述部分也在所述凹入表面与所述结晶材料之间。
18.根据权利要求16所述的半导体装置,其中:
所述导电材料为定位于所述衬底与所述结晶材料之间的第一导电材料;
所述互连结构进一步包括也与所述结晶材料界面连接的第二导电材料;
所述第一导电材料经配置以当所述互连结构被加热到升高温度时,控制所述互连结构的横向膨胀;及
所述第二导电材料经配置以当所述互连结构被加热到所述升高温度时,控制所述互连结构的垂直膨胀。
19.根据权利要求16所述的半导体装置,其中所述互连结构包含导电通孔。
20.根据权利要求16所述的半导体装置,其中所述互连结构包含导电迹线。
21.根据权利要求16所述的半导体装置,其中所述互连结构包含接触垫。
22.一种制造半导体装置的方法,其包括:
用第一材料来部分充填衬底中的开口,其中所述第一材料具有正热膨胀系数CTE;及
进一步用第二材料来充填所述开口,其中所述第二材料具有负CTE,
其中,所述第一材料位于所述衬底与所述第二材料之间。
23.根据权利要求22所述的方法,其中:
用所述第一材料部分充填所述开口包括将导电材料电镀到所述开口的侧壁上;及
进一步用所述第二材料充填所述开口包括将负热膨胀NTE材料沉积到所述开口中的所述导电材料的至少一部分上。
24.根据权利要求23所述的方法,其中所述导电材料为第一导电材料,且其中所述方法进一步包括:
从所述开口移除所述NTE材料的一部分;及
在移除所述NTE材料的所述部分后,进一步用第二导电材料充填所述开口。
25.根据权利要求24所述的方法,其进一步包括从所述衬底移除材料,使得至少所述第一材料完全延伸穿过所述衬底。
26.根据权利要求24所述的方法,其进一步包括形成互连件,其中所述互连件包含所述第一材料及所述第二材料。
27.一种制造方法,其包括形成互连结构,其中:
所述互连结构包含导电材料及在所述导电材料的至少一部分内的负热膨胀NTE材料;及
所述互连结构具有至少部分基于在所述导电材料内的所述NTE材料的体积的复合热膨胀系数CTE。
28.根据权利要求27所述的方法,其中:
所述导电材料具有大于零的热膨胀系数CTE;
所述NTE材料具有小于零的CTE。
29.根据权利要求27所述的方法,其进一步包括在半导体衬底上形成所述导电材料的体积,其中所述导电材料的所述体积是基于所述复合CTE。
30.根据权利要求29所述的方法,其中所述互连结构包含接触垫及导电迹线中的至少一者。
31.根据权利要求27所述的方法,其中形成所述互连结构进一步包括在半导体衬底中的开口内形成所述互连结构的至少一部分。
32.根据权利要求31所述的方法,其中所述开口的体积是基于所述复合CTE。
33.根据权利要求31所述的方法,其中所述互连结构包含导电通孔。
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9099442B2 (en) | 2013-08-05 | 2015-08-04 | Micron Technology, Inc. | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods |
US10068181B1 (en) * | 2015-04-27 | 2018-09-04 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafer and methods for making the same |
US10051199B2 (en) * | 2015-07-22 | 2018-08-14 | Dell Products, Lp | Apparatus and method for precision immobilization of multiple cameras in a multi-camera system |
US9761509B2 (en) * | 2015-12-29 | 2017-09-12 | United Microelectronics Corp. | Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device |
US9633955B1 (en) | 2016-08-10 | 2017-04-25 | United Microelectronics Corp. | Semiconductor integrated circuit structure including dielectric having negative thermal expansion |
CN107068611A (zh) * | 2016-12-23 | 2017-08-18 | 苏州能讯高能半导体有限公司 | 半导体芯片、半导体晶圆及半导体晶圆的制造方法 |
US10375845B2 (en) * | 2017-01-06 | 2019-08-06 | Microsoft Technology Licensing, Llc | Devices with mounted components |
US10403575B2 (en) * | 2017-01-13 | 2019-09-03 | Micron Technology, Inc. | Interconnect structure with nitrided barrier |
JP6697411B2 (ja) * | 2017-03-29 | 2020-05-20 | キオクシア株式会社 | 半導体装置の製造方法 |
US11121301B1 (en) | 2017-06-19 | 2021-09-14 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafers and their methods of manufacture |
US10658280B2 (en) * | 2017-12-29 | 2020-05-19 | Advanced Semiconductor Engineering, Inc. | Electrical device including a through-silicon via structure |
CN114361131A (zh) * | 2020-10-13 | 2022-04-15 | 长鑫存储技术有限公司 | 导电结构、半导体结构及其制作方法 |
CN113299602B (zh) * | 2021-06-01 | 2022-07-29 | 季华实验室 | 一种电镀铜-焦矾酸铜复合互连材料和硅基板及制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1510742A (zh) * | 2002-12-05 | 2004-07-07 | �Ҵ���˾ | 负热膨胀系统器件及微电子封装中的导电弹性体互连 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56150861U (zh) | 1980-04-14 | 1981-11-12 | ||
JPS56150861A (en) * | 1980-04-23 | 1981-11-21 | Toshiba Corp | Semiconductor device |
JP2004339018A (ja) * | 2003-05-16 | 2004-12-02 | Matsushita Electric Ind Co Ltd | 多孔質構造体およびそれを備えた複合体 |
US6924543B2 (en) | 2003-06-16 | 2005-08-02 | Intel Corporation | Method for making a semiconductor device having increased carrier mobility |
US20050110168A1 (en) * | 2003-11-20 | 2005-05-26 | Texas Instruments Incorporated | Low coefficient of thermal expansion (CTE) semiconductor packaging materials |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US7148577B2 (en) * | 2003-12-31 | 2006-12-12 | Intel Corporation | Materials for electronic devices |
JP2005244031A (ja) * | 2004-02-27 | 2005-09-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4766852B2 (ja) * | 2004-07-30 | 2011-09-07 | 学校法人東京理科大学 | タングステン酸ジルコニウムの製造方法 |
US7161730B2 (en) * | 2004-09-27 | 2007-01-09 | Idc, Llc | System and method for providing thermal compensation for an interferometric modulator display |
JP4593427B2 (ja) * | 2005-09-30 | 2010-12-08 | 株式会社フジクラ | 半導体装置及び半導体装置の製造方法 |
US8460777B2 (en) * | 2008-10-07 | 2013-06-11 | Alliant Techsystems Inc. | Multifunctional radiation-hardened laminate |
US20110204517A1 (en) | 2010-02-23 | 2011-08-25 | Qualcomm Incorporated | Semiconductor Device with Vias Having More Than One Material |
US8709948B2 (en) | 2010-03-12 | 2014-04-29 | Novellus Systems, Inc. | Tungsten barrier and seed for copper filled TSV |
CN102286760B (zh) | 2010-05-19 | 2016-10-05 | 诺发系统有限公司 | 用金属电化学填充高纵横比的大型凹入特征的方法、水溶液电镀槽溶液、电镀设备以及系统 |
KR101201720B1 (ko) | 2010-07-29 | 2012-11-15 | 삼성디스플레이 주식회사 | 표시 장치 및 유기 발광 표시 장치 |
US8404588B2 (en) | 2010-10-06 | 2013-03-26 | Electronics And Telecommunications Research Institute | Method of manufacturing via electrode |
JP6053256B2 (ja) * | 2011-03-25 | 2016-12-27 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体チップ及びその製造方法、並びに半導体装置 |
US20140117559A1 (en) * | 2012-03-30 | 2014-05-01 | Paul A. Zimmerman | Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (tsvs) |
US9330975B2 (en) | 2012-05-31 | 2016-05-03 | Micron Technology, Inc. | Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias |
US9099442B2 (en) | 2013-08-05 | 2015-08-04 | Micron Technology, Inc. | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods |
KR20150077969A (ko) * | 2013-12-30 | 2015-07-08 | 삼성디스플레이 주식회사 | 플렉시블 기판의 제조 방법, 플렉시블 표시 장치 및 플렉시블 표시 장치의 제조 방법 |
US20160276578A1 (en) * | 2015-03-18 | 2016-09-22 | Kabushiki Kaisha Toshiba | Device including magnetoresistive element and memory chip |
US9633955B1 (en) * | 2016-08-10 | 2017-04-25 | United Microelectronics Corp. | Semiconductor integrated circuit structure including dielectric having negative thermal expansion |
US10658280B2 (en) * | 2017-12-29 | 2020-05-19 | Advanced Semiconductor Engineering, Inc. | Electrical device including a through-silicon via structure |
US20190348344A1 (en) * | 2018-05-08 | 2019-11-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
-
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- 2013-08-05 US US13/959,429 patent/US9099442B2/en active Active
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- 2014-07-30 KR KR1020167005692A patent/KR101883578B1/ko active IP Right Grant
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1510742A (zh) * | 2002-12-05 | 2004-07-07 | �Ҵ���˾ | 负热膨胀系统器件及微电子封装中的导电弹性体互连 |
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US10546777B2 (en) | 2020-01-28 |
EP3031075A4 (en) | 2017-03-15 |
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