CN105609638A - 一种半导体层和tft的制备方法、tft、阵列基板 - Google Patents
一种半导体层和tft的制备方法、tft、阵列基板 Download PDFInfo
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- CN105609638A CN105609638A CN201610128473.9A CN201610128473A CN105609638A CN 105609638 A CN105609638 A CN 105609638A CN 201610128473 A CN201610128473 A CN 201610128473A CN 105609638 A CN105609638 A CN 105609638A
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Abstract
本发明实施例提供一种半导体层和TFT的制备方法、TFT、阵列基板,涉及显示技术领域,可解决现有技术中利用液相法制备的半导体层存在的迁移率低的问题,以及利用气相法制备的半导体层存在的半导体纯度不高、衬底受限、金属性CNT占比较高等问题。该半导体层的制备方法,包括:在衬底上形成二氧化硅薄膜,通过构图工艺处理,在待形成的半导体层的相对两侧形成侧壁;对侧壁进行氨基化处理,使侧壁的表面形成氨基硅氧烷单层自组装;对碳纳米管溶液进行羧基化,并将羧基化的碳纳米管溶液制作在形成有侧壁的衬底表面,形成碳纳米管薄膜;利用刻蚀工艺去掉除侧壁之间的其它部分的碳纳米管薄膜,形成半导体层。用于制备半导体层。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种半导体层和TFT的制备方法、TFT、阵列基板。
背景技术
碳纳米管(CarbonNanotube,简称CNT)自1991年1月被日本物理学家饭岛澄男使用高分辨透射电子显微镜从电弧法生产的碳纤维中发现以来,一直得到学术界和工业界的广泛关注和研究。CNT是一种管状的碳分子,管上每个碳原子采取SP2杂化,相互之间以碳-碳σ键结合起来,形成由六边形组成的蜂窝状结构作为CNT的骨架。CNT的分子结构决定了它具有一些独特的性质,如优异的电学性能、良好的导热性及机械强度高等。
目前,CNT被广泛应用在显示、传感器、射频电路、柔性电路等领域。CNT应用在TFT(ThinFilmTransistor,薄膜晶体管)方面,被用作半导体层的材料。现有技术中主要通过液相法和气相法制作CNT以作为TFT中半导体层。
液相法是将制备的CNT经过提纯后,在水或有机溶剂中进行分散,然后通过浸泡、旋涂、喷涂等方式制作在所需衬底上,并通过构图工艺而形成半导体层。然而,通过液相法在衬底上形成半导体层中的CNT一般是随机网络,CNT管-管结接触节点较多,从而造成迁移率一般不超过100cm2/V·s,这样就没有发挥CNT的潜能,而且CNT网络的均匀性和沟道定位不好。
气相法可以直接在衬底上制作CNT平行阵列,因而可大幅度减小CNT管-管结接触节点数目,使迁移率提高,但是气相法制备半导体层时,需要的温度较高,生长CNT平行阵列的衬底十分受限,且金属性CNT的占比很难降低,器件的开关性能比较差。
发明内容
本发明的实施例提供一种半导体层和TFT的制备方法、TFT、阵列基板,可解决现有技术中利用液相法制备的半导体层存在的迁移率低的问题,以及利用气相法制备的半导体层存在的半导体纯度不高、衬底受限、金属性CNT占比较高等问题。
为达到上述目的,本发明的实施例采用如下技术方案:
第一方面,提供一种半导体层的制备方法,包括:
在衬底上形成二氧化硅薄膜,通过构图工艺处理,在待形成的所述半导体层的相对两侧形成侧壁;对所述侧壁进行氨基化处理,使所述侧壁的表面形成氨基硅氧烷单层自组装;对碳纳米管溶液进行羧基化,并将羧基化的所述碳纳米管溶液制作在形成有所述侧壁的所述衬底表面,形成碳纳米管薄膜;利用刻蚀工艺去掉除所述侧壁之间的其它部分的碳纳米管薄膜,形成所述半导体层。
优选的,对所述侧壁进行氨基化处理,包括:将氨丙基硅烷溶液浸涂或喷淋在形成有所述侧壁的衬底上。
优选的,对碳纳米管溶液进行羧基化,包括:将强氧化剂与所述碳纳米管溶液混合,使所述碳纳米管溶液羧基化。
第二方面,提供一种TFT的制备方法,包括在衬底上形成栅极、栅绝缘层、半导体层、源极和漏极,所述半导体层通过上述的制备方法得到。
优选的,所述制备方法具体包括:在衬底上形成所述半导体层;在形成有所述半导体层的所述衬底上,形成所述栅绝缘层;在形成有所述栅绝缘层的所述衬底上形成金属薄膜,并通过一次构图工艺处理,形成所述栅极、所述源极和所述漏极;其中,所述源极和所述漏极与所述半导体层接触。
优选的,形成所述栅绝缘层,包括:在形成有所述半导体层的所述衬底上,形成栅绝缘薄膜,通过构图工艺处理,形成贯穿所述栅绝缘薄膜和所述半导体层的过孔,形成所述栅绝缘层;其中,所述过孔紧靠侧壁。
进一步优选的,形成所述栅绝缘层,包括:在形成有所述半导体层的所述衬底上,形成栅绝缘薄膜,通过构图工艺处理,形成贯穿所述栅绝缘薄膜和所述半导体层的过孔,形成所述栅绝缘层;其中,所述过孔紧靠侧壁。
优选的,所述衬底为柔性衬底或硬质衬底。
第三方面,提供一种TFT,包括:栅极、栅绝缘层、半导体层、源极和漏极,还包括设置在所述半导体层两侧的侧壁;所述侧壁包括二氧化硅材料的主体和覆盖所述主体表面的氨基硅氧烷单层自组装。
优选的,所述半导体层靠近所述衬底设置;所述栅极、所述源极和所述漏极同层设置;所述栅绝缘层设置在所述半导体层与所述栅极、所述源极和所述漏极之间;其中,所述源极和所述漏极与所述半导体层接触。
进一步优选的,所述源极和所述漏极通过所述栅绝缘层上的过孔与所述侧壁和所述半导体层均接触。
第四方面,提供一种阵列基板,包括上述的TFT。
本发明实施例提供一种半导体层和TFT的制备方法、TFT、阵列基板,通过在待形成的半导体层的相对两侧形成SiO2材料的侧壁,并通过对侧壁进行氨基化处理使侧壁表面形成氨基硅氧烷单层自组装,再将羧基化的CNT溶液制作在形成有侧壁的衬底表面,使羧基化的CNT溶液与侧壁表面形成的氨基硅氧烷单层自组装进行三维空间自组装,这样会使得CNT管-管结接触节点数目减少,从而使得制备的半导体层的迁移率提高。与现有的液相法制备的半导体层相比,由于本发明实施例的半导体层中的CNT管-管结接触节点数目较少,因而半导体层的迁移率更高,且制备的半导体层中CNT形成的是平行阵列,因而CNT的均匀性和沟道定位都较好;与现有的气相法制备的半导体层相比,衬底不受耐高温材料的限制,且半导体层的纯度更高,金属性CNT占比更低。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种半导体层的制备方法的流程示意图;
图2为本发明实施例提供的一种在衬底上形成侧壁的结构示意图;
图3为本发明实施例提供的一种在衬底上形成SiO2薄膜的结构示意图;
图4为本发明实施例提供的一种在衬底上形成半导体层的结构示意图;
图5为本发明实施例提供的一种TFT的结构示意图一;
图6为本发明实施例提供的一种TFT的结构示意图二;
图7为本发明实施例提供的一种TFT的制备方法的流程示意图;
图8为本发明实施例提供的一种LCD的阵列基板的结构示意图一;
图9为本发明实施例提供的一种LCD的阵列基板的结构示意图二;
图10为本发明实施例提供的一种OLED的阵列基板的结构示意图。
附图说明:
10-衬底;20-侧壁;30-半导体层;301-CNT薄膜;40-栅绝缘层;50-源极;60-漏极;70-栅极;801-像素电极;802-公共电极;803-阳极;804-阴极;805-有机材料功能层。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供一种半导体层的制备方法,如图1所示,包括:
S100、如图2所示,在衬底10上形成SiO2(二氧化硅)薄膜,通过构图工艺处理,在待形成的半导体层的相对两侧形成侧壁20。
即,侧壁20的材料为SiO2。
其中,衬底10可以是柔性衬底,例如PET(Polyethyleneterephthalate,聚对苯二甲酸乙二酯)衬底、PI(Polyimide,聚酰亚胺)衬底等。当然也可以是硬质衬底,例如,玻璃衬底、氧化硅衬底、氮化硅衬底等。
此处,例如可以采用PECVD(PlasmaEnhancedChemicalVaporDeposition,等离子体化学气相沉积法)、CVD(ChemicalVaporDeposition,化学气相沉积法)等方法形成SiO2薄膜。
在此基础上,通过构图工艺处理,在待形成的半导体层的相对两侧形成侧壁20例如可以为:在形成有SiO2薄膜的衬底10上形成光刻胶,使掩模板的不透光部分与待形成的侧壁20的区域对应,掩模板的透光部分与其他区域对应,并进行曝光、显影,然后采用刻蚀工艺去除显影后露出的SiO2薄膜(即与掩模板的透光部分对应的区域的SiO2薄膜),从而形成侧壁20,之后可将侧壁20上的光刻胶去除。其中,上述刻蚀工艺可以采用RIE(ReactiveIonEtching,反应离子刻蚀)或ICP(InductivelyCoupledPlasma,电感耦合等离子体)等方式。
需要说明的是,对于侧壁20的高度和长度,可根据待形成的半导体层的高度和区域而定;对于侧壁20的宽度(以图2中水平方向为参考),以不影响该半导体层所应用的器件例如薄膜晶体管的整体尺寸为准。
S101、对侧壁20进行氨基化处理,使侧壁20的表面形成氨基硅氧烷单层自组装。
其中,由于侧壁20的材料为SiO2,在对侧壁20进行氨基化处理后,位于侧壁20外表面(即侧壁20的除与衬底20接触的表面之外的其余表面)的SiO2可以与上述氨基化处理所采用的溶液进行反应,因此,可在侧壁20的所有外表面均形成氨基硅氧烷单层自组装。
此处,可通过浸涂或喷淋等方式,对侧壁20进行氨基化处理。其中,不对上述氨基化处理所采用的溶液进行限定,以能在侧壁20表面形成氨基硅氧烷单层自组装为准。
需要说明的是,本发明实施例中,当对侧壁20进行氨基化处理后,仍然可将其称为侧壁20。
S102、如图3所示,对CNT溶液进行羧基化,并将羧基化的CNT溶液制作在形成有侧壁20的衬底10表面,形成CNT薄膜301。
其中,由于在侧壁20的每个外表面均形成有氨基硅氧烷单层自组装,因此,当羧基化的CNT溶液制作在形成有侧壁20的衬底10表面时,羧基化的CNT溶液便可与其接触的侧壁20的每个表面(即上述侧壁20的每个外表面)的氨基硅氧烷单层自组装进行三维空间自组装。
当羧基化的CNT溶液与侧壁20的每个外表面形成的氨基硅氧烷单层自组装接触时,可以在每个外表面上,形成平行排列的CNT。
其中,虽然针对每个侧壁20的外表面,组装在其上的CNT都平行排列,但是组装在非平行的外表面上的CNT并不平行。
例如,在两个侧壁20相对的外表面上,可形成垂直于该相对的外表面的平行排列的CNT,在侧壁20的相对衬底10的上表面上,则形成垂直于该上表面的平行排列的CNT,在其他侧壁20的外表面上,也可形成垂直该外表面的平行排列的CNT。
在此基础上,由于本发明实施例中是将形成在两个侧壁20之间的CNT薄膜作为半导体层30,除此之外其余薄膜都会被去除,因而,在形成CNT薄膜时,虽然位于侧壁20的不同表面上的CNT的方向可能不同,但是由于除两个侧壁20之间的CNT薄膜都会被刻蚀,因此,最终形成在两个侧壁20之间的半导体层30中的CNT仍是平行排列的。
需要说明的是,在理想情况下,在每个外表面上都可以形成垂直于该外表面的平行排列的CNT,然而,在实际制作过程中,平行排列的CNT可能不能理想的完全垂直于相应的外表面,但是CNT仍是平行排列的。
此处,可将羧基化的CNT溶液通过浸涂或喷淋等方式,制作在形成有侧壁20的衬底10表面。其中,不对上述羧基化所采用的溶液进行限定,以在通过液相法将羧基化的CNT溶液涂在衬底10表面上时,使羧基化的CNT溶液与经过氨基化处理的侧壁20进行三维空间自组装即可。
对于CNT溶液的制备方法:可先通过石墨电弧法、催化裂解法或激光蒸发法等方法制备CNT,再利用物理或化学方法对CNT进行提纯,最后在水或有机溶剂(例如,乙醇或异丙醇等)中对CNT进行分散以形成分散均匀的高纯度(99%)半导体性CNT溶液。
S103、如图4所示,利用刻蚀工艺去掉除侧壁20之间的其它部分的CNT薄膜,形成半导体层30。
由于两个侧壁20相对的外表面具有一定的高度和宽度,因而当羧基化的CNT溶液与侧壁20表面的氨基硅氧烷单层自组装接触时,在两个侧壁20的相对外表面的高度和宽度方向都可以进行羧基化的CNT溶液与氨基硅氧烷单层自组装的自组装,从而在两个侧壁20的相对外表面的高度和宽度方向上形成平行排列的CNT,因此在两个侧壁20之间就可以形成三维(即两个侧壁20之间的长度、两个侧壁20的相对外表面的高度和宽度方向上)平行排列的CNT,即形成的半导体层30中的CNT三维平行排列。
此处,利用刻蚀工艺去掉除侧壁20之间的其它部分的CNT薄膜例如可以为:在形成有CNT薄膜301的衬底10上形成光刻胶,使掩模板的不透光部分与待形成的半导体层的区域对应,掩模板的透光部分与其他区域对应,进行曝光、显影后,采用刻蚀工艺去除显影后露出的CNT薄膜(即与掩模板的透光部分对应的区域的CNT薄膜),从而形成半导体层30,之后可将半导体层30上的光刻胶去除。其中,上述刻蚀工艺可以采用RIE或ICP等方式。
本发明实施例提供一种半导体层的制备方法,通过在待形成的半导体层的相对两侧形成SiO2材料的侧壁20,并通过对侧壁20进行氨基化处理使侧壁20表面形成氨基硅氧烷单层自组装,再将羧基化的CNT溶液制作在形成有侧壁20的衬底10表面,使羧基化的CNT溶液与侧壁20表面形成的氨基硅氧烷单层自组装进行三维空间自组装,这样会使得CNT管-管结接触节点数目减少,从而使得制备的半导体层30的迁移率提高。与现有的液相法制备的半导体层相比,由于本发明实施例的半导体层30中的CNT管-管结接触节点数目较少,因而半导体层30的迁移率更高,且制备的半导体层30中CNT形成的是平行阵列,因而CNT的均匀性和沟道定位都较好;与现有的气相法制备的半导体层30相比,衬底10不受耐高温材料的限制,且半导体层30的纯度更高,金属性CNT占比更低。
基于上述,步骤S101中对侧壁20进行氨基化处理,具体包括:
将氨丙基硅烷溶液浸涂或喷淋在形成有侧壁20的衬底10上。
将氨丙基硅烷溶液浸涂或喷淋在形成有侧壁20的衬底上时,氨丙基硅烷会和SiO2反应,从而在侧壁20的表面形成氨基硅氧烷单层自组装。
此处,氨丙基硅烷溶液可以包括:APTES(氨丙基三乙氧基硅烷)溶液、APTMS(氨丙基三甲氧基硅烷)等。
此处,将氨丙基硅烷溶液浸涂或喷淋在形成有侧壁20的衬底上的时间以能使氨丙基硅烷和SiO2发生反应且在侧壁20表面形成氨基硅氧烷单层自组装为准。
步骤S102中对CNT溶液进行羧基化,具体包括:将强氧化剂与CNT溶液混合,使CNT溶液羧基化。
其中,强氧化剂例如可以为硝酸、浓硫酸等。
在对CNT溶液进行羧基化时,对于强氧化剂与CNT溶液的比例,以能确保CNT溶液中的CNT均被羧基化为准。此处,还可以对强氧化剂与CNT混合溶液进行加热,搅拌等方式以加快对CNT溶液的羧基化。其中,CNT溶液为分散均匀的高纯度(≥99%)半导体性CNT溶液。
本发明实施例还提供了一种TFT的制备方法,如图5和图6所示,包括在衬底10上形成栅极70、栅绝缘层40、半导体层30、源极50和漏极60,其中,半导体层30通过上述的制备方法得到。
其中,衬底10可以是柔性衬底,例如PET衬底、PI衬底等;当然也可以是硬质衬底,例如,玻璃衬底、氧化硅衬底、氮化硅衬底等。
此处,本发明实施例制备的TFT可以是顶栅型TFT、低栅型TFT或双栅型TFT。
本发明实施例提供了一种TFT的制备方法,由于在形成其中的半导体层30时,需通过在待形成的半导体层的相对两侧形成SiO2材料的侧壁20,并通过对侧壁20进行氨基化处理使侧壁20表面形成氨基硅氧烷单层自组装,再将羧基化的CNT溶液制作在形成有侧壁20的衬底10表面,使羧基化的CNT溶液与侧壁20表面形成的氨基硅氧烷单层自组装进行三维空间自组装,这样会使得半导体层30中的CNT管-管结接触节点数目减少,从而使得制备的半导体层30的迁移率提高。与现有的液相法制备的半导体层相比,由于本发明实施例的半导体层30中的CNT管-管结接触节点数目较少,因而半导体层30的迁移率更高,且制备的半导体层30中CNT形成的是平行阵列,因而CNT的均匀性和沟道定位都较好;与现有的气相法制备的半导体层30相比,衬底10不受耐高温材料的限制,且半导体层30的纯度更高,金属性CNT占比更低,TFT的开关性能较好。
进一步地,由于半导体层30形成在两个侧壁20之间,而两个侧壁20在制作过程中可以在衬底10上精确进行定位,因而形成在两个侧壁20之间的半导体层30便可以进行定位,从而使得形成的TFT可以大规模在衬底10上进行定位和集成应用。
优选的,如图7所示,上述TFT的制备方法具体包括:
S200、如图5和图6所示,在衬底10上形成半导体层30。
其中,在衬底10上形成半导体层30可以通过上述步骤S100-S103制备半导体层30的方法得到。
S201、如图5和图6所示,在形成有半导体层30的衬底10上,形成栅绝缘层40。
其中,可以通过ALD(AtomicLayerDeposition,原子层沉积法)或PECVD(等离子体化学气相沉积,PlasmaEnhancedChemicalVaporDeposition)等方法在形成有半导体层30的衬底10上形成栅绝缘层40。
S202、如图5和图6所示,在形成有栅绝缘层40的衬底10上形成金属薄膜,并通过一次构图工艺处理,形成栅极70、源极50和漏极60。其中,源极50和漏极60与半导体层30接触。
其中,栅极70、源极50和漏极60的材料可以为Pd(钯)、Ti(钛)、Al(铝)、Cr(铬)、Au(金)、Pt(铂)、TiN(氮化钛)或TaN(氮化钽)中的一种或几种材料的组合。
源极50和漏极60与半导体层30接触,可以是如图5所示的,先在栅绝缘层40上形成过孔,之后通过蒸镀或溅射工艺形成金属薄膜,并通过构图工艺处理在过孔处形成源极50和漏极60,源极50和漏极60与半导体层30接触。当然也可以是如图6所示的,先形成贯穿栅绝缘层40和半导体层30的过孔,之后通过蒸镀或溅射工艺形成金属薄膜,并通过构图工艺处理在过孔处形成源极50和漏极60,源极50和漏极60与半导体层30接触。
本发明实施例中,由于栅极70、源极50和漏极60是通过一次构图工艺形成,因而减少了构图工艺次数,提高了生产效率。
进一步优选的,形成栅绝缘层40,具体包括:
参考图6所示,在形成有半导体层30的衬底10上,形成栅绝缘薄膜,通过构图工艺处理,形成贯穿栅绝缘薄膜和半导体层30的过孔,形成栅绝缘层40;其中,过孔紧靠侧壁20。
具体的,形成上述过孔例如可以为:在形成有栅绝缘薄膜的衬底10上形成光刻胶,使掩模板的透光部分与待形成过孔的区域对应,掩模板的不透光部分与其他区域对应,并进行曝光、显影,然后采用刻蚀工艺去除显影后露出的栅绝缘薄膜,以及栅绝缘薄膜下方的半导体层薄膜,从而形成贯穿栅绝缘薄膜和半导体层30的过孔,形成栅绝缘层40,之后可将栅绝缘层40上的光刻胶去除。其中,上述刻蚀工艺可以利用RIE或ICP等方式。
本发明实施例提供一种TFT,如图5和图6所示,包括:栅极70、栅绝缘层40、半导体层30、源极50和漏极60,还包括设置在半导体层30两侧的侧壁20;侧壁20包括SiO2材料的主体和覆盖于主体表面的氨基硅氧烷单层自组装。
需要说明的是,第一,侧壁20的SiO2材料的主体可以通过先在衬底10上形成SiO2薄膜,并通过构图工艺处理后在待形成的半导体层的相对两侧形成。
第二,可以将氨丙基硅烷溶液浸涂或喷淋在形成有SiO2材料的主体的衬底10上,氨丙基硅烷会和SiO2反应,从而在侧壁20的SiO2材料主体的表面形成覆盖于主体表面的氨基硅氧烷单层自组装。
本发明实施例提供了一种TFT,由于半导体层30中的CNT管-管结接触节点数目减少,因而使得制备的半导体层30的迁移率提高,且由于制备的半导体层30中CNT形成的是平行阵列,因而CNT的均匀性和沟道定位都较好;此外,衬底10也不受耐高温材料的限制,且半导体层30的纯度更高,金属性CNT占比更低,TFT的开关性能较好。进一步地,由于半导体层30形成在两个侧壁20之间,而两个侧壁20在制作过程中可以在衬底10上精确进行定位,因而形成在两个侧壁20之间的半导体层30便可以进行定位,从而使得形成的TFT可以大规模在衬底10上进行定位和集成应用。
优选的,如图5和图6所示,半导体层30靠近衬底10设置;栅极70、源极50和漏极60同层设置;栅绝缘层40设置在半导体层30与栅极70、源极50和漏极60之间。其中,源极50和漏极60与半导体层30接触。
本发明实施例中,由于栅极70、源极50和漏极60同层设置,因而可以通过一次构图工艺形成,从而减少了构图工艺次数,提高了生产效率。
进一步优选的,如图6所示,源极50和漏极60通过栅绝缘层40上的过孔与侧壁20和半导体层30均接触。
本发明实施例还提供一种阵列基板,包括上述的TFT。
其中,阵列基板中的每个子像素除包括上述的TFT外,还包括与漏极60电联接的第一电极。
具体的,当该阵列基板为液晶显示器(LiquidCrystalDisplay,简称LCD)的阵列基板时,如图8所示,第一电极为像素电极801。此外如图9所示,该阵列基板还可以包括公共电极802。
当该阵列基板为有机电致发光二极管(OrganicLight-EmittingDiode,简称OLED)显示器的阵列基板时,如图10所示,第一电极为阳极803,在此基础上,该阵列基板还包括阴极804,以及位于阳极803和阴极804之间的有机材料功能层805。
本发明实施例提供了一种阵列基板,由于半导体层30中的CNT管-管结接触节点数目减少,因而使得制备的半导体层30的迁移率提高,且由于制备的半导体层30中CNT形成的是平行阵列,因而CNT的均匀性和沟道定位都较好;此外,衬底10也不受耐高温材料的限制,且半导体层30的纯度更高,金属性CNT占比更低,TFT的开关性能较好。进一步地,由于半导体层30形成在两个侧壁20之间,而两个侧壁20在制作过程中可以在衬底10上精确进行定位,因而形成在两个侧壁20之间的半导体层30便可以进行定位,从而使得形成的TFT可以大规模在衬底10上进行定位和集成应用。
本发明实施例还提供一种显示面板,包括上述的阵列基板以及对盒基板。
具体的,当阵列基板为LCD的阵列基板时,该显示面板还可以包括彩膜基板,以及位于阵列基板和彩膜基板之间的液晶层。
当阵列基板为OLED显示器的阵列基板时,该显示面板还可以包括封装基板。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (11)
1.一种半导体层的制备方法,其特征在于,包括:
在衬底上形成二氧化硅薄膜,通过构图工艺处理,在待形成的所述半导体层的相对两侧形成侧壁;
对所述侧壁进行氨基化处理,使所述侧壁的表面形成氨基硅氧烷单层自组装;
对碳纳米管溶液进行羧基化,并将羧基化的所述碳纳米管溶液制作在形成有所述侧壁的所述衬底表面,形成碳纳米管薄膜;
利用刻蚀工艺去掉除所述侧壁之间的其它部分的碳纳米管薄膜,形成所述半导体层。
2.根据权利要求1所述的制备方法,其特征在于,对所述侧壁进行氨基化处理,包括:
将氨丙基硅烷溶液浸涂或喷淋在形成有所述侧壁的衬底上。
3.根据权利要求1所述的制备方法,其特征在于,对碳纳米管溶液进行羧基化,包括:
将强氧化剂与所述碳纳米管溶液混合,使所述碳纳米管溶液羧基化。
4.一种TFT的制备方法,包括在衬底上形成栅极、栅绝缘层、半导体层、源极和漏极,其特征在于,所述半导体层通过权利要求1-3任一项所述的制备方法得到。
5.根据权利要求4所述的制备方法,其特征在于,所述制备方法具体包括:
在衬底上形成所述半导体层;
在形成有所述半导体层的所述衬底上,形成所述栅绝缘层;
在形成有所述栅绝缘层的所述衬底上形成金属薄膜,并通过一次构图工艺处理,形成所述栅极、所述源极和所述漏极;其中,所述源极和所述漏极与所述半导体层接触。
6.根据权利要求5所述的制备方法,其特征在于,形成所述栅绝缘层,包括:
在形成有所述半导体层的所述衬底上,形成栅绝缘薄膜,通过构图工艺处理,形成贯穿所述栅绝缘薄膜和所述半导体层的过孔,形成所述栅绝缘层;其中,所述过孔紧靠侧壁。
7.根据权利要求4-6任一项所述的制备方法,其特征在于,所述衬底为柔性衬底或硬质衬底。
8.一种TFT,包括:栅极、栅绝缘层、半导体层、源极和漏极,其特征在于,还包括设置在所述半导体层两侧的侧壁;所述侧壁包括二氧化硅材料的主体和覆盖所述主体表面的氨基硅氧烷单层自组装。
9.根据权利要求8所述的TFT,其特征在于,所述半导体层靠近所述衬底设置;
所述栅极、所述源极和所述漏极同层设置;
所述栅绝缘层设置在所述半导体层与所述栅极、所述源极和所述漏极之间;其中,所述源极和所述漏极与所述半导体层接触。
10.根据权利要求9所述的TFT,其特征在于,所述源极和所述漏极通过所述栅绝缘层上的过孔与所述侧壁和所述半导体层均接触。
11.一种阵列基板,其特征在于,包括权利要求8-10任一项所述的TFT。
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US20180108783A1 (en) | 2018-04-19 |
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