1355083 100年03月11日按正替換百 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種薄膜電晶體基板製造方法。 【先前技術】 [0002] 目前，液晶顯示器逐漸取代用於計算機之傳統陰極射線 管（Cathode Ray Tube, CRT)顯示器，而且，由於液晶 顯示器具輕、薄、小等特點，使其非常適合應用於桌上 型電腦、膝上型電腦、個人數字助理（Personal Digital Assistant, PDA) ' 便擴式電話、 電視及多種辦 公自動化與視聽設備中。液晶面板是其主要元件，其一 般包括一薄膜電晶體基板、一彩色濾光片基板及夾於該 薄膜電晶體基板與該彩色濾光片基板之間之液晶層。 [0003] 請參閱圖1，係一種先前技術薄膜電晶體基板100之結構 示意圖。該薄膜電晶體基板100包括一基底101、一位於 基底101上之閘極102、一位於該閘極102及該基底101上 之閘極絕緣層103、一位於該閘極絕緣層103上之半導體 層104、一位於該半導體層104及該閘極絕緣層103上之 源極105與汲極106、一位於該閘極絕緣層103、該源極 105及該汲極106上之鈍化層107以及一位於該鈍化層107 上之像素電極108。 [0004] 請參照圖2，係該薄膜電晶體基板100之製造方法之流程 圖。該製造方法採用五道光罩製程，包括以下步驟： [0005] —、第一道光罩製程 [0006] (1)形成閘極金屬層：提供一絕緣基底101，在該絕緣 096130513 表單編號A0101 第3頁/共32頁 1003082443-0 1355083 100年03月11日梭正替換頁 基底101上依序形成一閘極金屬層及一第一光阻層； [0007] (2)形成閘極：以第一道光罩之圖案對該第一光阻層進 行曝光顯影，從而形成一第一光阻層圖案；以該第一光 阻層圖案為遮罩對該閘極金屬層進行蝕刻，進而形成一 閘極1 0 2，移除第一光阻層。 [0008] 二、第二道光罩製程 [0009] (3)形成閘極絕緣層、非晶矽及摻雜非晶矽層：於具有 該閘極之絕緣基底上形成一閘極絕緣層103、一非晶矽及 摻雜非晶矽層及一第二光阻層； [0010] (4)形成半導體層：以第二道光罩之圖案對該第二光阻 層進行曝光顯影，從而形成一第二光阻層圖案；以該第 二光阻層圖案為遮罩對該摻雜非晶矽層及該非晶矽層進 行蝕刻，進而形成具有一預定圖案之半導體層104，移除 第二光阻層。 [0011] 三、第三道光罩製程 [0012] (5)形成源/汲極金屬層：於該基底及該半導體層圖案上 形成一源/汲·極金屬層及一第三光阻層； [0013] (6)形成源/汲極金屬層圖案：以第三道光罩之圖案對該 第三光阻層進行曝光顯影，從而形成一第三光阻層圖案 ;以該第三光阻層圖案為遮罩對該源/汲極金屬層進行蝕 刻，進而形成一源極105及一汲極106，並對摻雜非晶矽 層進行蝕刻形成一溝槽，移除第三光阻層。 [0014] 四、第四道光罩製程 096130513 表單編號A0101 第4頁/共32頁 1003082443-0 1355083 - 100年03月11日梭正替換頁 [0015] (7)形成鈍化層：於具有該閘極、源極及汲極的基底上 沉積一純化層及一第四光阻層； [0016] (8)形成鈍化層圖案：以第四道光罩之圖案對該第四光 阻層進行曝光顯影，從而形成一第四光阻層圖案；以該 第四光阻層圖案為遮罩對該鈍化層進行蝕刻，進而定義 出一鈍化層107之圖案，移除第四光阻層。 [0017] 五、第五道光罩製程 [0018] (9)形成一導體層：於具有該閘極、源極、汲極及鈍化 層圖案的基底上形成一導體層及一第五光阻層； [0019] (10)形成像素電極：以第五道光罩之圖案對該第五光阻 層進行曝光顯影，從而形成一第五光阻層圖案；以該第 五光阻層圖案為遮罩對該導體層進行蝕刻，進而圖案化 該導體層，形成像素電極108，移除該第五光阻層。 [0020] 惟，該方法需要較多光罩製程，而光罩製程通常較為複 雜且成本較高，從而使得製造成本較高。另外，於每一 次光罩製程之微影生產過程中，灰塵的污染以及曝光之 好壞會直接影響整個產品之良率，因此，光罩製程較多 易增加降低產品良率之機會。 【發明内容】 [0021] 有鑑於此，提供一種製程簡單且成本低之薄膜電晶體基 板製造方法實為必要。 [0022] 一種薄膜電晶體基板製造方法，其步驟包括提供一絕緣 基底；於該絕緣基底上沉積一第一閘極絕緣層；於一第 一道光罩製程在該第一閘極絕緣層上形成一閘極槽；於 096130513 表單編號 A0101 第 5 頁/共 32 頁 1003082443-0 1355083 100年03月11日核正替换頁 剩餘之第一閘極絕緣層上及該閘極槽内沉積一閘極金屬 層；對該閘極金屬層進行化學機械研磨形成一閘極；於 剩餘之第一閘極絕緣層及該閘極上依序沉積一第二閘極 絕緣層、一半導體層及一第一鈍化層；於一第二道光罩 製程在該第一鈍化層上形成一源極槽及一汲極槽；於剩 餘之第一鈍化層上、該源極槽及一汲極槽内沉積一源/汲 極金屬層；對該源/汲極金屬層進行化學機械研磨形成一 源極及一汲極；於該第一鈍化層及該源極、汲極上沉積 一第二鈍化層；於一第三道光罩製程在該第二鈍化層、 第一鈍化層、半導體層及第二閘極絕緣層上形成一像素 電極槽並使得汲極暴露出來；在剩餘之第二鈍化層上、 暴露之汲極上、像素電極槽内沉積一導體層；於一第四 道光罩製程在該導體層上形成一像素電極。 [0023] 相較於先前技術，該製造方法利用化學機械研磨配合光 罩製程，實現用四道光罩製程形成薄膜電晶體基板，無 需用一道光罩製程去單獨形成具有預定圖案之鈍化層， 從而比先前技術節省一道光罩製程，光罩次數減少，製 程簡化，可有效降低成本。 【實施方式】 [0024] 請參閱圖3，係本發明薄膜電晶體基板之一較佳實施方式 所揭示之結構示意圖。該薄膜電晶體基板200包括一絕緣 基底201、設置於該絕緣基底201上之一閘極213及一第 一閘極絕緣層202、依序設置於該第一閘極絕緣層202上 之第二閘極絕緣層206及半導體層207、設置於該半導體 層207上之一第一鈍化層208、一源極214及一汲極215、 096130513 表單編號A0101 第6頁/共32頁 1003082443-0 1355083 100年03月11日修正替换頁 設置於該半導體層207及源極214上之第二鈍化層209及 一設置於該汲極215及第一閘極絕緣層202上之像素電極 216。 [0025] 請參閱圖4，係圖3所示薄膜電晶體基板200製造方法之一 較佳實施方式之流程圖。該薄膜電晶體基板200之製造方 法包括四道光罩製程，其具體步驟如下： [0026] 一、第一道光罩製程 [0027] (1)形成第一閘極絕緣層； [0028] 請參閱圖5，提供一絕緣基底201，該絕緣基底201可以為 玻璃、石英或者陶瓷等絕緣材質；用化學氣相沉積法 (chemical vapor deposition, CVD)，反應氣體為 矽烷（SiH,)與氨氣（NH。），於該絕緣基底201上形成一氮 4 3 化矽（SiN )構成之第一閘極絕緣層202 ;在該第一閘極絕1355083 On March 11, 100, according to the positive replacement, the invention is as follows: [Technical Field of the Invention] [0001] The present invention relates to a method for manufacturing a thin film transistor substrate. [Prior Art] [0002] At present, liquid crystal displays are gradually replacing the traditional cathode ray tube (CRT) displays for computers, and because of their light, thin and small liquid crystal display devices, they are very suitable for application. Desktop computers, laptops, and personal digital assistants (PDAs) 'expanded phones, televisions, and a variety of office automation and audiovisual equipment. The liquid crystal panel is a main component thereof, and generally comprises a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Please refer to FIG. 1, which is a schematic structural view of a prior art thin film transistor substrate 100. The thin film transistor substrate 100 includes a substrate 101, a gate 102 on the substrate 101, a gate insulating layer 103 on the gate 102 and the substrate 101, and a semiconductor on the gate insulating layer 103. a layer 104, a source 105 and a drain 106 on the semiconductor layer 104 and the gate insulating layer 103, a passivation layer 107 on the gate insulating layer 103, the source 105 and the drain 106, and A pixel electrode 108 on the passivation layer 107. Referring to FIG. 2, a flow chart of a method of manufacturing the thin film transistor substrate 100 is shown. The manufacturing method uses a five-mask process, including the following steps: [0005] -, the first mask process [0006] (1) forming a gate metal layer: providing an insulating substrate 101, in the insulation 096130513 Form No. A0101 3 pages/32 pages 1003082443-0 1355083 On March 11th, 100th, a gate metal layer and a first photoresist layer are sequentially formed on the page substrate 101; [2] forming a gate: Forming a first mask to expose the first photoresist layer to form a first photoresist layer pattern; etching the gate metal layer with the first photoresist layer pattern as a mask to form A gate 1 0 2 removes the first photoresist layer. [0008] Second, the second mask process [0009] (3) forming a gate insulating layer, an amorphous germanium and a doped amorphous germanium layer: forming a gate insulating layer 103 on the insulating substrate having the gate, An amorphous germanium and doped amorphous germanium layer and a second photoresist layer; [410] forming a semiconductor layer: exposing and developing the second photoresist layer in a pattern of a second mask to form a a second photoresist layer pattern; etching the doped amorphous germanium layer and the amorphous germanium layer with the second photoresist layer pattern as a mask, thereby forming a semiconductor layer 104 having a predetermined pattern, and removing the second light Resistance layer. [0011] Third, the third mask process [0012] (5) forming a source / drain metal layer: forming a source / germanium electrode layer and a third photoresist layer on the substrate and the semiconductor layer pattern; [0013] (6) forming a source/dual metal layer pattern: exposing and developing the third photoresist layer in a pattern of a third mask to form a third photoresist layer pattern; and the third photoresist layer The pattern is a mask to etch the source/drain metal layer to form a source 105 and a drain 106, and the doped amorphous germanium layer is etched to form a trench to remove the third photoresist layer. [0014] Fourth, the fourth mask process 096130513 Form No. A0101 Page 4 / Total 32 pages 1003082443-0 1355083 - October 31, 100 shuttle replacement page [0015] (7) Forming a passivation layer: with the gate Depositing a purification layer and a fourth photoresist layer on the substrate of the pole, the source and the drain; (8) forming a passivation layer pattern: exposing and developing the fourth photoresist layer in a pattern of a fourth mask Forming a fourth photoresist layer pattern; etching the passivation layer with the fourth photoresist layer pattern as a mask, thereby defining a pattern of the passivation layer 107, and removing the fourth photoresist layer. [0017] Fifth, the fifth mask process [0018] (9) forming a conductor layer: forming a conductor layer and a fifth photoresist layer on the substrate having the gate, source, drain and passivation layer patterns [0019] (10) forming a pixel electrode: exposing and developing the fifth photoresist layer in a pattern of a fifth mask to form a fifth photoresist layer pattern; using the fifth photoresist layer pattern as a mask The conductor layer is etched, and the conductor layer is patterned to form a pixel electrode 108, and the fifth photoresist layer is removed. [0020] However, this method requires more mask processes, and the mask process is generally more complicated and costly, resulting in higher manufacturing costs. In addition, in the lithography production process of each mask process, dust pollution and exposure will directly affect the yield of the entire product. Therefore, the mask process is more likely to increase the chance of reducing product yield. SUMMARY OF THE INVENTION [0021] In view of the above, it is necessary to provide a method for fabricating a thin film transistor substrate which is simple in process and low in cost. [0022] A method for fabricating a thin film transistor substrate, the method comprising: providing an insulating substrate; depositing a first gate insulating layer on the insulating substrate; and forming a first mask on the first gate insulating layer Forming a gate trench; at 096130513 Form No. A0101 Page 5 of 32 1003082443-0 1355083 On March 11th, 100th, the first gate insulating layer remaining on the replacement page and a gate deposited in the gate trench a metal layer; a chemical mechanical polishing of the gate metal layer to form a gate; a second gate insulating layer, a semiconductor layer and a first layer are sequentially deposited on the remaining first gate insulating layer and the gate a passivation layer; forming a source trench and a drain trench on the first passivation layer in a second mask process; depositing a source on the remaining first passivation layer, the source trench and a drain trench / a drain metal layer; chemically mechanically grinding the source/drain metal layer to form a source and a drain; depositing a second passivation layer on the first passivation layer and the source and the drain; Three reticle processes in the second passivation layer, first passivation Forming a pixel electrode trench on the layer, the semiconductor layer and the second gate insulating layer and exposing the drain; depositing a conductor layer on the remaining second passivation layer, the exposed drain, and the pixel electrode trench; A four-mask process forms a pixel electrode on the conductor layer. [0023] Compared with the prior art, the manufacturing method utilizes chemical mechanical polishing in combination with a mask process to realize formation of a thin film transistor substrate by a four-mask process without separately forming a passivation layer having a predetermined pattern by a mask process. Compared with the prior art, it saves a mask process, the number of masks is reduced, and the process is simplified, which can effectively reduce the cost. Embodiments [0024] Referring to Figure 3, there is shown a schematic structural view of a preferred embodiment of a thin film transistor substrate of the present invention. The thin film transistor substrate 200 includes an insulating substrate 201, a gate 213 disposed on the insulating substrate 201, a first gate insulating layer 202, and a second layer sequentially disposed on the first gate insulating layer 202. a gate insulating layer 206 and a semiconductor layer 207, a first passivation layer 208, a source 214, and a drain 215, 096130513 disposed on the semiconductor layer 207. Form No. A0101 Page 6 of 32 Page 303082443-0 1355083 The second passivation layer 209 disposed on the semiconductor layer 207 and the source 214 and the pixel electrode 216 disposed on the drain 215 and the first gate insulating layer 202 are modified. Referring to FIG. 4, a flow chart of a preferred embodiment of a method for fabricating the thin film transistor substrate 200 shown in FIG. The manufacturing method of the thin film transistor substrate 200 includes four mask processes, and the specific steps thereof are as follows: [0026] First, the first mask process [0027] (1) forming a first gate insulating layer; [0028] 5, an insulating substrate 201 is provided, which may be an insulating material such as glass, quartz or ceramic; by chemical vapor deposition (CVD), the reaction gas is decane (SiH) and ammonia ( NH.), forming a first gate insulating layer 202 composed of nitrogen arsenide (SiN) on the insulating substrate 201;
X 緣層202上沉積一第一光阻層231。 [0029] 請一併參閱圖6，以第一道光罩圖案對準該第一光阻層 231上方，以紫外光線平行照射該第一光阻層231，再對 該第一光阻層231進行顯影，從而可形成一第一光阻圖案 ，以該第一光阻圖案為遮罩對該第一閘極絕緣層20 2進行 蝕刻使對應處之該絕緣基底201暴露，並移除剩餘之第一 光阻層231，形成預定之閘極槽210及公共線槽260。 [0030] (2)形成閘極金屬層； [0031] 請一併參閱圖7，於剩餘之該第一閘極絕緣層202、該閘 極槽210上沉積一閘極金屬層205。其材料可為鋁（A1)系 096130513 表單編號A0101 第7頁/共32頁 1003082443-0 1355083 100年03月11日核正替換頁 [0032] [0033] [0034] [0035] [0036] [0037] [0038] 金屬、翻（Mo)、絡（Cr)、組（Ta)、或銅（Cu)。該閘極 金屬層205之厚度與該第一閘極絕緣層2〇2之厚度相同。 (3)形成閘極圖案； 〇月併參閱圖8 ’以化學機械研磨（chemi ca 1 mechanical polishing， CMP) 除去位於該閘極槽 21〇 外之閘極 金屬層205，形成具有預定圖案之閘極213及公共線226 二、第二道光罩製程 (4) 形成第二閘極絕緣層、半導體層及第一鈍化層； 請參閱圖9，用化學氣相沉積法於具有該第一閘極絕緣層 202、該閘極213及該公共線226之絕緣基底201上形成一 氮化矽（SiNx)構成之第二閘極絕緣層206 ;再用化學氣 相沉積方法在該第二閘極絕緣層2 〇 6上形成一半導體層 207 ;於該半導體層207上沉積一第—鈍化層208 ;於該 第一純化層208上沉積一1第二光阻層232。 請一併參閱圖10，以第二道光罩圖案對準該第二光阻層 2 3 2上方，以紫外光線平行照射該第二光阻層2 3 2，再對 該第·一光阻層232進行顯影，從而可於該第二光阻層232 上形成一第二光阻圖案。以該第二光阻圖案為遮罩，對 該第一純化層208進行姓刻使得部分半導體層2〇7暴露， 移除剩餘之第二光阻層232，形成源極槽220、汲極槽 230及儲存電容電極槽270。 (5) 形成源/汲極金屬層； 096130513 表單編號A0101 第8頁/共32頁 1003082443-0 1355083 _ 100年03月11日按正替换頁 [0039] 於剩餘之第一鈍化層208及暴露之半導體層207上沉積一 源/及極金屬層（圖未示）。其中該源/汲極金屬層材料 可為銘合金、|g(Al)、鉬（Mo)、姐（Ta)、或钥鎢（MoW) 合金》 [0040] ( 6 )形成源/淡極圖案； [0041] 請一併參閱圖11，對該源/汲極金屬層以化學機械研磨除 去位於剩餘之第一鈍化層208上之源/汲極金屬層，從而 形成具有預定圖案之源極214、汲極215及儲存電容電極 227 〇 [0042] 三、第三道光罩製程 [0043] (7)形成第二鈍化層； [0044] 請一併參閱圖12，於該剩餘之第一鈍化層208、該源/汲 極214、215及該儲存電容電極227上沉積一第二鈍化層 209。 [0045] (8)形成像素電極槽並暴露該汲極； [0046] 請一併參閱圖13，在該第二鈍化層209上沉積一第三光阻 層233，以第三道光罩對準該第三光阻層233上方，以紫 外光線平行照射該第三光阻層，再對該第三光阻層進行 顯影，從而形成一第三光阻圖案。如圖13所示，該第三 光阻圖案具有一與該汲極215對應之第一凹槽240、一與 該儲存電容電極227對應之第二凹槽242及位於該二凹槽 240、242之間之一像素電極槽250 »該像素電極槽250暴 露該第二鈍化層209。 096130513 表單編號Α0101 第9頁/共32頁 1003082443-0 1355083 100 年 03 月 [0047] 請一併參閱圖14，以該第三光阻圖案為遮罩，蝕刻該第 二純化層209、第一鈍化層208、半導體層207、第二間 極絕緣層206，移除該像素電極槽25〇處之該第二鈍化層 209、第一鈍化層2〇8、半導體層2〇7、第二閘極絕緣層 206，暴露該像素電極槽250所對應之第一閘極絕緣層 202。同時’該汲極215及該儲存電容電極227上對應之 第二鈍化層209亦被去除，該汲極2!5及該儲存電容電極 227暴露。移除剩餘之該第三光阻層233。 [0048] 四、第四道光罩製程 [0049] (9)形成導體層； [0050]請一併參閱圖15，於該第二鈍化層209、該汲極215、該 暴露之第一閘極絕緣層2〇2及該儲存電容電極227上沉積 一透明之導體層290，該導體層290為銦錫氧化物或銦鋅 氧化物。 [0051] (10)形成像素電極圖案； [0052] 於§亥導體層290上沉積一第四光阻層（圖未示）。以第四 道光罩圖案對準該第四光阻層上方，以紫外光線平行照 射該第四光阻層，再對該第四光阻層進行顯影，從而可 行成一第四光阻圖案。以該第四光阻層圖案為遮罩對該 導體層290進行姓刻，從而得到具有預定圖案之像素電極 216 « [0053] 096130513 相較於先前技術’該製造方法利用化學機械研磨配合光 罩製程’實現用四道光罩製程形成該薄膜電晶體基板2〇〇 ’無需一道光罩製程去單獨形成具有預定®案之鈍化層 表單編號A0101 » ln 1355083 _ 100年03月11日梭正替換頁 ，從而比先前技術節省一道光罩製程，光罩次數減少， 製程簡化’可有效降低成本。 [0054] 本發明溥膜電晶體基板製造方法之第一道光罩過程中， 亦可不必沉積該第一閘極絕緣層，而直接對絕緣基板進 行光罩、顯影及蝕刻以形成一閘極槽，對於後續之製程 並無影響° [0055] 综上所述，本發明確已符合發明之要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施方式， 本發明之範圍並不以上述實施方式為限，舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化’ 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0056] 圖1係一種先前技術薄膜電晶體基板之結構示意圖。 [0057] 圖2係圊1所示薄膜電晶體基板製造方法之流程圖。 [0058] 圖3係採用本發明薄膜電晶體基板製造方法所製选之薄膜 電晶體基板結構示意圖。 [0059] 圖4係本發明之薄膜電晶體基板製造方法之流程圖。 [0060] 圖5~15係圖4所示製造方法之各步驟之圖示說明。 【主要元件符號說明】 [0061] 薄膜電晶體基板：200 [0062] 第二鈍化層：209 [0063] 絕緣基底：201 096130513 表單編號A0101 第丨1頁/共32頁 1003082443-0 1355083 100年03月11日核正脊换頁 [0064] 閘極：213 [0065] 第一閘極絕緣層：202 [0066] 源極：214 [0067] 第二閘極絕緣層：206 [0068] 汲極：215 [0069] 半導體層：207 [0070] 像素電極：216 [0071] 第一鈍化層：208 [0072] 導體層：290 1003082443-0 096130513 表單編號A0101 第12頁/共32頁A first photoresist layer 231 is deposited on the X edge layer 202. [0029] Please refer to FIG. 6 together, and align the first photoresist layer 231 with the first mask pattern, and irradiate the first photoresist layer 231 with ultraviolet light, and then the first photoresist layer 231. Developing, thereby forming a first photoresist pattern, etching the first gate insulating layer 20 2 with the first photoresist pattern as a mask to expose the insulating substrate 201 at the corresponding position, and removing the remaining The first photoresist layer 231 forms a predetermined gate trench 210 and a common trench 260. [0030] (2) Forming a gate metal layer; [0031] Referring to FIG. 7, a gate metal layer 205 is deposited on the remaining first gate insulating layer 202 and the gate trench 210. The material may be aluminum (A1) system 096130513 Form No. A0101 Page 7 / Total 32 Page 1003082443-0 1355083 100 March 2011 Nuclear Replacement Page [0032] [0034] [0036] [0036] 0037] [0038] Metal, turn (Mo), complex (Cr), group (Ta), or copper (Cu). The thickness of the gate metal layer 205 is the same as the thickness of the first gate insulating layer 2〇2. (3) forming a gate pattern; 〇月 and referring to FIG. 8 'mechanical mechanical polishing (CMP) to remove the gate metal layer 205 located outside the gate trench 21 to form a gate having a predetermined pattern Pole 213 and common line 226 2. Second mask process (4) forming a second gate insulating layer, a semiconductor layer and a first passivation layer; see FIG. 9, using chemical vapor deposition to have the first gate A second gate insulating layer 206 made of tantalum nitride (SiNx) is formed on the insulating layer 202, the gate electrode 213 and the insulating substrate 201 of the common line 226; and the second gate insulating layer is further insulated by a chemical vapor deposition method. A semiconductor layer 207 is formed on the layer 〇6; a first passivation layer 208 is deposited on the semiconductor layer 207; and a second photoresist layer 232 is deposited on the first purification layer 208. Please refer to FIG. 10 together, and align the second photoresist layer 2 3 2 with a second mask pattern, and irradiate the second photoresist layer 2 3 2 in parallel with ultraviolet light, and then the first photoresist layer. 232 is developed to form a second photoresist pattern on the second photoresist layer 232. Taking the second photoresist pattern as a mask, the first purification layer 208 is surnamed to expose a portion of the semiconductor layer 2〇7, and the remaining second photoresist layer 232 is removed to form a source trench 220 and a drain trench. 230 and storage capacitor electrode slot 270. (5) Forming the source/drain metal layer; 096130513 Form No. A0101 Page 8 of 32 1003082443-0 1355083 _ March 31, 2011 Pressing the replacement page [0039] on the remaining first passivation layer 208 and exposed A source/and a metal layer (not shown) is deposited over the semiconductor layer 207. Wherein the source/dual metal layer material may be an alloy, a |g(Al), a molybdenum (Mo), a sister (Ta), or a tungsten (MoW) alloy. [0040] (6) forming a source/light pole pattern [0041] Referring to FIG. 11, the source/drain metal layer is chemically mechanically polished to remove the source/drain metal layer on the remaining first passivation layer 208, thereby forming a source 214 having a predetermined pattern. , drain 215 and storage capacitor electrode 227 〇 [0042] Third, the third mask process [0043] (7) forming a second passivation layer; [0044] Please also refer to Figure 12, the remaining first passivation layer 208. A second passivation layer 209 is deposited on the source/drain electrodes 214 and 215 and the storage capacitor electrode 227. [0045] (8) forming a pixel electrode trench and exposing the drain; [0046] Referring to FIG. 13, a third photoresist layer 233 is deposited on the second passivation layer 209, and the third mask is aligned. Above the third photoresist layer 233, the third photoresist layer is irradiated in parallel with ultraviolet light, and the third photoresist layer is developed to form a third photoresist pattern. As shown in FIG. 13 , the third photoresist pattern has a first recess 240 corresponding to the drain 215 , a second recess 242 corresponding to the storage capacitor electrode 227 , and the second recess 240 , 242 . One of the pixel electrode slots 250 » the pixel electrode trench 250 exposes the second passivation layer 209. 096130513 Form No. 101 0101 Page 9 / Total 32 Page 1003082443-0 1355083 100 March [0047] Please refer to FIG. 14 together with the third photoresist pattern as a mask to etch the second purification layer 209, first The passivation layer 208, the semiconductor layer 207, and the second interpole insulating layer 206 remove the second passivation layer 209, the first passivation layer 2〇8, the semiconductor layer 2〇7, and the second gate at the pixel electrode trench 25〇 The pole insulating layer 206 exposes the first gate insulating layer 202 corresponding to the pixel electrode slot 250. At the same time, the drain 215 and the corresponding second passivation layer 209 on the storage capacitor electrode 227 are also removed, and the drain 2! 5 and the storage capacitor electrode 227 are exposed. The remaining third photoresist layer 233 is removed. [0048] Fourth, the fourth mask process [0049] (9) forming a conductor layer; [0050] Please refer to Figure 15, the second passivation layer 209, the drain 215, the exposed first gate A transparent conductor layer 290 is deposited on the insulating layer 2〇2 and the storage capacitor electrode 227. The conductor layer 290 is indium tin oxide or indium zinc oxide. (10) forming a pixel electrode pattern; [0052] depositing a fourth photoresist layer (not shown) on the conductive layer 290. The fourth photoresist layer is aligned with the fourth photoresist layer to illuminate the fourth photoresist layer in parallel with the ultraviolet light, and then the fourth photoresist layer is developed to form a fourth photoresist pattern. The conductor layer 290 is firstly engraved with the fourth photoresist layer pattern as a mask, thereby obtaining a pixel electrode 216 having a predetermined pattern. [0053] 096130513 Compared with the prior art, the manufacturing method utilizes chemical mechanical polishing with a mask. The process 'implements the four-mask process to form the thin-film transistor substrate 2' without a mask process to form a passivation layer with a predetermined pattern. Form No. A0101 » ln 1355083 _ 100 March 2011 Shuttle replacement page Therefore, the reticle process can be saved compared with the prior art, the number of masks is reduced, and the process simplification can effectively reduce the cost. [0054] In the first mask process of the method for manufacturing a ruthenium film transistor substrate, the first gate insulating layer may not be deposited, and the insulating substrate may be directly masked, developed, and etched to form a gate. The slot has no effect on the subsequent process. [0055] In summary, the present invention has indeed met the requirements of the invention, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0056] FIG. 1 is a schematic view showing the structure of a prior art thin film transistor substrate. 2 is a flow chart showing a method of manufacturing a thin film transistor substrate shown in FIG. 3 is a schematic structural view of a thin film transistor substrate prepared by using the method for manufacturing a thin film transistor substrate of the present invention. 4 is a flow chart showing a method of manufacturing a thin film transistor substrate of the present invention. 5 to 15 are graphical illustrations of the steps of the manufacturing method shown in FIG. 4. [Major component symbol description] [0061] Thin film transistor substrate: 200 [0062] Second passivation layer: 209 [0063] Insulation substrate: 201 096130513 Form number A0101 Page 1 of 32 1003082443-0 1355083 100 years 03 November 11th Orthogonal Ridge Replacement [0064] Gate: 213 [0065] First Gate Insulation: 202 [0066] Source: 214 [0067] Second Gate Insulation: 206 [0068] Bungee: 213 [0069] Semiconductor Layer: 207 [0070] Pixel Electrode: 216 [0071] First Passivation Layer: 208 [0072] Conductor Layer: 290 1003082443-0 096130513 Form No. A0101 Page 12 of 32