200910597 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體基板製造方法。 【先前技術】 目前，液晶顯示器逐漸取代用於計算機之傳統陰極射 線管（Cathode Ray Tube，CRT)顯示器，而且，由於液晶顧 示器具輕、薄、小等特點，使其非常適合應用於桌上型電 腦、膝上型電腦、個人數字助理（PersGnal Digiui PDA)、便攜式電話、電視以種辦公自動化與視聽設備 中。液晶面板是其主要元件，其—般包括一薄膜電晶體基 板、-彩色濾光片基板及夾於該薄膜電晶體基板與該彩色 濾光片基板之間之液晶層。 =參閱圖1，係一種先前技術薄膜電晶體基板1〇〇之 結構示意圖。該薄膜電晶體基板⑽包括—基底皿、一 ;基底101上之閘極1〇2、一位於該間極1〇2及該基底 =1上之閘極絕緣層103、一位於該閘極絕緣層上之半 ^ θ 104 位於該半導體層104及該閘極絕緣層1〇3 上之源極105與祕106、一位於該閘極絕緣層1〇3、該源 極105及5亥/及極106上之純化層1〇7以及一位於該純化層 107上之像素電極108。 泣。請參照圖2,係該薄膜電晶體基板1〇〇之製造方法之 *程圖。該製造方法採用五道光罩製程，包括以下步驟： 一、第一道光罩製程 (1)形成閘極金屬層：提供一絕緣基底101，在該絕 200910597 彖基底101上依序形成—間極金 — .(2)形成間極··以第一道井置夕I杏 先F且層’· ‘進行曝光顯影，從而形成-第-光好圖=該第—光㈣ =案為遮罩對該間極金屬層進:、進 極102，移除第一光阻層。 運而形成一閑 —、第一道光罩製程 (3) 形成閘極絕緣層、非曰 有該間極之絕緣基底上；/曰“夕及摻雜非晶石夕層：於具 多雜非日日矽層及一第二光阻層； ^日日矽 (4) 形成半導體層： 、、 阻層進行曝光顯影，從而〗之圖案對該第二光 二光阻層圖案為遮阻層圖案；以該第 蝕刻，進而形成呈：預非3曰矽層及該非晶矽層進行 二光阻層。、有—預定圖案之半導體層⑽，移除第 三、 第三道光罩製程 (5)形成源/汲極金屬芦· 上形成及該半導體層圖案 ⑹形成源/没極金屬-.二， 该第三光阻層進行曝光_旦31.以弟二以罩之圖案對 案;以該第三光阻層圖幸為：罩：：：成一第三光阻層圖 刻，進而形成-源極源/汲極金屬層進純 層進行餘刻形成-溝押没極1〇6，並對換雜非晶石夕 四〜 溝槽’移除第三光阻層。 四、 弟四道光罩製程 、源極及没極的基底 (7)形成鈍化層：於具有該閘極 200910597 上沉積一鈍化層及一第四光阻層； (8)形成鈍化層圖案：以第四道来置夕θ '光阻層進行曝光顯影，從而形 ：=該第四 第四光阻層圖案為遮罩對該鈍化層進行= 一純化層107之圖案，移除第四光阻層。進而疋義出 五、第五道光罩製程 (9)形成一導體層：於具有該閘、^ ^ ^ 化層圖案的基底上形成二/及極及純 ⑽形成像素電極：以第五道Μ之圖^ 阻=進行曝光顯影，從而形成—第五光阻層圖案；/以該第 導俨层-^ ^ ^ 守菔層進仃蝕刻，進而圖案化該 層’形成像素電極⑽，移除該第五光阻層。 惟：該方法需要較多光罩製程，而; ，雜且成本較高，從而使得製造成本較高。另外，： 次光罩製程之微影生j過程巾，# 、 壞會直接影響整個產品=^的Γ曝光之好 加降低產品良率之^良辜’因此，光罩製程較多易增 【發明内容】 有‘於此#供—種製程簡單且成本低之薄膜電晶體 基板製造方法實為必要。 -種薄膜電晶體基板製造方法，其步驟包括提供—絕 =基底m緣基底上沉積―第—閘極絕緣層；於—第 遏光罩製私形成-閘極槽；於剩餘之第—間極絕緣層上 及及間極槽内沉積—閘極金屬層；對該問極金屬層進行化 200910597 學機械研磨形成-閘極；於剩餘之第一問極絕緣層及該問 極上依序沉積—第二閉極絕緣層、—半導體層及-第—鈍 ' k於第一道光罩製程形成—源極槽及一没極槽；於 剩餘之第一鈍化層上、該源極槽及一及極槽内沉積-源/ 汲極金屬層；對該源/汲極金屬層進行化學機械研磨形成一 ，極及一汲極；於該第一鈍化層及該源極、汲極上沉積一 第鈍化層，於帛二道光罩製程形成—像素電極槽並使 得汲極暴露出來；在剩餘之第二鈍化層上、暴露之汲極上、 像素電極槽内沉積一導體層；於一第四道光罩製程形成一 像素電極。 相較於先前技術，該製造方法利用化學機械研磨配合 光罩製程’實現用四道光罩製程形成薄膜電晶體基板，無 需用一，光罩製程去單獨形成具有預定圖案之鈍化層，從 而比先前技術節省一道光罩製程，光罩次數減少，製程簡 化，可有效降低成本。 【實施方式】 請參閱圖3,係本發明薄膜電晶體基板之一較佳實施方 式所揭示之結構示意圖。該薄膜電晶體基板2〇〇包括一絕 ，基底201、設置於該絕緣基底2〇1上之—閘極213及一 第一，極絕緣層202、依序設置於該第一閘極絕緣層2〇2 上之第二閘極絕緣層206及半導體層207、設置於該半導 體層207上之一第一鈍化層2〇8、一源極214及一汲極 215、設置於該半導體層2〇7及源極214上之第二鈍化層 209及一設置於該汲極215及第—閘極絕緣層2〇2上之像 200910597 素電極216。 、、請參閱圖4,係圖3所示薄膜電晶體基板細製造方 =之-較佳實施方式之流程圖。該薄膜電晶體基板之 衣造方法包括四道光罩製程，其具體步驟如下： 一、第一道光罩製程 (1)形成第一閘極絕緣層； 請參閱圖5，提供-絕緣基底201，該絕緣基底201可 以為玻璃、石英或者_絕緣材質；用化學氣相沉積法 cal vapor deposition，CVD)，反應氣體為矽烷（义叫) 二氣，（NH3)，於該絕緣基底2〇!上形成一氮化矽（SiNx)構 成之^ -閑極絕緣層2〇2;在該第—閘極絕緣層观上沉 積一第一光阻層231。 請一併參閱圖6,以第一道光罩圖案對準該第一光阻 运231上方，以紫外光線平行照射該第—光阻層，再 ^該第-光阻層231進行顯影，從而可形成—第曰―光阻圖 Γ，以該第一光阻圖案為遮罩對該第—閘極絕緣層202進 :飿刻使對應處之該絕緣基底謝暴露，並移除剩餘之第 光阻層231 ’形成預定之閘極槽21〇及公共線槽26〇。 〈2)形成閘極金屬層； 請—併參閱目7,於剩餘之該第一間極絕㈣2〇2、該 :極槽210上沉積-閘極金屬層2〇5。其材料可為紹⑷） ^屬、、鉻⑼、纽㈣、或銅（Cu)。該間極金屬 运205之厚度與該第一閘極絕緣層2〇2之厚度相同。 (3)形成閘極圖案； 200910597 〇月併參閱圖8 ’以化學機械研磨（chemical .mechanics polishing，CMp)除去位於該閘極槽2i〇外之閘 _極金屬層205’形成具有預定圖案之開極213及公共線， 二、第二道光罩製程 (=形成第二閘極絕緣層、半導體層及第一鈍化層； 。月，閱圖9，用化學氣相沉積法於具有該第一閘極絕 緣層搬、該問極213及該公共線加之絕緣基底2〇1上 形成-鼠化石夕（SiNx)構成之第二閘極絕緣層裏，·再用化 學氣相沉積方法在該第二閘極絕緣層2〇6 層207，_於該半導體層2〇7 一 I牛¥體 货干命篮層207上/几積一第一鈍化層208;於該 弟一鈍化層208上沉積一第二光阻層232。 參閱圖H)，以第二道光罩圖案對準該第二光阻 trrr以紫外光線平行照射該第二光阻層说，再 子^-士阻層232進行顯影，從而可於該第二光阻層说 上形成一弟二光阻圖案.。以該第二光阻圖宰為遮 =1Τ°ΓΓ刻使得部分半導體層207暴露，： 2-W230 (5) 形成源/汲極金屬層； -鈍化層細及暴露之半導體層2G?上沉積 =録屬層（圖未示）。其中該源㈣金 可 =〇、峰。[组⑼、或銷鶴㈣^ (6) 形成源/汲極圖案； ^ 請一併參閱圖U’對該源/汲極金屬層以化學機械研 11 200910597 磨除去位於剩餘之第一鈍化層208上之源/汲極金屬層，從 .而形成具有預定圖案之源極214、汲極215及儲存電容電 ，極 227 。 三、第三道光罩製程 (7) 形成第二鈍化層； 請一併參閱圖12，於該剩餘之第一鈍化層208、該源/ 汲極214、215及該儲存電容電極227上沉積一第二鈍化層 209 ° (8) 形成像素電極槽並暴露該汲極； 請一併參閱圖13，在該第二鈍化層209上沉積一第三 光阻層233，以第三道光罩對準該第三光阻層233上方， 以紫外光線平行照射該第三光阻層，再對該第三光阻層進 行顯影，從而形成一第三光阻圖案。如圖13所示，該第三 光阻圖案具有一與該汲極215對應之第一凹槽240、一與 該儲存電容電極227對應之第二凹槽242及位於該二凹槽 240、242之間之一像素電極槽250。該像素電極槽250暴 露該第二鈍化層209。 請一併參閱圖14，以該第三光阻圖案為遮罩，蝕刻該 第二鈍化層209、第一鈍化層208、半導體層207、第二閘 極絕緣層206，移除該像素電極槽250處之該第二鈍化層 209、第一鈍化層208、半導體層207、第二閘極絕緣層206, 暴露該像素電極槽250所對應之第一閘極絕緣層202。同 時，該汲極215及該儲存電容電極227上對應之第二鈍化 層209亦被去除，該汲極215及該儲存電容電極227暴露。 12 200910597 移除剩餘之該第三光阻層233 四、第四道光罩製程 (9)形成導體層； 上曰响併芩閱圖I5’於該第二鈍化層209、該汲極215、 該暴露之第一閘極絕緣房 、 琢增2U2及該儲存電容電極227上沉 積透明之導體層290，該導〇οη达* σ ¥體a 290為銦錫氧化物或銦 鋅乳化物。 (1〇)形成像素電極圖案； 導體層290上沉積一第四光阻層 四逞光㈣案料㈣四絲層上方，以紫外): 射該第四光阻層’再對該第四光阻層進行顯影，從而可: 芦290進/ S ° ^第四光阻層11案為遮罩對該導I 二=Γ而得到具有預定圖案之像素電極加 九車衣fe ’貝現用四道光罩制 200,益需一道#1制4 +衣私形成该溥膜電晶體基4 声，從而比务/ 單獨形成具有預定圖案之心 :技術節省一道光罩製程，光 衣耘間化，可有效降低成本。 Ί 本發明薄膜電晶體基板製造方 中，亦可不必沉積該第一間極絕緣/之二一道光罩過老 進行光罩、顯影及蝕刻 ^ 接對絕緣基泰 並無影響。 化成閉極槽’對於後續之製卷 專二所rt?明確已符合發明之要件，爰依法提出 申η以上所述者僅為本發明之㈣實施=出 13 200910597 本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技 .藝之人士援依本發明之精神所作之等效修飾或變化，皆應 .涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術薄膜電晶體基板之結構示意圖。 圖2係圖1所示薄膜電晶體基板製造方法之流程圖。 圖3係採用本發明薄膜電晶體基板製造方法所製造之薄膜 電晶體基板結構不意圖。 圖4係本發明之薄膜電晶體基板製造方法之流程圖。 圖5〜15係圖4所示製造方法之各步驟之圖示說明。 【主要元件符號說明】 薄膜電晶體基板 200 第二鈍化層 209 絕緣基底 201 閘極. 213 第一閘極絕緣層 202 源極 214 第二閘極絕緣層 206 汲極 215 半導:體層 207 像素電極 216 第一鈍化層 208 導體層 290 14200910597 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a thin film transistor substrate. [Prior Art] At present, liquid crystal displays are gradually replacing the traditional cathode ray tube (CRT) display for computers, and because of the light, thin and small characteristics of the liquid crystal display device, it is very suitable for application on the table. Computers, laptops, personal digital assistants (PersGnal Digiui PDAs), portable phones, televisions for office automation and audiovisual equipment. The liquid crystal panel is a main component thereof, and generally includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Referring to Figure 1, there is shown a schematic view of a prior art thin film transistor substrate. The thin film transistor substrate (10) includes a substrate, a gate 1, a gate on the substrate 101, a gate insulating layer 103 on the interpole 1 and 2, and a gate insulating layer. The half of the layer θ 104 is located on the semiconductor layer 104 and the gate insulating layer 1 〇 3 of the source 105 and the secret 106, one of the gate insulating layer 1 〇 3, the source 105 and 5 A purification layer 1?7 on the electrode 106 and a pixel electrode 108 on the purification layer 107. weep. Referring to Fig. 2, there is shown a process diagram of the method for manufacturing the thin film transistor substrate. The manufacturing method adopts a five-mask process, including the following steps: 1. The first mask process (1) forms a gate metal layer: an insulating substrate 101 is provided, which is sequentially formed on the substrate 10 of the 200910597 substrate. Gold—(2) Forming the interpole ············································ The first metal layer is removed from the interpolar metal layer, and the first photoresist layer is removed. To form a leisure--the first mask process (3) to form a gate insulating layer, on the insulating substrate not having the interpole; /曰" and doped amorphous stone layer: a non-daily layer and a second photoresist layer; ^ day and day (4) forming a semiconductor layer:, and a resist layer is exposed and developed, so that the pattern of the second photodiode layer pattern is a mask layer pattern And the first etching is performed to form a pre-non-three-layer layer and the amorphous germanium layer to perform a two-resistive layer. The semiconductor layer (10) having a predetermined pattern is removed, and the third and third mask processes are removed (5) Forming a source/dip metal on the reed and forming the semiconductor layer pattern (6) to form a source/dipole metal-.2, the third photoresist layer is exposed to _31. The second is in the form of a hood; The third photoresist layer is fortunately: the cover::: is formed into a third photoresist layer, and then the source/dot metal layer is formed into the pure layer for the formation of the residual-dip immersion 〇6, and For the replacement of amorphous austenitic four ~ trench 'removal of the third photoresist layer. Fourth, the four reticle process, the source and the immersed substrate (7) form a passivation layer: A passivation layer and a fourth photoresist layer are deposited on the gate 200910597; (8) a passivation layer pattern is formed: the fourth layer is used to perform exposure and development, thereby forming: = the fourth The four photoresist layer pattern is a mask for the passivation layer = a pattern of the purification layer 107, and the fourth photoresist layer is removed. Further, the fifth mask process (9) forms a conductor layer: Forming a second/pole and a pure (10) on the substrate of the gate pattern, forming a pixel electrode: performing a exposure and development with a fifth turn; forming a fifth photoresist layer pattern; The first conductive layer-^^^ is etched and then patterned to form the pixel electrode (10) to remove the fifth photoresist layer. However, the method requires more mask processing, and; Miscellaneous and high cost, which makes the manufacturing cost higher. In addition, the lithography process of the secondary mask process, #,, bad will directly affect the entire product = ^ Γ exposure is good and reduce the product yield ^ Liangzhu 'Therefore, the mask process is more likely to increase. [Inventive content] There is a 'this # supply--process is simple and The invention relates to a method for manufacturing a thin film transistor substrate. A method for manufacturing a thin film transistor substrate, the method comprising the steps of: providing a deposition of a first-gate insulating layer on a substrate of a substrate m; Privately formed - gate trench; deposited on the remaining first-interpole insulating layer and in the inter-pole trench - gate metal layer; the problem of the polar metal layer is formed in 200910597 mechanical grinding to form - gate; The first interposer insulating layer and the interposer are sequentially deposited—the second closed-pole insulating layer, the semiconductor layer, and the first-blunt' k are formed in the first mask process—the source trench and the immersion trench; Depositing a source/drain metal layer on the remaining first passivation layer, the source trench and the one and the pole trenches; performing chemical mechanical polishing on the source/drain metal layer to form a pole and a drain; Depositing a passivation layer on the first passivation layer and the source and the drain, forming a pixel electrode trench in the second photomask process and exposing the drain; on the remaining second passivation layer, the exposed drain, and the pixel Depositing a conductor layer in the electrode slot; in a fourth mask Forming a pixel electrode. Compared with the prior art, the manufacturing method utilizes chemical mechanical polishing in conjunction with the mask process to realize the formation of a thin film transistor substrate by a four-mask process, without using a mask process to separately form a passivation layer having a predetermined pattern, thereby The technology saves a mask process, the number of masks is reduced, and the process is simplified, which can effectively reduce costs. [Embodiment] Please refer to Fig. 3, which is a schematic structural view of a preferred embodiment of a thin film transistor substrate of the present invention. The thin film transistor substrate 2 includes a substrate 201, a gate 213 disposed on the insulating substrate 211, and a first, very insulating layer 202, sequentially disposed on the first gate insulating layer. a second gate insulating layer 206 and a semiconductor layer 207 on the second layer, a first passivation layer 2〇8, a source 214 and a drain 215 disposed on the semiconductor layer 207, and disposed on the semiconductor layer 2 A second passivation layer 209 on the 〇7 and the source 214 and an image of the 200910597 element electrode 216 disposed on the drain 215 and the first gate insulating layer 2〇2. Please refer to FIG. 4, which is a flow chart of the thin film transistor substrate shown in FIG. The method for fabricating the thin film transistor substrate comprises four mask processes, and the specific steps are as follows: 1. The first mask process (1) forms a first gate insulating layer; Referring to FIG. 5, an insulating substrate 201 is provided. The insulating substrate 201 may be glass, quartz or _insulating material; by chemical vapor deposition (cal vapor deposition, CVD), the reaction gas is decane (expressed) two gas, (NH3), on the insulating substrate 2 〇! Forming a tantalum nitride (SiNx) layer - a dummy insulating layer 2 〇 2; depositing a first photoresist layer 231 on the first gate insulating layer. Referring to FIG. 6 together, the first reticle pattern is aligned above the first light blocking 231, and the first photoresist layer is irradiated with ultraviolet light in parallel, and then the first photoresist layer 231 is developed. Forming a -th - photoresist pattern, the first photoresist pattern is used as a mask to the first gate insulating layer 202: engraving to expose the insulating substrate at the corresponding portion, and removing the remaining portion The photoresist layer 231' forms a predetermined gate trench 21 and a common trench 26. <2) Forming a gate metal layer; - and refer to item 7, in the remaining first electrode (4) 2, 2, the gate trench is deposited with a gate metal layer 2〇5. The material may be Shao (4)), genus, chromium (9), neo (four), or copper (Cu). The thickness of the interpole metal 205 is the same as the thickness of the first gate insulating layer 2〇2. (3) forming a gate pattern; 200910597 并月 and referring to FIG. 8 'Removing the gate _ pole metal layer 205' located outside the gate trench 2i by chemical mechanical polishing (CMp) to form a predetermined pattern Opening electrode 213 and common line, second, second mask process (= forming a second gate insulating layer, a semiconductor layer and a first passivation layer; month, see Figure 9, using chemical vapor deposition to have the first The gate insulating layer is moved, the asking electrode 213 and the common line are added to the insulating substrate 2〇1 to form a second gate insulating layer composed of a nucleus (SiNx), and the chemical vapor deposition method is used again. The second gate insulating layer 2 〇 6 layers 207, _ on the semiconductor layer 2 〇 7 I ¥ 体 体 命 命 207 207 207 207 几 几 几 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 沉积 沉积 沉积 沉积 沉积a second photoresist layer 232. Referring to FIG. H), the second photoresist pattern trrr is aligned with the second mask pattern to illuminate the second photoresist layer in parallel with the ultraviolet light, and then developed by the photoresist layer 232. So that a second photoresist pattern can be formed on the second photoresist layer. The second photoresist pattern is masked as a mask to expose a portion of the semiconductor layer 207, wherein: 2-W230 (5) forms a source/drain metal layer; - a passivation layer is thin and the exposed semiconductor layer 2G is deposited. = Recording layer (not shown). Among them, the source (four) gold can be 〇, peak. [Group (9), or Pin Crane (4)^ (6) Form the source/drain pattern; ^ Please refer to Figure U' for the source/dip metal layer by chemical mechanical grinding 11 200910597 to remove the remaining first passivation layer The source/drain metal layer on 208 forms a source 214, a drain 215, and a storage capacitor, 227, having a predetermined pattern. Third, the third mask process (7) forms a second passivation layer; please refer to FIG. 12 together, depositing a remaining first passivation layer 208, the source/drain electrodes 214, 215 and the storage capacitor electrode 227 The second passivation layer 209 ° (8) forms a pixel electrode trench and exposes the drain; please refer to FIG. 13 together, depositing a third photoresist layer 233 on the second passivation layer 209, and aligning with the third mask Above the third photoresist layer 233, the third photoresist layer is irradiated in parallel with ultraviolet light, and the third photoresist layer is developed to form a third photoresist pattern. As shown in FIG. 13 , the third photoresist pattern has a first recess 240 corresponding to the drain 215 , a second recess 242 corresponding to the storage capacitor electrode 227 , and the second recess 240 , 242 . One pixel electrode slot 250 is in between. The pixel electrode trench 250 exposes the second passivation layer 209. Referring to FIG. 14 , the second photoresist pattern is used as a mask, and the second passivation layer 209 , the first passivation layer 208 , the semiconductor layer 207 , and the second gate insulating layer 206 are etched to remove the pixel electrode slot. The second passivation layer 209, the first passivation layer 208, the semiconductor layer 207, and the second gate insulating layer 206 at 250 are exposed to the first gate insulating layer 202 corresponding to the pixel electrode trench 250. At the same time, the drain 215 and the corresponding second passivation layer 209 on the storage capacitor electrode 227 are also removed, and the drain 215 and the storage capacitor electrode 227 are exposed. 12 200910597 Removing the remaining third photoresist layer 233. The fourth mask process (9) forms a conductor layer; the upper ring is slammed and the second passivation layer 209, the drain 215, A transparent conductive layer 290 is deposited on the exposed first gate insulating chamber, the enthalpy 2U2, and the storage capacitor electrode 227, and the conductive layer 290 is an indium tin oxide or an indium zinc emulsion. Forming a pixel electrode pattern on the conductor layer 290; depositing a fourth photoresist layer on the conductor layer 290 (four) material (four) above the four wire layer, in ultraviolet light:: shooting the fourth photoresist layer 'and then the fourth light The resist layer is developed, so that: the reed 290 enters / S ° ^ the fourth photoresist layer 11 is masked to the guide I 2 = Γ to obtain a pixel electrode with a predetermined pattern plus nine clothing fe 'bei four lights Cover 200, it is necessary to form a 溥 film transistor based on a #1 system 4 + clothing, so as to form a predetermined pattern of hearts / technology alone: technology saves a mask process, light clothing, can be Effectively reduce costs. Ί In the manufacture of the thin film transistor substrate of the present invention, it is not necessary to deposit the first interlayer insulating/two reticle over the old to perform photomasking, development and etching, which has no effect on the insulating base. The invention is not limited to the scope of the invention. The equivalents of the embodiments of the present invention are intended to be equivalent to the modifications and variations of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art thin film transistor substrate. 2 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in FIG. 1. Fig. 3 is a schematic view showing the structure of a thin film transistor substrate produced by the method for producing a thin film transistor substrate of the present invention. 4 is a flow chart showing a method of manufacturing a thin film transistor substrate of the present invention. 5 to 15 are illustrations of the steps of the manufacturing method shown in Fig. 4. [Major component symbol description] Thin film transistor substrate 200 Second passivation layer 209 Insulation substrate 201 Gate. 213 First gate insulating layer 202 Source electrode 214 Second gate insulating layer 206 Dip pole 215 Semi-conducting: Body layer 207 Pixel electrode 216 first passivation layer 208 conductor layer 290 14