CN105529007A - Drive circuit of ITO electrode in LCOS display structure - Google Patents
Drive circuit of ITO electrode in LCOS display structure Download PDFInfo
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- CN105529007A CN105529007A CN201610067077.XA CN201610067077A CN105529007A CN 105529007 A CN105529007 A CN 105529007A CN 201610067077 A CN201610067077 A CN 201610067077A CN 105529007 A CN105529007 A CN 105529007A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention discloses a drive circuit of an ITO electrode in a LCOS display structure, which is integrated in an LCOS display structure and generates drive voltage of the ITO electrode according to working voltage of the LCOS display structure. The invention enables the drive circuit of the ITO electrode and the LCOS display structure to use the same power supply so as to reduce the power supply voltage in order to adapt to the advanced technology, reduce the size of the chip and save the power consumption. Besides, the drive circuit can also guarantee the synchronization of the voltage signals between the ITO electrode and the LCOS display structure in order to ensure the voltage between the ITO electrode and the LCOS display structure to be in an DC balance state, and enables the service life of the liquid crystal material in the LCOS display structure to be guaranteed. The drive circuit of the ITO electrode in the LCOS display structure is integrated in the LCOS display structure, which reduces the wiring on the PCB board, reduces the cost, reduces the noise interference and improves the anti-interference capability.
Description
Technical field
The present invention relates to application of electronic technology field, the driving circuit of ITO electrode in especially a kind of LCOS display structure.
Background technology
Liquid crystal display is (top electrode and bottom electrode) filling liquid crystal material between two-plate, changes the arrangement situation of liquid crystal material interior molecules, to reach the object of shading and printing opacity by changing voltage between pole plate.And the characteristic of liquid crystal material determines the display effect that between two-plate, voltage just can will reach more than 5V, and between pole plate, voltage is that DC (DirectCurrent, direct current) balances, otherwise can reduce the life-span of liquid crystal material.
As shown in Figure 1, common LCOS display panels comprises substrate 101, ITO electrode 102 and LCOS display structure 103, described ITO electrode 102 is formed on described substrate 101, described LCOS display structure 103 comprises liquid crystal material and silicon base, be formed with metal electrode (i.e. bottom electrode) in described silicon base, described liquid crystal material is formed between described silicon base and ITO electrode (i.e. top electrode) 102.In order to ensure display effect and the serviceable life of liquid crystal material, the voltage between described ITO electrode 102 and metal electrode must be exceeded 5V, and is DC balance.
Therefore, need the square-wave voltage by a relatively large margin adding one-period change in described ITO electrode 102, as shown in Figure 2, the amplitude of this square-wave voltage ITO is fixing, and such as amplitude is 7V.And simultaneously on the metal electrode of LCOS display structure 103 inside, add a same phase and the controlled square wave voltage signal V0 of signal amplitude, to control the size and Orientation of voltage V1 between described ITO electrode and metal electrode, make the display effect that liquid crystal display reaches best.
Current, conventional way is the voltage signal producing described ITO electrode on pcb board, and then this voltage signal is inputed to described LCOS display structure.Thus, described ITO electrode and LCOS display structure need different power supplys, add number of power sources, too increase power consumption and the area of pcb board simultaneously, add cost.And the supply voltage of described LCOS display structure requires to be greater than 5V, cause using advanced manufacturing process to make LCOS display structure, result also in the increase of cost.Further, because the voltage signal of described ITO electrode produces on described pcb board, not necessarily can Complete Synchronization with the voltage signal on described metal electrode, also just make may not accomplish therebetween to mate completely, also just make described liquid crystal material can not be in the state of DC balance always, thus have influence on the serviceable life of described liquid crystal material.Further, the cabling on described pcb board is easily subject to the interference of neighbourhood noise, thus can reduce the antijamming capability of described liquid crystal display.
Summary of the invention
The object of the present invention is to provide the driving circuit of ITO electrode in a kind of LCOS display structure, can not the problem of Complete Synchronization to solve voltage signal on ITO electrode and metal electrode.
Another object of the present invention is to, solve the problem that LCOS display panels cost of manufacture is high.
In order to achieve the above object, the invention provides the driving circuit of ITO electrode in a kind of LCOS display structure, be integrated in LCOS display structure, comprise: power supply generation module and selection module;
Described power supply generation module is used for generating according to the operating voltage of described LCOS display structure driving ITO electrode required voltage;
Described selection module is used for the driving voltage generating described ITO electrode according to the voltage of the driving ITO electrode of described power supply generation module generation.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, the operating voltage of described LCOS display structure comprises: the first operating voltage and the second operating voltage, and the magnitude of voltage of described first operating voltage is greater than the magnitude of voltage of described second operating voltage; Described driving ITO electrode required voltage comprises: the 3rd operating voltage and the 4th operating voltage, and the magnitude of voltage of described 3rd operating voltage is greater than the magnitude of voltage of described 4th operating voltage.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described power supply generation module comprises:
Power level module, for generating the voltage of described driving ITO electrode; And
Feedback control module, for controlling the gauge tap of described power level module, with the voltage required for the driving ITO electrode stablizing described power level CMOS macro cell.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described feedback control module comprises:
First circuit, second circuit, tertiary circuit, logic controller and the 3rd comparer;
The output terminal of described second circuit and tertiary circuit is connected with the first input end of described logic controller and the second input end respectively, and the output terminal of described logic controller is connected with the input end of described power level module;
The normal phase input end of described 3rd comparer is connected to described power level module, and inverting input is connected to threshold voltage, and output terminal is connected to the 3rd input end of described logic controller.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described power level module comprises: drive circuit module and power generation module, the output terminal of described drive circuit module is connected with the input end of described power generation module, and the output terminal of described power generation module exports described 3rd operating voltage and the 4th operating voltage.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described power generation module comprises:
First MOS transistor of series connection and the 5th MOS transistor, the grid end of described first MOS transistor is connected to the first output terminal of described drive circuit module, source is connected to described first operating voltage, and the grid end of described 5th MOS is connected to ground, and drain terminal is connected to the 4th node;
7th MOS transistor of series connection and the 3rd MOS transistor, the grid end of described 7th MOS transistor is connected to described second operating voltage, drain terminal is connected to described 4th node, the grid end of described 3rd MOS transistor is connected to the second output terminal of described drive circuit module, and source is connected to the 5th node;
4th MOS transistor of series connection and the 8th MOS transistor, the grid end of described 4th MOS transistor is connected to the 3rd output terminal of described drive circuit module, source is connected to the 6th node, and the grid end of described 8th MOS transistor is connected to described second operating voltage, and drain terminal is connected to the 7th node;
6th MOS transistor of series connection and the second MOS transistor, the grid end of described 6th MOS transistor is connected to described first operating voltage, drain terminal is connected to described 7th node, and the grid end of described second MOS transistor is connected to the 4th output terminal of described drive circuit module, and source is connected to ground;
Inductance, its two ends are connected to described 4th node and the 7th node;
4th electric capacity, its two ends are connected to described 5th node and ground, and the voltage of described 5th node is described 4th operating voltage;
5th electric capacity, its two ends are connected to described 6th node and ground, and the voltage of described 6th node is described 3rd operating voltage.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described feedback control module comprises: the first circuit, second circuit and tertiary circuit.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described power level module comprises: the first charge pump, the second charge pump, the 6th electric capacity and the 7th electric capacity;
The clock synchronous of described first charge pump and the second charge pump;
The first input end of described first charge pump is connected with the output terminal of described second circuit, and the second input end is connected with described first operating voltage, and output terminal is connected with described 3rd operating voltage, and is connected to ground by one the 6th electric capacity;
The first input end of described second charge pump is connected with the output terminal of described tertiary circuit, and the second input end is connected to ground, and output terminal is connected with described 4th operating voltage, and is connected to ground by one the 7th electric capacity.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described first circuit comprises: the first resistance, the second resistance and the first electric capacity, one end of described first resistance is connected to described first operating voltage, one end of the other end and described second resistance is series at first node, the other end of described second resistance is connected to ground, and described first node is connected to a reference voltage, and described first electric capacity and the second resistor coupled in parallel are between described first node and ground.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described second circuit comprises: the first comparer, the 3rd resistance, the 4th resistance and the second electric capacity; The normal phase input end of described first comparer is connected to Section Point, one end of described 3rd resistance and one end of the 4th resistance are series at described Section Point, the other end of described 3rd resistance is connected to described 3rd operating voltage, the other end of described 4th resistance is connected to ground, and described second electric capacity and described 3rd resistor coupled in parallel are between described Section Point and ground; Inverting input is connected to described reference voltage; Output terminal is connected to the input end of logic controller.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described tertiary circuit comprises: the second comparer, the 5th resistance, the 6th resistance and the 3rd electric capacity; The normal phase input end of described second comparer is connected to described reference voltage; Inverting input is connected to the 3rd node, one end of described 5th resistance and one end of the 6th resistance are series at described 3rd node, the other end of described 5th resistance is connected to described first operating voltage, the other end of described 6th resistance is connected to described 4th operating voltage, and described 3rd electric capacity and described 6th resistor coupled in parallel are between described first operating voltage and the 4th operating voltage; Output terminal is connected to described logic controller;
The resistance of described first resistance and the second resistance is equal, and the resistance of described 3rd resistance and the 6th resistance is equal, and the resistance of described 4th resistance and the 5th resistance is equal, and the magnitude of voltage of described first operating voltage is the magnitude of voltage twice of described reference voltage.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described selection module comprises: the first level conversion and driver module, second electrical level conversion and driver module, the 9th MOS transistor, the tenth MOS transistor, the 11 MOS transistor, the 12 MOS transistor and protection circuit;
The source of described 9th MOS transistor is connected with described 3rd operating voltage, and the source of drain terminal and described 12 MOS transistor is series at the 8th node, and grid end is connected to the output terminal of described first level conversion and driver module;
The drain terminal of described 12 MOS transistor and the drain terminal of described 11 MOS transistor are series at the 9th node, the described grid end of the 11 MOS transistor and the grid of the 12 MOS transistor are connected to protelum point, and described protelum point is connected to described second operating voltage;
The source of described 11 MOS transistor and the drain terminal of described tenth MOS transistor are series at the 11 node, and the grid end of described tenth MOS transistor is connected to the output terminal of the conversion of described second electrical level and driver module, and drain terminal is connected to described 4th operating voltage;
The input end of described first level conversion and driver module is connected to the clock signal of described LCOS display structure, and two reference edges are connected to described 3rd operating voltage and the second operating voltage;
The input end of described second electrical level conversion and driver module is connected to the clock signal of described LCOS display structure, and two reference edges are connected to described second operating voltage and the 4th operating voltage;
Described 8th node, the 9th node and the 11 node are connected with described protection circuit respectively.
Preferably, in above-mentioned LCOS display structure ITO electrode driving circuit in, described protection circuit comprises: the 7th resistance, the 8th resistance, the 9th resistance, the first electrostatic releaser, the second electrostatic releaser, the 3rd electrostatic releaser and the 4th electrostatic releaser;
One end of described 7th resistance is connected to described 8th node, the other end is connected to the grid end of described first electrostatic releaser, the grid end of described first electrostatic releaser is connected with source, and be connected with the drain terminal of described 3rd electrostatic releaser, the source of described 3rd electrostatic releaser is connected with grid end, and is connected with described second operating voltage;
One end of described 8th resistance is connected to described 9th node, the other end is connected to the 12 node, the drain terminal of described first electrostatic releaser and the drain terminal of described second electrostatic releaser are connected to described 12 node, and the voltage of described 12 node is the driving voltage of described ITO electrode;
One end of described 9th resistance is connected to described 11 node, the other end is connected to grid end and the source of described second electrostatic releaser, the grid end of described second electrostatic releaser is connected with source, and be connected with the drain terminal of described 4th electrostatic releaser, the grid end of described 4th electrostatic releaser is connected with source, and is connected to described second operating voltage;
The resistance value of described 7th resistance and the 9th resistance is equal.
In LCOS display structure provided by the invention ITO electrode driving circuit in, this driving circuit is integrated in described LCOS display structure, power supply generation module is used for generating according to the operating voltage of described LCOS display structure driving ITO electrode required voltage, and the voltage selecting module to be used for the driving ITO electrode produced according to described power supply generation module generates the driving voltage of described ITO electrode.The driving circuit of described ITO electrode and LCOS display structure is made to adopt identical power supply, thus the supply voltage of reduction driving circuit is to adapt to advanced technique, reduce chip size, save power consumption, voltage signal Complete Synchronization between described ITO electrode and LCOS display structure can also be ensured, to ensure that the voltage between described ITO electrode and LCOS display structure is in the state of DC balance always, is guaranteed in the serviceable life of liquid crystal material in described LCOS display structure.Further, in this LCOS display structure, the driving circuit of ITO electrode is integrated in LCOS display structure, decreases the cabling on PCB, reduces cost, reduces the interference of neighbourhood noise, improves jamproof ability.
Accompanying drawing explanation
Fig. 1 is the structural representation of liquid crystal display in prior art;
Fig. 2 is the schematic diagram of ITO electrode in prior art, metal electrode and the voltage signal between described ITO electrode and metal electrode;
Fig. 3 is the structural representation of the driving circuit of ITO electrode in LCOS display structure in the embodiment of the present invention one;
Fig. 4 is the circuit diagram of feedback control module in the embodiment of the present invention one;
Fig. 5 is the schematic diagram of power level module in the embodiment of the present invention one;
Fig. 6 is the circuit diagram of power generation module in the embodiment of the present invention one;
Fig. 7 is the circuit diagram selecting module in the embodiment of the present invention one;
Fig. 8 is the circuit diagram of power level module in the embodiment of the present invention two;
In figure: 101-substrate; 102-ITO electrode; 103-LCOS display structure;
200-power supply generation module; 300-selects module; 201-feedback control module; 202-power level module;
First operating voltage-VDD3; Second operating voltage-VDD; 3rd operating voltage-VP; 4th operating voltage-VN; 2011-first circuit; 2012-second circuit; 2013-tertiary circuit; 2014-the 3rd comparer; 2015-logic controller; 2016-first comparer; 2017-second comparer; REF-reference voltage;
2021-drive circuit module; 2022-power generation module;
301-protection circuit; 302-first level conversion and driver module; The conversion of 303-second electrical level and driver module;
401-first charge pump; 402-second charge pump.
Embodiment
Below in conjunction with schematic diagram, the specific embodiment of the present invention is described in more detail.According to following description and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Embodiment one
Embodiments provide the driving circuit of ITO electrode in a kind of LCOS display structure, as shown in Figure 3, comprise power supply generation module 200 and select module 300, described power supply generation module 200 drives ITO electrode required voltage for generating according to the operating voltage of described LCOS display structure, and described selection module 300 generates the driving voltage of described ITO electrode for the voltage of the driving ITO electrode produced according to described power supply generation module 200.
The operating voltage of described LCOS display structure comprises: the first operating voltage VDD3 and the second operating voltage VDD, and the magnitude of voltage of described first operating voltage VDD3 is greater than the magnitude of voltage of described second operating voltage VDD.Described driving ITO electrode required voltage comprises: the 3rd operating voltage VP and the 4th operating voltage VN, and the magnitude of voltage of described 3rd operating voltage VP is greater than the magnitude of voltage of described 4th operating voltage VN.
Concrete, described power supply generation module 200 comprises power level module 202 and feedback control module 201, and described power level module 202 drives the voltage of ITO electrode for generating, i.e. described 3rd operating voltage VP and the 4th operating voltage VN.Described feedback control module 201 for controlling the gauge tap of described power level module 202, with stablize described power level module 202 generate driving ITO electrode required for voltage.
As shown in Figure 4, described feedback control module 201 includes but not limited to: the first circuit 2011, second circuit 2012, tertiary circuit 2013, logic controller 2015 and the 3rd comparer 2014.The output terminal of described second circuit 2012 and tertiary circuit 2013 is connected with the first input end of described logic controller 2015 and the second input end respectively, and the output terminal of described logic controller 2015 is connected with the input end of described power level module 202.The normal phase input end of described 3rd comparer 2014 is connected to described power level module 202, and inverting input is connected to threshold voltage, and output terminal is connected to the 3rd input end of described logic controller 2015.
Described first circuit 2011 comprises: the first resistance, the second resistance and the first electric capacity C1, one end of described first resistance is connected to described first operating voltage VDD3, one end of the other end and described second resistance is series at first node D1, the other end of described second resistance is connected to ground, described first node D1 is connected to a reference voltage REF, and described first electric capacity C1 and the second resistor coupled in parallel are between described first node D1 and ground.Wherein, the resistance of described first resistance and the second resistance is equal, i.e. R1=R2.
Described second circuit 2012 comprises: the first comparer 2016, the 3rd resistance, the 4th resistance and the second electric capacity C2; The normal phase input end of described first comparer 2016 is connected to Section Point D2, one end of described 3rd resistance and one end of the 4th resistance are series at described Section Point D2, the other end of described 3rd resistance is connected to described 3rd operating voltage VP, the other end of described 4th resistance is connected to ground, and described second electric capacity C2 and described 3rd resistor coupled in parallel are between described Section Point D2 and ground; Inverting input is connected to described reference voltage REF; Output terminal is connected to the input end of logic controller 2015.
Described tertiary circuit 2013 comprises: the second comparer 2017, the 5th resistance, the 6th resistance and the 3rd electric capacity C3; The normal phase input end of described second comparer 2017 is connected to described reference voltage REF; Inverting input is connected to the 3rd node D3, one end of described 5th resistance and one end of the 6th resistance are series at described 3rd node D3, the other end of described 5th resistance is connected to described first operating voltage VDD3, the other end of described 6th resistance is connected to described 4th operating voltage VN, and described 3rd electric capacity C3 and described 6th resistor coupled in parallel are between described first operating voltage VDD3 and the 4th operating voltage VN; Output terminal is connected to described logic controller 2015.Wherein, the resistance of described 3rd resistance and the 6th resistance is equal, and the resistance of described 4th resistance and the 5th resistance is equal, and the magnitude of voltage of described first operating voltage VDD3 is the magnitude of voltage twice of described reference voltage REF.
I.e. R3=R6, R4=R5, REF=(VDD3)/2.
Can be derived by Fig. 4:
Because the consistance of the VDD-to-VSS in described LCOS display structure is good, as long as make coupling between resistance R1 ~ R6 good, described 3rd operating voltage VP and the 4th operating voltage VN can be made to follow described first operating voltage VDD3 and the second operating voltage VDD accurately.
I.e. VP-VDD3=GND-VN.(formula 3)
As shown in Figure 5, described power level module 202 adopts the structure of single inductance dual output, comprise drive circuit module 2021 and power generation module 2022, the output terminal of described drive circuit module 2021 is connected with the input end of described power generation module 2022, and the output terminal of described power generation module 2022 exports described 3rd operating voltage VP and the 4th operating voltage VN.
As shown in Figure 6, described power generation module 2022 includes but not limited to: the first MOS transistor of series connection and the 5th MOS transistor, the grid end of described first MOS transistor is connected to the first output terminal of described drive circuit module 2021, source is connected to described first operating voltage VDD3, the grid end of described 5th MOS is connected to ground, and drain terminal is connected to the 4th node D4; 7th MOS transistor M7 of series connection and the 3rd MOS transistor M3, the grid end of described 7th MOS transistor is connected to described second operating voltage VDD, drain terminal is connected to described 4th node D4, the grid end of described 3rd MOS transistor is connected to the second output terminal of described drive circuit module 2021, and source is connected to the 5th node D5; 4th MOS transistor M4 of series connection and the 8th MOS transistor M8, the grid end of described 4th MOS transistor M4 is connected to the 3rd output terminal of described drive circuit module 2021, source is connected to the 6th node D6, the grid end of described 8th MOS transistor M8 is connected to described second operating voltage VDD, and drain terminal is connected to the 7th node D7; 6th MOS transistor M6 of series connection and the second MOS transistor M2, the grid end of described 6th MOS transistor M6 is connected to described first operating voltage VDD3, drain terminal is connected to described 7th node D7, the grid end of described second MOS transistor M2 is connected to the 4th output terminal of described drive circuit module 2021, and source is connected to ground; Inductance, its two ends are connected to described 4th node D4 and the 7th node D7; 4th electric capacity C4, its two ends are connected to described 5th node D5 and ground, and the voltage of described 5th node D5 is described 4th operating voltage VN; 5th electric capacity C5, its two ends are connected to described 6th node D6 and ground, and the voltage of described 6th node D6 is described 3rd operating voltage VP.
Wherein, described first MOS transistor M1, the 4th MOS transistor M4, the 5th MOS transistor M5 and the 8th MOS transistor M8 are N-type MOS transistor, and described second MOS transistor M2, the 3rd MOS transistor M3, the 6th MOS transistor M6 and the 7th MOS transistor M7 are N-type MOS transistor.
The mode adopting MOS transistor to connect in described power level module 202 ensures that each MOS transistor can not overvoltage.When the absolute value of voltage of described 3rd operating voltage VP and the 4th operating voltage VN reduces, described 3rd comparer 2014 can overturn, the the first MOS transistor M1 being by described Logic control module and drive circuit module 2021 and the second MOS transistor M2 opens, to described induction charging.The signal that the normal phase input end of described 3rd comparer 2014 connects is the voltage signal changed according to the current signal of described inductance.Along with the electric current of described inductance rises, after reaching described threshold voltage according to the voltage signal of its conversion, if described 3rd operating voltage VP is low, then described second MOS transistor M2 disconnects, described 4th MOS transistor M4 conducting, described 5th electric capacity C5 is charged, to increase the absolute value of voltage of described 3rd operating voltage VP.If described 4th operating voltage VN is greater than described threshold voltage, then described first MOS transistor M1 disconnects, and described 3rd MOS transistor M3 conducting, charges to described 4th electric capacity C4, to increase the absolute value of voltage of described 4th operating voltage VN.
Described threshold voltage is relevant to the conducting resistance of each MOS transistor in described power level module 202.Its magnitude of voltage is 0.5V ~ 3V, specifically can set according to actual conditions.
As shown in Figure 7, described selection module 300 includes but not limited to: the first level conversion and driver module 302, second electrical level conversion and driver module 303, the 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11, the 12 MOS transistor M12 and protection circuit 301; Concrete, the source of described 9th MOS transistor M9 is connected with described 3rd operating voltage VP, and the source of drain terminal and described 12 MOS transistor M12 is series at the 8th node D8, and grid end is connected to the output terminal of described first level conversion and driver module 302; The drain terminal of described 12 MOS transistor M12 and the drain terminal of described 11 MOS transistor M11 are series at the 9th node D9, the described end of the 11 MOS transistor M11 and the grid of the 12 MOS transistor M12 are connected to protelum point D10, and described protelum point D10 is connected to described second operating voltage VDD; The source of described 11 MOS transistor M11 and the drain terminal of described tenth MOS transistor M10 are series at the 11 node D11, the grid end of described tenth MOS transistor M10 is connected to the output terminal of the conversion of described second electrical level and driver module 303, and drain terminal is connected to described 4th operating voltage VN; The input end of described first level conversion and driver module 302 is connected to the clock signal Sel of described LCOS display structure, and two reference edges are connected to described 3rd operating voltage VP and the second operating voltage VDD; The input end of described second electrical level conversion and driver module 303 is connected to the clock signal Sel of described LCOS display structure, and two reference edges are connected to described second operating voltage VDD and the 4th operating voltage VN; Described 8th node D8, the 9th node D9 and the 11 node D11 are connected with described protection circuit 301 respectively.
The clock signal Sel being operated in VDD and GND power domain is transformed into the clock signal of VP and VDD power domain in order to drive the grid of the 9th MOS transistor M9 by the first level conversion and driver module.Clock signal Sel is transformed into the clock signal of VDD and VN power domain in order to drive the grid of the tenth MOS transistor M10 by second electrical level conversion and driver module.
Wherein, described 9th MOS transistor M9 and the 12 MOS transistor M12 is N-type MOS transistor, and described tenth MOS transistor M10 and the 11 MOS transistor M11 is N-type MOS transistor.Described first electrostatic releaser and the 4th electrostatic releaser are N-type MOS transistor, and described second electrostatic releaser and the 3rd electrostatic releaser are N-type MOS transistor.
With described first operating voltage VDD3 for 3.3V, described second operating voltage VDD is 1.5V, described 3rd operating voltage VP is 5.3V, described 4th operating voltage VN is-2V is example, the pressure reduction of 7.3V is had between described 3rd operating voltage VP and the 4th operating voltage VN, the operating voltage of the MOS transistor selected in the present embodiment is 3.3V, reduces power consumption and cost, can ensure again the object having enough pressure reduction between described 3rd operating voltage VP and the 4th operating voltage VN simultaneously to reach.Thus cause any one MOS transistor in the present embodiment all cannot bear the high pressure of 7.3V.Therefore in described selection module 300, multiple MOS transistor is together in series, such as, the series connection of described 9th MOS transistor M9 and the 12 MOS transistor M12, the series connection of described 11 MOS transistor M11 and the tenth MOS transistor M10.
Described 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11 source equal with respective with the substrate of the 12 MOS transistor M12 is connected.Described 11 MOS transistor M11 is all connected with described second operating voltage VDD with the grid end of the 12 MOS transistor M12, the control circuit that the grid end of described 9th MOS transistor M9 connects between described 3rd operating voltage VP and the second operating voltage VDD exports, and the control circuit that the grid end of described tenth MOS transistor M10 connects between described second operating voltage VDD and the 4th operating voltage VN exports.So described 9th MOS transistor M9 and the tenth MOS transistor M10 is normal open.
When the voltage of described 9th node D9, namely when the driving voltage of described ITO electrode exports as described 3rd operating voltage VP, described tenth MOS transistor M10 disconnects, the voltage of described 11 node D11 is limited in (described second operating voltage VDD-Vthn) by described 11 MOS transistor M11, wherein Vthn is the threshold voltage of N-type MOS transistor in the embodiment of the present invention, be generally 0.3V ~ 1V, that concrete is 0.7V, therefore the value of (described second operating voltage VDD-Vthn) is (1.5V-0.7V)=0.8V, the source-drain voltage of M10 and M11 is all less than 4.5V, lower than the voltage breakdown 5V of MOS transistor, when the voltage of described 9th node D9, namely when the driving voltage of described ITO electrode exports as described 4th operating voltage VN, described 9th MOS transistor M9 disconnects, the voltage of described 8th node D8 is limited in (described second operating voltage VDD+Vthp) by described 12 MOS transistor M12, wherein Vthp is the threshold voltage of N-type MOS transistor in the embodiment of the present invention, be generally 0.3V ~ 1V, that concrete is 0.7V, therefore the value of (described second operating voltage VDD+Vthp) is (1.5V+0.7V)=2.2V, the source-drain voltage of M9 and M12 is all less than 4.4V, lower than the voltage breakdown 5V of MOS transistor.Therefore described 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11 and the 12 MOS transistor M12 all can not overvoltage.
In other embodiments of the invention, the change of the plate voltage needed along with liquid crystal display material, can also select the MOS transistor of other operating voltage to realize technical scheme of the present invention.Do not repeat them here.
Described protection circuit 301 includes but not limited to: the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the first electrostatic releaser ESD1, the second electrostatic releaser ESD2, the 3rd electrostatic releaser ESD3 and the 4th electrostatic releaser ESD4; One end of described 7th resistance R7 is connected to described 8th node D8, the other end is connected to the grid end of described first electrostatic releaser ESD1, the grid end of described first electrostatic releaser ESD1 is connected with source, and be connected with the drain terminal of described 3rd electrostatic releaser ESD3, the source of described 3rd electrostatic releaser ESD3 is connected with grid end, and is connected with described second operating voltage VDD; One end of described 8th resistance R8 is connected to described 9th node D9, the other end is connected to the 12 node D12, the drain terminal of described first electrostatic releaser ESD1 and the drain terminal of described second electrostatic releaser ESD2 are connected to described 12 node D12, and the voltage of described 12 node D12 is the driving voltage of described ITO electrode; One end of described 9th resistance R9 is connected to described 11 node D11, the other end is connected to grid end and the source of described second electrostatic releaser ESD2, the grid end of described second electrostatic releaser is connected with source, and be connected with the drain terminal of described 4th electrostatic releaser, the grid end of described 4th electrostatic releaser ESD4 is connected with source, and is connected to described second operating voltage VDD; The resistance value of described 7th resistance R7 and the 9th resistance R9 is equal, and the resistance value of described 8th resistance R8 can be determined according to the driving force of the rise and fall time index of ITO output signal and described selection module 300.
Described protection circuit 301 utilize the driving voltage of described ITO electrode and the pressure reduction between described 8th node D8, the 11 node D11 less; divide two-stage Electro-static Driven Comb (ESD, Electro-Staticdischarge) structure that electrostatic leakage electric current is discharged into described second operating voltage VDD.
Embodiment two
In the present embodiment, described feedback control module 201 comprises: the first circuit 2011, second circuit 2012 and tertiary circuit 2013.Described first circuit 2011, second circuit 2012, tertiary circuit 2013 are all identical with the structure in embodiment one, do not repeat them here.
As shown in Figure 8, corresponding with it described power level module 202 module but be not limited to: the first charge pump 401, second charge pump 402, the 6th electric capacity C6 and the 7th electric capacity C7; The clock synchronous of described first charge pump 401 and the second charge pump 402; The first input end EN of described first charge pump 401 is connected with the output terminal of described second circuit 2012, and the second input end is connected with described first operating voltage VDD3, and output terminal is connected with described 3rd operating voltage VP, and is connected to ground by one the 6th electric capacity C6; The first input end EN of described second charge pump 402 is connected with the output terminal of described tertiary circuit 2013, and the second input end is connected to ground, and output terminal is connected with described 4th operating voltage VN, and is connected to ground by one the 7th electric capacity C7.
Described first charge pump 401 is positive pump, and described second charge pump 402 is negative pump.Utilize the output terminal of described second circuit 2012 to control the Enable Pin of described first charge pump 401, utilize the output terminal of described tertiary circuit 2013 to control the Enable Pin of described second charge pump 402.When the absolute value of voltage of described 3rd operating voltage VP reduces, open described first charge pump, described 6th electric capacity C6 is charged, to improve the absolute value of voltage of described 3rd operating voltage VP, the absolute value of voltage of described 3rd operating voltage VP is made to return to setting value, still with described first operating voltage VDD3 for 3.3V, described second operating voltage VDD is 1.5V, described 3rd operating voltage VP is 5.3V, described 4th operating voltage VN is-2V is example, and the setting value of the absolute value of voltage of described 3rd operating voltage VP is 5.3V in the present embodiment.When the absolute value of voltage of described 4th operating voltage VN reduces, open described second charge pump, described 7th electric capacity C7 is charged, to improve the absolute value of voltage of described 4th operating voltage VN, the absolute value of voltage of described 4th operating voltage VN is made to return to setting value, in the present embodiment, the setting value of the absolute value of voltage of described 4th operating voltage VN is 2V.
In other embodiments of the invention, other charge pump circuit can also be adopted to produce described 3rd operating voltage VP and the 4th operating voltage VN, do not repeat them here.
Other parts are all identical with the structure in embodiment one, do not repeat them here.
To sum up, in the LCOS display structure that the embodiment of the present invention provides ITO electrode driving circuit in, this driving circuit is integrated in described LCOS display structure, power supply generation module is used for generating according to the operating voltage of described LCOS display structure driving ITO electrode required voltage, and the voltage selecting module to be used for the driving ITO electrode produced according to described power supply generation module generates the driving voltage of described ITO electrode.The driving circuit of described ITO electrode and LCOS display structure is made to adopt identical power supply, thus the supply voltage of reduction driving circuit is to adapt to advanced technique, reduce chip size, save power consumption, voltage signal Complete Synchronization between described ITO electrode and LCOS display structure can also be ensured, to ensure that the voltage between described ITO electrode and LCOS display structure is in the state of DC balance always, is guaranteed in the serviceable life of liquid crystal material in described LCOS display structure.Further, in this LCOS display structure, the driving circuit of ITO electrode is integrated in LCOS display structure, decreases the cabling on PCB, reduces cost, reduces the interference of neighbourhood noise, improves jamproof ability.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (13)
1. the driving circuit of ITO electrode in LCOS display structure, is characterized in that, be integrated in LCOS display structure, comprise: power supply generation module and select module;
Described power supply generation module is used for generating according to the operating voltage of described LCOS display structure driving ITO electrode required voltage;
Described selection module is used for the driving voltage generating described ITO electrode according to the voltage of the driving ITO electrode of described power supply generation module generation.
2. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 1, it is characterized in that, the operating voltage of described LCOS display structure comprises the first operating voltage and the second operating voltage, and the magnitude of voltage of described first operating voltage is greater than the magnitude of voltage of described second operating voltage; Described driving ITO electrode required voltage comprises the 3rd operating voltage and the 4th operating voltage, and the magnitude of voltage of described 3rd operating voltage is greater than the magnitude of voltage of described 4th operating voltage.
3. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 2, it is characterized in that, described power supply generation module comprises:
Power level module, for generating the voltage of described driving ITO electrode; And
Feedback control module, for controlling the gauge tap of described power level module, with the voltage required for the driving ITO electrode stablizing described power level CMOS macro cell.
4. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 3, it is characterized in that, described feedback control module comprises: the first circuit, second circuit, tertiary circuit, logic controller and the 3rd comparer;
The output terminal of described second circuit and tertiary circuit is connected with the first input end of described logic controller and the second input end respectively, and the output terminal of described logic controller is connected with the input end of described power level module;
The normal phase input end of described 3rd comparer is connected to described power level module, and inverting input is connected to threshold voltage, and output terminal is connected to the 3rd input end of described logic controller; Described first circuit, second circuit are all connected a reference voltage with tertiary circuit.
5. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 4, it is characterized in that, described power level module comprises: drive circuit module and power generation module;
The output terminal of described drive circuit module is connected with the input end of described power generation module, and the output terminal of described power generation module exports described 3rd operating voltage and the 4th operating voltage.
6. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 5, it is characterized in that, described power generation module comprises:
First MOS transistor of series connection and the 5th MOS transistor, the grid end of described first MOS transistor is connected to the first output terminal of described drive circuit module, source is connected to described first operating voltage, and the grid end of described 5th MOS is connected to ground, and drain terminal is connected to the 4th node;
7th MOS transistor of series connection and the 3rd MOS transistor, the grid end of described 7th MOS transistor is connected to described second operating voltage, drain terminal is connected to described 4th node, the grid end of described 3rd MOS transistor is connected to the second output terminal of described drive circuit module, and source is connected to the 5th node;
4th MOS transistor of series connection and the 8th MOS transistor, the grid end of described 4th MOS transistor is connected to the 3rd output terminal of described drive circuit module, source is connected to the 6th node, and the grid end of described 8th MOS transistor is connected to described second operating voltage, and drain terminal is connected to the 7th node;
6th MOS transistor of series connection and the second MOS transistor, the grid end of described 6th MOS transistor is connected to described first operating voltage, drain terminal is connected to described 7th node, and the grid end of described second MOS transistor is connected to the 4th output terminal of described drive circuit module, and source is connected to ground;
Inductance, its two ends are connected to described 4th node and the 7th node;
4th electric capacity, its two ends are connected to described 5th node and ground, and the voltage of described 5th node is described 4th operating voltage;
5th electric capacity, its two ends are connected to described 6th node and ground, and the voltage of described 6th node is described 3rd operating voltage.
7. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 3, it is characterized in that, described feedback control module comprises: the first circuit, second circuit and tertiary circuit, and described first circuit, second circuit are all connected a reference voltage with tertiary circuit.
8. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 7, it is characterized in that, described power level module comprises: the first charge pump, the second charge pump, the 6th electric capacity and the 7th electric capacity;
The clock synchronous of described first charge pump and the second charge pump;
The first input end of described first charge pump is connected with the output terminal of described second circuit, and the second input end is connected with described first operating voltage, and output terminal is connected with described 3rd operating voltage, and is connected to ground by one the 6th electric capacity;
The first input end of described second charge pump is connected with the output terminal of described tertiary circuit, and the second input end is connected to ground, and output terminal is connected with described 4th operating voltage, and is connected to ground by one the 7th electric capacity.
9. as the driving circuit of ITO electrode in the LCOS display structure in claim 2-8 as described in any one, it is characterized in that, described first circuit comprises: the first resistance, the second resistance and the first electric capacity, one end of described first resistance is connected to described first operating voltage, one end of the other end and described second resistance is series at first node, the other end of described second resistance is connected to ground, described first node is connected to described reference voltage, and described first electric capacity and the second resistor coupled in parallel are between described first node and ground.
10. the driving circuit of ITO electrode in LCOS display structure as claimed in claim 9, it is characterized in that, described second circuit comprises: the first comparer, the 3rd resistance, the 4th resistance and the second electric capacity; The normal phase input end of described first comparer is connected to Section Point, one end of described 3rd resistance and one end of the 4th resistance are series at described Section Point, the other end of described 3rd resistance is connected to described 3rd operating voltage, the other end of described 4th resistance is connected to ground, and described second electric capacity and described 3rd resistor coupled in parallel are between described Section Point and ground; Inverting input is connected to described reference voltage; Output terminal is connected to the input end of logic controller.
The driving circuit of ITO electrode in 11. LCOS display structures as claimed in claim 10, it is characterized in that, described tertiary circuit comprises: the second comparer, the 5th resistance, the 6th resistance and the 3rd electric capacity; The normal phase input end of described second comparer is connected to described reference voltage; Inverting input is connected to the 3rd node, one end of described 5th resistance and one end of the 6th resistance are series at described 3rd node, the other end of described 5th resistance is connected to described first operating voltage, the other end of described 6th resistance is connected to described 4th operating voltage, and described 3rd electric capacity and described 6th resistor coupled in parallel are between described first operating voltage and the 4th operating voltage; Output terminal is connected to described logic controller;
The resistance of described first resistance and the second resistance is equal, and the resistance of described 3rd resistance and the 6th resistance is equal, and the resistance of described 4th resistance and the 5th resistance is equal, and the magnitude of voltage of described first operating voltage is the magnitude of voltage twice of described reference voltage.
The driving circuit of ITO electrode in 12. LCOS display structures as claimed in claim 2, it is characterized in that, described selection module comprises: the first level conversion and driver module, second electrical level conversion and driver module, the 9th MOS transistor, the tenth MOS transistor, the 11 MOS transistor, the 12 MOS transistor and protection circuit;
The source of described 9th MOS transistor is connected with described 3rd operating voltage, and the source of drain terminal and described 12 MOS transistor is series at the 8th node, and grid end is connected to the output terminal of described first level conversion and driver module;
The drain terminal of described 12 MOS transistor and the drain terminal of described 11 MOS transistor are series at the 9th node, the described grid end of the 11 MOS transistor and the grid of the 12 MOS transistor are connected to protelum point, and described protelum point is connected to described second operating voltage;
The source of described 11 MOS transistor and the drain terminal of described tenth MOS transistor are series at the 11 node, and the grid end of described tenth MOS transistor is connected to the output terminal of the conversion of described second electrical level and driver module, and drain terminal is connected to described 4th operating voltage;
The input end of described first level conversion and driver module is connected to the clock signal of described LCOS display structure, and two reference edges are connected to described 3rd operating voltage and the second operating voltage;
The input end of described second electrical level conversion and driver module is connected to the clock signal of described LCOS display structure, and two reference edges are connected to described second operating voltage and the 4th operating voltage;
Described 8th node, the 9th node and the 11 node are connected with described protection circuit respectively.
The driving circuit of ITO electrode in 13. LCOS display structures as claimed in claim 12, it is characterized in that, described protection circuit comprises: the 7th resistance, the 8th resistance, the 9th resistance, the first electrostatic releaser, the second electrostatic releaser, the 3rd electrostatic releaser and the 4th electrostatic releaser;
One end of described 7th resistance is connected to described 8th node, the other end is connected to the grid end of described first electrostatic releaser, the grid end of described first electrostatic releaser is connected with source, and be connected with the drain terminal of described 3rd electrostatic releaser, the source of described 3rd electrostatic releaser is connected with grid end, and is connected with described second operating voltage;
One end of described 8th resistance is connected to described 9th node, the other end is connected to the 12 node, the drain terminal of described first electrostatic releaser and the drain terminal of described second electrostatic releaser are connected to described 12 node, and the voltage of described 12 node is the driving voltage of described ITO electrode;
One end of described 9th resistance is connected to described 11 node, the other end is connected to grid end and the source of described second electrostatic releaser, the grid end of described second electrostatic releaser is connected with source, and be connected with the drain terminal of described 4th electrostatic releaser, the grid end of described 4th electrostatic releaser is connected with source, and is connected to described second operating voltage;
The resistance value of described 7th resistance and the 9th resistance is equal.
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| US20020175662A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Power supply and reference voltage circuit for TFT LCD source driver |
| CN1770248A (en) * | 2004-11-03 | 2006-05-10 | 上海华园微电子技术有限公司 | Display drive circuit for liquid crystal on silicon based on large-scale integrated circuit |
| CN101202019A (en) * | 2006-12-13 | 2008-06-18 | 中华映管股份有限公司 | Image data display method and circuit arrangement structure thereof |
| CN102662552A (en) * | 2012-04-11 | 2012-09-12 | 鸿富锦精密工业（深圳）有限公司 | Resistance-type touch panel and electronic device provided with resistance-type touch panel |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020175662A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Power supply and reference voltage circuit for TFT LCD source driver |
| CN1770248A (en) * | 2004-11-03 | 2006-05-10 | 上海华园微电子技术有限公司 | Display drive circuit for liquid crystal on silicon based on large-scale integrated circuit |
| CN101202019A (en) * | 2006-12-13 | 2008-06-18 | 中华映管股份有限公司 | Image data display method and circuit arrangement structure thereof |
| CN102662552A (en) * | 2012-04-11 | 2012-09-12 | 鸿富锦精密工业（深圳）有限公司 | Resistance-type touch panel and electronic device provided with resistance-type touch panel |
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