CN102446480B - Voltage conversion circuit - Google Patents
Voltage conversion circuit Download PDFInfo
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- CN102446480B CN102446480B CN201010509121.0A CN201010509121A CN102446480B CN 102446480 B CN102446480 B CN 102446480B CN 201010509121 A CN201010509121 A CN 201010509121A CN 102446480 B CN102446480 B CN 102446480B
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Abstract
The invention provides a voltage conversion circuit which comprises an electric charge pump module, a switch module, a level conversion module and a capacitor; the electric charge pump module is used for converting an input voltage into a predetermined voltage, when the level conversion module controls the switch module to close, the predetermined voltage is outputted by the switch module to an output end of a voltage conversion circuit; and when the level conversion module controls the switch module to open, the capacitor supplies an output voltage to the voltage conversion circuit. Only one electric charge pump is adopted to convert the input voltage to the predetermined voltage to be outputted, and the output voltage can be more than or smaller than the input voltage. One capacitor is utilized correspondently to the electric charge pump, so the size of the voltage conversion circuit can be reduced, and the cost can be reduced. Since the voltage conversion circuit has the advantages of small size, the voltage conversion circuit can be further integrated onto an array substrate of a display panel and can be synchronically completed during the production of the array substrate, so the cost of a drive chip can be further reduced.
Description
Technical field
The present invention relates to technical field of circuit design, particularly a kind of voltage conversion circuit.
Background technology
Operationally, thin film transistor (TFT) array must have the action of scanning to panel display board, makes display data sequentially stored in each display unit in thin film transistor (TFT) array.In the drive voltage circuit of thin film transistor (TFT) array, a voltage level shifter must be used, for converting the clock signal of low-voltage to high-tension clock signal.Like this, this high-tension clock signal just has enough abilities to drive late-class circuit, completes the display of panel display board.
At present, the voltage conversion circuit producing high-tension clock signal comprises two charge pumps, two corresponding two electric capacity of charge pump.
Two charge pumps replace the output of control voltage change-over circuit, thus realize the clock signal of voltage conversion circuit output HIGH voltage.But because the volume of electric capacity and charge pump itself is comparatively large, the area of such two electric capacity and circuit corresponding to two charge pumps is also larger.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of voltage conversion circuit, can reduce the area of circuit board.
The embodiment of the present invention provides a kind of voltage conversion circuit, comprising: electric charge pump module, switch module, level switch module and a capacitor;
The input signal of electric charge pump module comprises the first clock signal, second clock signal and input voltage; Described first clock signal and second clock signal are the clock signal of a pair complementation; The output terminal of electric charge pump module is connected to the input end of switch module, and switch module output terminal is as the output terminal of voltage conversion circuit, and the output terminal of voltage conversion circuit passes through capacitor grounding;
The control end of switch module connects the output terminal of level switch module, the conducting of described level switch module gauge tap module and disconnection, the input signal of described level switch module comprises described second clock signal, and the output voltage of voltage conversion circuit is as the power supply of level switch module;
Within front 1/2 cycle of a work period, input voltage is transported to the output terminal of electric charge pump module by electric charge pump module under the control of the first clock signal and second clock signal, and switch module disconnects by level switch module under the control of second clock signal;
Within rear 1/2 cycle of a work period, input voltage is changed into predetermined voltage by electric charge pump module under the control of the first clock signal and second clock signal, level switch module is by switch module conducting under the control of second clock signal, and predetermined voltage provides output voltage by switch module to the output terminal of voltage conversion circuit and is predetermined voltage to the voltage that capacitor charges on capacitor.
Preferably, by changing the amplitude of second clock signal or different predetermined voltages can being obtained by changing input voltage.
Preferably, described level switch module is for providing the control end that an amplitude equals voltage conversion circuit output voltage values, control signal that phase place is contrary with second clock signal outputs to switch control module.
Preferably, the output voltage of described voltage conversion circuit equal input voltage and second clock signal amplitude and.
Preferably, described first clock signal, second clock signal and input voltage are all powered by same supply voltage, and the output voltage of voltage conversion circuit is 2 times of input voltage.
Preferably, described electric charge pump module comprises the first NMOS tube, the first PMOS, the second PMOS and the first electric capacity;
The grid of the first NMOS tube is all connected the first clock signal with the grid of the first PMOS;
The source ground of the first NMOS tube;
The drain electrode of the first NMOS tube is all connected the grid of the second PMOS with the drain electrode of the first PMOS;
The source electrode of the first PMOS is all connected second clock signal by the first electric capacity with the drain electrode of the second PMOS; The source electrode of the first PMOS and the drain electrode of the second PMOS link together as the output terminal of electric charge pump module;
The source electrode of the second PMOS connects input voltage.
Preferably, described switch module comprises the 3rd PMOS;
The source electrode of the 3rd PMOS, as the first end of switch module, connects the output terminal of electric charge pump module;
The drain electrode of the 3rd PMOS is as the second end of switch module;
The grid of the 3rd PMOS, as the control end of switch module, connects the output terminal of level switch module.
Preferably, described level switch module comprises: the 4th PMOS, the 5th PMOS, the second NMOS tube, the 3rd NMOS tube, the first phase inverter and the second phase inverter;
The source electrode of the 4th PMOS and the second end of the equal connecting valve module of the 5th PMOS source electrode;
The grid of the 4th PMOS connects the drain electrode of the 5th PMOS, and the drain electrode of the 4th PMOS connects the grid of the 5th PMOS;
The grid of the second NMOS tube connects second clock signal by the first phase inverter, and the grid of the 3rd NMOS tube connects second clock signal;
The source electrode of the second NMOS tube and the source grounding of the 3rd NMOS tube;
The drain electrode of the second NMOS tube connects the drain electrode of the 4th PMOS, and the drain electrode of the 3rd NMOS tube connects the drain electrode of the 5th PMOS;
The drain electrode of the 4th PMOS connects the input end of the second phase inverter, and the output terminal of the second phase inverter is as the control end of the output terminal connecting valve module of level switch module.
Preferably, the output voltage of described voltage conversion circuit equals the difference that input voltage deducts second clock signal amplitude.
Preferably, described first clock signal, second clock signal and input voltage are powered by same supply voltage, and the output voltage of voltage conversion circuit is-1 times of input voltage.
Preferably, described electric charge pump module comprises the 6th PMOS, the 5th NMOS tube, the 4th NMOS tube and the 3rd electric capacity;
The grid of the 6th PMOS is all connected the first clock signal with the grid of the 4th NMOS tube;
The source electrode of the 6th PMOS connects input voltage;
Drain electrode and the drain electrode of the 4th NMOS tube of the 6th PMOS are all connected the grid of the 5th NMOS tube;
The grounded drain of the 5th NMOS tube;
The source electrode of the 4th NMOS tube is all connected second clock signal by the 3rd electric capacity with the source electrode of the 5th NMOS tube;
The source electrode of the 4th NMOS tube and the source electrode of the 5th NMOS tube link together as the output terminal of electric charge pump module.
Preferably, described switch module comprises the 6th NMOS tube;
The drain electrode of the 6th NMOS tube, as the first end of switch module, connects the output terminal of electric charge pump module;
The source electrode of the 6th NMOS tube is as the second end of switch module;
The grid of the 6th NMOS tube, as the control end of switch module, connects the output terminal of level switch module.
Preferably, described level switch module comprises: the 7th PMOS, the 8th PMOS, the 7th NMOS tube, the 8th NMOS tube, the 3rd phase inverter and the 4th phase inverter;
7th PMOS is all connected input voltage with the source electrode of the 8th PMOS;
Second clock signal connects the grid of the 7th PMOS by the 3rd phase inverter, and second clock signal connects the grid of the 8th PMOS;
The drain electrode of the 7th PMOS connects the drain electrode of the 7th NMOS tube, and the 8th PMOS connects the drain electrode of the 8th NMOS tube;
Second end of the source electrode of the 7th NMOS tube and the equal connecting valve module of source electrode of the 8th NMOS tube;
The grid of the 7th NMOS tube connects the drain electrode of the 8th NMOS tube, and the drain electrode of the 7th NMOS tube connects the grid of the 8th NMOS tube;
The drain electrode of the 7th NMOS tube connects the input end of the 4th phase inverter, and the output terminal of the 4th phase inverter is as the control end of the output terminal connecting valve module of level switch module.
Preferably, described voltage conversion circuit is integrated on the array base palte of display panel.
Compared with prior art, the present invention has the following advantages:
Voltage conversion circuit provided by the invention, only adopt a charge pump, input voltage is converted to multiplication of voltage voltage, the amplitude of this multiplication of voltage voltage is the prearranged multiple of input voltage.Such charge pump correspondence make use of an electric capacity, thus can reduce the volume of voltage conversion circuit, reduces costs.Because voltage conversion circuit provided by the invention has the advantage of small size, can also be integrated on the array base palte of display panel further, and synchronously complete in the making of array base palte, can further reduce driving chip cost.
Accompanying drawing explanation
Fig. 1 is voltage conversion circuit embodiment one structural drawing provided by the invention;
Fig. 2 is voltage conversion circuit one embodiment circuit diagram provided by the invention;
Fig. 3 is another embodiment circuit diagram of voltage conversion circuit provided by the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
See Fig. 1, this figure is voltage conversion circuit embodiment one structural drawing provided by the invention;
The voltage conversion circuit that the present embodiment provides, comprising: electric charge pump module 1, switch module 2, level switch module 3 and capacitor C2;
The input signal of electric charge pump module 1 comprises the first clock signal C K, second clock signal CKB and input voltage vin; Described first clock signal C K and second clock signal CKB is the clock signal of a pair complementation, that is, when CK is high level, CKB is low level; When CK is low level, CKB is high level;
Electric charge pump module 1, under the control of the first clock signal C K and second clock signal CKB, exports after input voltage vin being converted to predetermined voltage; It should be noted that, the voltage after electric charge pump module 1 conversion is pulse voltage, and predetermined voltage is the amplitude voltage of this pulse voltage.This predetermined voltage can be greater than or less than input voltage vin, and its change is subject to the control of the first clock signal C K, second clock signal CKB, and its variation range is relevant with the amplitude of input voltage vin and second clock signal CKB.Such as, when the predetermined voltage that the first clock signal C K and second clock signal CKB controls to export is greater than input voltage vin, the scope of the pulse voltage after described conversion is (input voltage vin, the amplitude sum of input voltage vin and second clock signal CKB), such as input voltage vin is 5V, and the amplitude of second clock signal CKB is 5V, then the pulsating sphere of pulse voltage is (5,10), namely electric charge pump module 10 pairs of input voltage vin raise; When the predetermined voltage that the first clock signal C K and second clock signal CKB controls to export is less than input voltage vin, the scope of the pulse voltage after described conversion is (input voltage vin, the difference of the amplitude of input voltage vin and second clock signal CKB), such as input voltage vin is 0V, the amplitude of second clock signal CKB is 5V, then the pulsating sphere of pulse voltage is (0 ,-5), and namely electric charge pump module 1 pair of input voltage vin reduces.The amplitude of input voltage vin and second clock signal CKB also can be other values in other embodiments, and corresponding just can obtain different scheduled voltages.
The input end of the output terminal connecting valve module 2 of electric charge pump module 1, the output terminal of switch module 2 is as the output terminal of voltage conversion circuit; The output terminal OUT of voltage conversion circuit is by capacitor C2 ground connection;
The output voltage of voltage conversion circuit output terminal OUT is as the power supply of level switch module 3; The control end of the output terminal connecting valve module 2 of level switch module 3;
The input signal of level switch module 3 comprises described second clock signal CKB, and level switch module 3 is for providing the control end that an amplitude equals voltage conversion circuit output voltage values, control signal that phase place is contrary with second clock signal exports to switch module 2.
Switch module 2, under the control of level switch module 3, carries out selection to the pulse voltage of electric charge pump module 1 and exports.As mentioned above, input voltage vin can carry out raising or reduce rear output by the electric charge pump module 1 under different clocks signal and output voltage control, as electric charge pump module 1 pair of input voltage raise after voltage be required predetermined voltage, pulse voltage scope after conversion is (input voltage vin, the amplitude sum of input voltage vin and second clock signal CKB), a steady state value being greater than input voltage to make the output voltage of voltage conversion circuit and predetermined voltage, when pulse voltage is high level and predetermined voltage, now level switch module 3 gauge tap module 2 conducting, by high level output to the output end vo ut of voltage conversion circuit, and capacitor C2 is charged simultaneously, when pulse voltage is low level, now level switch module 3 gauge tap module 2 disconnects, and the pulse voltage low level of electric charge pump module 1 is not exported.
When switch module 2 disconnects, provide to the output end vo ut of voltage conversion circuit the predetermined voltage being greater than input voltage by capacitor C2.Above, voltage conversion circuit just can obtain the constant output voltage that is greater than input voltage.Vice versa for the principle of work reduced input voltage as needed, and no longer describes in detail herein, and those skilled in the art can release according to the principle of work raised input voltage.
It should be noted that, the control signal CT that this level switch module 3 exports is mainly in order to match with predetermined voltage, if such as input voltage vin is 5V, the amplitude of second clock signal CKB is 5V, the predetermined voltage exported is greater than input voltage vin, its amplitude is 10V, then the amplitude of control signal CT equals voltage conversion circuit output voltage values, so mainly in order to ensure the closed and disconnected of gauge tap module.
Voltage conversion circuit provided by the invention, only utilize an electric charge pump module just can realize the object that input voltage is improved or reduced, such electric charge pump module correspondence make use of a capacitor, just can change the output voltage of voltage conversion circuit, thus the volume of voltage conversion circuit can be reduced, reduce costs.
Voltage conversion circuit provided by the invention can change output voltage, exports after namely can raising input voltage, exports after also can reducing input voltage, is introduced respectively below to the change situation of voltage conversion circuit rising or reduction input voltage.
First introduce voltage conversion circuit and raise rear output to input voltage, namely the output voltage of voltage conversion circuit is greater than the situation of input voltage.See Fig. 2, this figure is the circuit diagram of voltage conversion circuit one embodiment that the embodiment of the present invention provides.
In this enforcement, voltage conversion circuit comprises electric charge pump module 10, switch module 20, level switch module 30, second capacitor C2 and supply voltage VDD.
Electric charge pump module 10 comprises the first NMOS tube MN1, the first PMOS MP1, the second PMOS MP2 and the first electric capacity C1;
The grid of the first NMOS tube MN1 is all connected the first clock signal C K with the grid of the first PMOS MP1;
The source ground of the first NMOS tube MN1 is VSS;
The drain electrode of the first NMOS tube MN1 is all connected the grid of the second PMOS MP2 with the drain electrode of the first PMOS MP1 by node N1;
The source electrode of the first PMOS MP1 is all connected with the first electric capacity C1 by node P1 with the drain electrode of the second PMOS MP2, and the first electric capacity C1 is connected to second clock signal CKB;
Node P1 is as the output terminal of electric charge pump module 10;
The source electrode of the second PMOS MP2 connects input voltage VDD.
Switch module 20 comprises the 3rd PMOS MP3;
The source electrode of the 3rd PMOS MP3 connects the output terminal of electric charge pump module 1O as the input end of switch module 20;
The drain electrode of the 3rd PMOS MP3, as the output terminal of switch module 20, exports the output end vo ut of voltage conversion circuit to;
Level switch module 30 comprises: the 4th PMOS MP4, the 5th PMOS MP5, the second NMOS tube MN2 and the 3rd NMOS tube MN3, the first phase inverter D1 and the second phase inverter D2;
The source electrode of the 4th PMOS MP4 and the output terminal of the equal connecting valve module 20 of the 5th PMOS MP5 source electrode, namely connect the drain electrode of the 3rd PMOS MP3;
The grid of the 4th PMOS MP4 connects the drain electrode of the 5th PMOS MP5, and the drain electrode of the 4th PMOS MP4 connects the grid of the 5th PMOS MP5;
The grid of the second NMOS tube MN2 connects second clock signal CKB by the first phase inverter D1, and the grid of the 3rd NMOS tube MN3 connects second clock signal CKB;
The source electrode of the second NMOS tube MN2 and the source grounding of the 3rd NMOS tube MN3;
The drain electrode of the second NMOS tube MN2 connects the drain electrode of the 4th PMOS MP4, and the drain electrode of the 3rd NMOS tube MN3 connects the drain electrode of the 5th PMOS MP5;
The drain electrode of the 4th PMOS MP4 connects the input end of the second phase inverter D2, and the output terminal of the second phase inverter D2, as the control end of the output terminal connecting valve module 20 of level switch module 30, namely connects the grid of the 3rd PMOS MP3.
The effect of level switch module 30 CKB of input is converted to predetermined clock signal CT to export, and CT amplitude is two times of CKB amplitude, and the phase place of these two clock signals is contrary.
The principle of work of the present embodiment is introduced below in conjunction with Fig. 2.
It is 5V that the input voltage vin of voltage conversion circuit equals supply voltage VDD, and the variation range of the first clock signal is 0 ~ 5V, and the variation range of second clock signal is 0 ~ 5V.
Before one-period during 1/2 cycle, the first clock signal C K is 5V, when second clock signal CKB is 0V, first NMOS tube MN1 conducting, first PMOS MP1 disconnects, and therefore, the voltage of node N1 is 0V (source ground due to the first NMOS tube MN1).Second PMOS MP2 conducting, sends source voltage Vin to node P1.The voltage of the first electric capacity C1 lower end is 0V, and upper end is 5V.Now, the voltage of the output terminal CT of level switch module is 5V, and therefore, the 3rd PMOS MP3 disconnects.
In next 1/2 cycle, the first clock signal C K is 0V, and when second clock signal CKB is 5V, the first NMOS tube MN1 disconnects, the first PMOS MP1 conducting, and therefore, the 5V voltage of node P1 sends node N1 to, and now the second PMOS MP2 disconnects.Because the source electrode of the 3rd PMOS MP3 is equal with the voltage of drain electrode, therefore the 3rd PMOS MP3 also closes.Now, meet the principle of charge conservation of electric capacity, therefore when second clock pulse CKB to be become the moment of 5V from 0V, the upper end of the first electric capacity C1 can become 10V from 5V moment, and then the 3rd PMOS MP3 can conducting, voltage after rising exports the voltage of 10V by the output end vo ut of voltage conversion circuit, and charges to the second electric capacity C2 and make the voltage at the second electric capacity C2 two ends reach 10V.
Again next 1/2 cycle, the first clock signal C K becomes 5V, and second clock signal CKB becomes 0V, the first NMOS tube MN1 conducting, and the first PMOS MP1 disconnects, and the voltage of node N1 node is 0V (source ground due to the first NMOS tube MN1).Second PMOS MP2 conducting.Before the voltage at the first electric capacity C1 two ends gets back to rising again, the voltage of C1 lower end is 0V, and the voltage of upper end is 5V.Now, level switch module 30 gauge tap module 20 disconnects, and the output voltage that this voltage conversion circuit OUT holds is provided by the second electric capacity C2.
In sum, repeat above switch motion and the output voltage Vout of this voltage conversion circuit just can be made to be greater than input voltage vin, namely rear output is raised to input voltage vin.
As preferred embodiment, in the voltage conversion circuit that the present embodiment provides, it is 5V that input voltage vin equals supply voltage VDD, the variation range of the first clock signal C K is 0 ~ 5V, the variation range of second clock signal CKB is 0 ~ 5V, voltage is provided by a power supply because general in circuit, namely voltage is provided to supply input voltage vin by supply voltage VDD, first clock signal C K, second clock signal CKB, so the value of input voltage vin and the first clock signal C K, the amplitude of second clock signal CKB is equal, the output voltage of voltage conversion circuit is the value of input voltage vin and the amplitude sum of second clock signal CKB, output voltage is the twice of input voltage.In other embodiments, input voltage vin and the first clock signal C K, second clock signal CKB can by different Power supplies, and obtain different output voltages thus, such as input voltage vin is 5V, first clock signal C K, second clock signal CKB change in the scope of 0V to 10V, then the output voltage obtained is 15V.
The situation that the following examples are less than input voltage with the output voltage of voltage conversion circuit explains.See Fig. 3, this figure is the another embodiment circuit diagram of voltage conversion circuit provided by the invention.
The voltage conversion circuit electric charge pump module 100 that the present embodiment provides, switch module 200, level switch module 300 and the second electric capacity C2.
The electric charge pump module 100 that the present embodiment provides comprises the 6th PMOS MP6, the 4th NMOS tube MN4, the 5th NMOS tube MN5 and the 3rd electric capacity C3;
The grid of the 6th PMOS MP6 is all connected the first clock signal C K with the grid of the 4th NMOS tube MN4;
The source electrode of the 6th PMOS MP6 connects supply voltage VDD;
The drain electrode of the 6th PMOS MP6 is all connected the grid of the 5th NMOS tube MN5 with the drain electrode of the 4th NMOS tube MN4 by node N2;
The source electrode of the 5th NMOS tube MN5 connects output voltage Vin;
The source electrode of the 4th NMOS tube MN4 is all connected second clock signal CKB by node P2 with the 3rd electric capacity C3 with the drain electrode of the 5th NMOS tube MN5, and node P3 is as the output terminal of electric charge pump module 100;
The switch module 200 that the present embodiment provides comprises the 6th NMOS tube MN6;
The source electrode of the 6th NMOS tube MN6, as the input end of switch module 200, connects the output terminal of electric charge pump module 100, i.e. connected node P2;
The drain electrode of the 6th NMOS tube MN6 is as the output terminal of switch module 200;
The grid of the 6th NMOS tube MN6, as the control end of switch module 200, connects the output terminal of level switch module 300.
The level switch module 300 that the present embodiment provides comprises: the 7th PMOS MP7, the 8th PMOS MP8, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 3rd phase inverter D3 and the 4th phase inverter D4;
7th PMOS MP7 is all connected supply voltage VDD with the source electrode of the 8th PMOS MP8;
The output terminal of second clock signal CKB connects the grid of the 7th PMOS MP7 by the 3rd phase inverter D3, the input end of second clock signal CKB connects the grid of the 8th PMOS MP8;
The drain electrode of the 7th PMOS MP7 connects the drain electrode of the 7th NMOS tube MN7, and the 8th PMOS MP8 connects the drain electrode of the 8th NMOS tube MN8;
The output terminal of the source electrode of the 7th NMOS tube MN7 and the equal connecting valve module 200 of source electrode of the 8th NMOS tube MN8, namely connects the drain electrode of the 6th NMOS tube MN6;
The grid of the 7th NMOS tube MN7 connects the drain electrode of the MN8 of the 8th NMOS tube, and the drain electrode of the 7th NMOS tube MN7 connects the grid of the 8th NMOS tube MN8;
The drain electrode of the 7th NMOS tube MN7 connects the input end of the 4th phase inverter D4, and the output terminal of the 4th phase inverter D4, as the control end of the output terminal connecting valve module 200 of level switch module 300, namely connects the grid of the 6th NMOS tube MN6.
The principle of work of the present embodiment is introduced below in conjunction with Fig. 2.
It is 0V that the defeated eight voltage Vin of voltage conversion circuit equal supply voltage VSS, and the variation range of the first clock signal is 0 ~ 5V, and the variation range of second clock signal is 0 ~ 5V, and supply voltage VDD is 5V.
Before one-period during 1/2 cycle, the first clock signal C K is 0V, and when second clock signal CKB is 5V, the 6th PMOS MP6 conducting, the 4th NMOS tube MN4 disconnects, and therefore, the voltage of node N2 is VDD.5th NMOS tube MN5 conducting, sends the 0V voltage of source voltage Vin and VSS to node P2.The voltage of the 3rd electric capacity C3 lower end is 5V, and upper end is 0V.Now, the voltage of the output terminal CT of level switch module 300 is 0V, and therefore, the 6th NMOS tube MN6 disconnects.
In next 1/2 cycle, the first clock signal C K is 5V, and when second clock signal CKB is 0V, the 6th NMOS tube MN6 disconnects, the 4th PMOS MN4 conducting, and therefore, the 0V voltage of node P2 sends node N2 to, and now the 5th NMOS tube MN5 disconnects.Because the source electrode of the 6th NMOS tube MN6 is equal with the voltage of drain electrode, therefore the 6th NMOS tube MN6 also closes.Now, meet the principle of charge conservation of electric capacity, therefore when second clock pulse CKB to be become the moment of 0V from 5V, the upper end of the 3rd electric capacity C3 can become-5V from 0V moment, and then the 6th NMOS tube MN6 can conducting, voltage after change exports the voltage of-5V by the output end vo ut of voltage conversion circuit, and charges to the second electric capacity C2 and make the voltage at the second electric capacity two ends reach-5V.
Again next 1/2 cycle, the first clock signal C K becomes 0V, and second clock signal CKB becomes 5V, the 6th PMOS MP6 conducting, and the 4th NMOS tube MN4 disconnects, and the voltage of node N2 is VDD value is 5V.5th NMOS tube MN5 conducting.Before the voltage at the 3rd electric capacity C3 two ends gets back to change again, the voltage of C3 lower end is 5V, and the voltage of upper end is 0V.Now, level switch module 300 gauge tap module 200 disconnects, and the output voltage that this voltage conversion circuit OUT holds is provided by the second electric capacity C2.
In sum, repeat above switch motion and the output voltage Vout of this voltage conversion circuit just can be made to be greater than input voltage vin, namely rear output is raised to input voltage vin.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (13)
1. a voltage conversion circuit, is characterized in that, comprising: electric charge pump module, switch module, level switch module and a capacitor;
The input signal of electric charge pump module comprises the first clock signal, second clock signal and input voltage; Described first clock signal and second clock signal are the clock signal of a pair complementation; The output terminal of electric charge pump module is connected to the input end of switch module, and switch module output terminal is as the output terminal of voltage conversion circuit, and the output terminal of voltage conversion circuit passes through capacitor grounding;
The control end of switch module connects the output terminal of level switch module, the conducting of described level switch module gauge tap module and disconnection, the input signal of described level switch module comprises described second clock signal, and the output voltage of voltage conversion circuit is as the power supply of level switch module;
Within front 1/2 cycle of a work period, input voltage is transported to the output terminal of electric charge pump module by electric charge pump module under the control of the first clock signal and second clock signal, and switch module disconnects by level switch module under the control of second clock signal;
Within rear 1/2 cycle of a work period, input voltage is changed into predetermined voltage by electric charge pump module under the control of the first clock signal and second clock signal, level switch module is by switch module conducting under the control of second clock signal, and predetermined voltage provides output voltage by switch module to the output terminal of voltage conversion circuit and is predetermined voltage to the voltage that capacitor charges on capacitor;
Described level switch module comprises: the 4th PMOS, the 5th PMOS, the second NMOS tube, the 3rd NMOS tube, the first phase inverter and the second phase inverter;
The source electrode of the 4th PMOS and the second end of the equal connecting valve module of the 5th PMOS source electrode;
The grid of the 4th PMOS connects the drain electrode of the 5th PMOS, and the drain electrode of the 4th PMOS connects the grid of the 5th PMOS;
The grid of the second NMOS tube connects second clock signal by the first phase inverter, and the grid of the 3rd NMOS tube connects second clock signal;
The source electrode of the second NMOS tube and the source grounding of the 3rd NMOS tube;
The drain electrode of the second NMOS tube connects the drain electrode of the 4th PMOS, and the drain electrode of the 3rd NMOS tube connects the drain electrode of the 5th PMOS;
The drain electrode of the 4th PMOS connects the input end of the second phase inverter, and the output terminal of the second phase inverter is as the control end of the output terminal connecting valve module of level switch module.
2. voltage conversion circuit according to claim 1, is characterized in that, by changing the amplitude of second clock signal or can obtaining different predetermined voltages by changing input voltage.
3. voltage conversion circuit according to claim 1, it is characterized in that, described level switch module is for providing the control end that an amplitude equals voltage conversion circuit output voltage values, control signal that phase place is contrary with second clock signal outputs to switch control module.
4. voltage conversion circuit according to claim 1, is characterized in that, the output voltage of described voltage conversion circuit equal input voltage and second clock signal amplitude and.
5. voltage conversion circuit according to claim 4, is characterized in that, described first clock signal, second clock signal and input voltage are all powered by same supply voltage, and the output voltage of voltage conversion circuit is 2 times of input voltage.
6. voltage conversion circuit according to claim 4, is characterized in that, described electric charge pump module comprises the first NMOS tube, the first PMOS, the second PMOS and the first electric capacity;
The grid of the first NMOS tube is all connected the first clock signal with the grid of the first PMOS;
The source ground of the first NMOS tube;
The drain electrode of the first NMOS tube is all connected the grid of the second PMOS with the drain electrode of the first PMOS;
The source electrode of the first PMOS is all connected second clock signal by the first electric capacity with the drain electrode of the second PMOS; The source electrode of the first PMOS and the drain electrode of the second PMOS link together as the output terminal of electric charge pump module;
The source electrode of the second PMOS connects input voltage.
7. voltage conversion circuit according to claim 4, is characterized in that, described switch module comprises the 3rd PMOS;
The source electrode of the 3rd PMOS, as the first end of switch module, connects the output terminal of electric charge pump module;
The drain electrode of the 3rd PMOS is as the second end of switch module;
The grid of the 3rd PMOS, as the control end of switch module, connects the output terminal of level switch module.
8. a voltage conversion circuit, is characterized in that, comprising: electric charge pump module, switch module, level switch module and a capacitor;
The input signal of electric charge pump module comprises the first clock signal, second clock signal and input voltage; Described first clock signal and second clock signal are the clock signal of a pair complementation; The output terminal of electric charge pump module is connected to the input end of switch module, and switch module output terminal is as the output terminal of voltage conversion circuit, and the output terminal of voltage conversion circuit passes through capacitor grounding;
The control end of switch module connects the output terminal of level switch module, the conducting of described level switch module gauge tap module and disconnection, the input signal of described level switch module comprises described second clock signal, and the output voltage of voltage conversion circuit is as the power supply of level switch module;
Within front 1/2 cycle of a work period, input voltage is transported to the output terminal of electric charge pump module by electric charge pump module under the control of the first clock signal and second clock signal, and switch module disconnects by level switch module under the control of second clock signal;
Within rear 1/2 cycle of a work period, input voltage is changed into predetermined voltage by electric charge pump module under the control of the first clock signal and second clock signal, level switch module is by switch module conducting under the control of second clock signal, and predetermined voltage provides output voltage by switch module to the output terminal of voltage conversion circuit and is predetermined voltage to the voltage that capacitor charges on capacitor;
Described level switch module comprises: the 7th PMOS, the 8th PMOS, the 7th NMOS tube, the 8th NMOS tube, the 3rd phase inverter and the 4th phase inverter;
7th PMOS is all connected input voltage with the source electrode of the 8th PMOS;
Second clock signal connects the grid of the 7th PMOS by the 3rd phase inverter, and second clock signal connects the grid of the 8th PMOS;
The drain electrode of the 7th PMOS connects the drain electrode of the 7th NMOS tube, and the 8th PMOS connects the drain electrode of the 8th NMOS tube;
Second end of the source electrode of the 7th NMOS tube and the equal connecting valve module of source electrode of the 8th NMOS tube;
The grid of the 7th NMOS tube connects the drain electrode of the 8th NMOS tube, and the drain electrode of the 7th NMOS tube connects the grid of the 8th NMOS tube;
The drain electrode of the 7th NMOS tube connects the input end of the 4th phase inverter, and the output terminal of the 4th phase inverter is as the control end of the output terminal connecting valve module of level switch module.
9. voltage conversion circuit according to claim 8, is characterized in that, the output voltage of described voltage conversion circuit equals the difference that input voltage deducts second clock signal amplitude.
10. voltage conversion circuit according to claim 9, is characterized in that, described first clock signal, second clock signal and input voltage are powered by same supply voltage, and the output voltage of voltage conversion circuit is-1 times of input voltage.
11. voltage conversion circuits according to claim 9, is characterized in that, described electric charge pump module comprises the 6th PMOS, the 5th NMOS tube, the 4th NMOS tube and the 3rd electric capacity;
The grid of the 6th PMOS is all connected the first clock signal with the grid of the 4th NMOS tube;
The source electrode of the 6th PMOS connects input voltage;
Drain electrode and the drain electrode of the 4th NMOS tube of the 6th PMOS are all connected the grid of the 5th NMOS tube;
The grounded drain of the 5th NMOS tube;
The source electrode of the 4th NMOS tube is all connected second clock signal by the 3rd electric capacity with the source electrode of the 5th NMOS tube;
The source electrode of the 4th NMOS tube and the source electrode of the 5th NMOS tube link together as the output terminal of electric charge pump module.
12. voltage conversion circuits according to claim 9, is characterized in that, described switch module comprises the 6th NMOS tube;
The drain electrode of the 6th NMOS tube, as the first end of switch module, connects the output terminal of electric charge pump module;
The source electrode of the 6th NMOS tube is as the second end of switch module;
The grid of the 6th NMOS tube, as the control end of switch module, connects the output terminal of level switch module.
13. voltage conversion circuits according to claim 8, is characterized in that, described voltage conversion circuit is integrated on the array base palte of display panel.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010509121.0A CN102446480B (en) | 2010-10-14 | 2010-10-14 | Voltage conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010509121.0A CN102446480B (en) | 2010-10-14 | 2010-10-14 | Voltage conversion circuit |
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| CN102446480A CN102446480A (en) | 2012-05-09 |
| CN102446480B true CN102446480B (en) | 2015-04-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103368383B (en) * | 2013-07-24 | 2015-09-02 | 苏州加古尔微电子科技有限公司 | For the ON-OFF control circuit of DC-DC boost converter |
| DE102016109118A1 (en) | 2016-05-18 | 2017-11-23 | Infineon Technologies Ag | Circuit architecture for a measuring device, a level converter circuit, a charge pumping stage and a charge pump and method for operating these |
| DE102016109114A1 (en) * | 2016-05-18 | 2017-11-23 | Infineon Technologies Ag | Circuit architecture for a measuring device, a level converter circuit, a charge pumping stage and a charge pump and method for operating these |
| CN107516542B (en) * | 2017-07-03 | 2020-07-10 | 合肥格易集成电路有限公司 | IO circuit and memory |
| CN108962119B (en) * | 2018-08-01 | 2021-11-02 | 京东方科技集团股份有限公司 | Level shift circuit, driving method thereof and display device |
| CN114664269B (en) * | 2022-04-21 | 2023-07-28 | 京东方科技集团股份有限公司 | Working power supply conversion circuit, display driving plate and liquid crystal display |
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|---|---|---|---|---|
| US6483728B1 (en) * | 2000-12-22 | 2002-11-19 | Matrix Semiconductor, Inc. | Charge pump circuit |
| JP2006276457A (en) * | 2005-03-29 | 2006-10-12 | Optrex Corp | Voltage generating circuit in liquid crystal drive circuit |
| TW200933562A (en) * | 2008-01-31 | 2009-08-01 | Tpo Displays Corp | Images display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483728B1 (en) * | 2000-12-22 | 2002-11-19 | Matrix Semiconductor, Inc. | Charge pump circuit |
| JP2006276457A (en) * | 2005-03-29 | 2006-10-12 | Optrex Corp | Voltage generating circuit in liquid crystal drive circuit |
| TW200933562A (en) * | 2008-01-31 | 2009-08-01 | Tpo Displays Corp | Images display system |
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| CN102446480A (en) | 2012-05-09 |
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