CN101277562B - Power supply circuit and display device - Google Patents
Power supply circuit and display device Download PDFInfo
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- CN101277562B CN101277562B CN2008100885457A CN200810088545A CN101277562B CN 101277562 B CN101277562 B CN 101277562B CN 2008100885457 A CN2008100885457 A CN 2008100885457A CN 200810088545 A CN200810088545 A CN 200810088545A CN 101277562 B CN101277562 B CN 101277562B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
- H05B41/14—Circuit arrangements
- H05B41/24—Circuit arrangements in which the lamp is fed by high frequency ac, or with separate oscillator frequency
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
- H05B41/14—Circuit arrangements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
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- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I 1 and I 2 when a clock DCCLK is inverted, resistances R 1 of a wiring 11 , R 2 of a wiring 12 and R 4 of a wiring 14 are set so as to satisfy relations R 4> R 1 and R 4> R 2 . That is, the through currents I 1 and I 2 can be suppressed by reducing the resistances R 1 and R 2 so that electric potentials are quickly inverted when the clock DCCLK is inverted. Also, the through current I 1 can be suppressed to suppress the reduction in the positive output electric potential VPP by setting the resistance R 4 to be larger than either of the resistances R 1 and R 2.
Description
Technical field
The present invention relates to power circuit and possess the display device of this power circuit.
Background technology
Since in the past, passing through low temperature polycrystalline silicon TFT (Thin Film Transistor, thin film transistor (TFT)) in the active array type LCD of manufacture process manufacturing, in order to reduce the cost of drive signal IC, be formed with power circuit on the glass substrate of liquid crystal panel, this power circuit produces the power supply potential in order to conducting (the on)/shutoff (off) of control pixel TFT.
In described power circuit, have: make positive supply current potential VDD as the input current potential become 2 times and produce 2VDD charge pump (charge pump) mode the positive electricity source generating circuit and make positive power supply potential VDD become-1 times and produce the negative electricity source generating circuit of the charge pump mode of negative power supply potential-VDD.
A plurality of electric charges that described positive electricity source generating circuit, negative electricity source generating circuit possess through being connected in series transmit transistor and are coupled in the flying capacitor that electric charge transmits transistorized connected node.Moreover, synchronous with the clock frequency that puts on flying capacitor, transmit transistor and switch electric charge, via the electric charge transfer assembly electric charge is sent to outgoing side from input side thus.
The active array type LCD of building in the above-mentioned power circuit on the glass substrate is recorded in patent document 1.
Patent document 1: TOHKEMY 2004-146082 communique
Summary of the invention
The problem that the invention desire solves
Yet, in above-mentioned power circuit, when clock frequency is reversed, have at electric charge and transmit the situation that produces unnecessary through current in the transistor.If produce unnecessary through current, then the efficient of power circuit reduces, and the increase that causes the not enough of output potential or consume electric power.
The scheme of dealing with problems
Being characterized as of power circuit of the present invention possesses: first and second electric charge through being connected in series transmits transistor; First distribution provides to described first electric charge and transmits transistorized source electrode in order to will import current potential; Output capacitor, it is connected in described second electric charge and transmits transistor drain; And flying capacitor, one square end is connected in described first electric charge transmission transistor AND gate, second electric charge via second distribution and transmits transistorized connected node, and is applied with clock frequency at the opposing party's terminal; The resistance value of described first distribution is bigger than the resistance value of described second distribution.
The effect of invention
According to power circuit of the present invention, the unnecessary through current that is produced in the time of can suppressing the clock frequency counter-rotating, and can suppress the deficiency of output potential, the increase that consumes electric power.
Description of drawings
Fig. 1 is the circuit diagram according to the power circuit of first embodiment of the present invention and second embodiment.
Fig. 2 is the oscillogram of expression according to the action of the positive electricity source generating circuit of first embodiment of the present invention and second embodiment.
Fig. 3 is the layout of expression according to the distribution of the power circuit of first embodiment of the present invention and second embodiment.
Fig. 4 is the oscillogram of expression according to the action of the negative electricity source generating circuit of first embodiment of the present invention and second embodiment.
Fig. 5 is the circuit diagram according to the power circuit of the 3rd embodiment of the present invention.
Fig. 6 is the circuit diagram according to the power circuit of the 4th embodiment of the present invention.
Symbol description
1 positive electricity source generating circuit, 2 negative electricity source generating circuits
3,3A driver IC 4 buffer circuits
11,12,13,14,21,22,23,24 distributions
100 glass substrate C1, C2, C11, C12 flying capacitor
C3, C13 output capacitor DCCLK clock frequency
The horizontal clock frequency I1 of HCLK, I2, I3, I4 through current
MP1, MP2, MP11, MP12 P channel-type electric charge transmit transistor
MN1, MN2, MN11, MN12 N channel-type electric charge transmit transistor
P1, P2, P3, P11, P13 terminal
R1, R2, R3, R4, R11, R12, R13, R14 resistance value
V1, V2, V3, V4 current potential VBB output potential (power supply terminal)
VCLK vertical clock frequency VDD power supply potential (ground terminal)
VPP output potential VSS earthing potential
W1, W2, W3, W 4 distribution width XDCCLK clock frequencies
Embodiment
First embodiment
Fig. 1 is the circuit diagram that shows the power circuit of first embodiment.Described power circuit be by: according to positive input current potential VDD produce positive output potential VPP=2VDD positive electricity source generating circuit 1, and constituted in order to the negative electricity source generating circuit 2 that produces negative output potential VBB=-VDD.Power supply potential VDD (example of " input power supply " of the present invention), earthing potential VSS, and special-purpose clock frequency and providing to these circuit are provided for driver IC 3.The power supply potential 2VDD that is produced ,-VDD provides to the vertical drive circuit in order to the vertical scanning signal of the conducting/shutoff of the pixel TFT that produces each pixel that control is disposed at pixel region as power supply potential.
In addition, described power circuit is by (the System On Glass of system on glass with the required circuit function of the integrated driving liquid crystal of low temperature polycrystalline silicon TFT manufacturing technology, SOG) technology, and be formed on the glass substrate 100 (liquid crystal panel) of active array type LCD.On glass substrate 100, except that power circuit and driver IC 3, though also be formed with vertical drive circuit, horizontal drive circuit, and accept, only display power supply circuit and driver IC 3 in Fig. 1 from the horizontal time-base of these driving circuits, the pixel region of vertical scanning signal.
In positive electricity source generating circuit 1, N channel-type electric charge transmits transistor MN1 (example of " first electric charge transmits transistor " of the present invention) and is connected in series with P channel-type electric charge transmission transistor MP1 (example of " second electric charge transmits transistor " of the present invention), at described transistorized connected node, be connected with square end of flying capacitor C1 (example of " (first) flying capacitor " of the present invention) via distribution 11 (example of " second distribution " of the present invention).Flying capacitor C1 is the CSET that is arranged at outside the glass substrate 100.Distribution 11 is for being connected in the distribution of square end of flying capacitor C1 from described connected node via being arranged at terminals P 1 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 11 is made as R1.
In addition, N channel-type electric charge transmits transistor MN2 (example of " tricharged transmits transistor " of the present invention) and is connected in series with P channel-type electric charge transmission transistor MP2 (example of " the 4th electric charge transmits transistor " of the present invention), at described transistorized connected node, be connected with square end of flying capacitor C2 (example of " second flying capacitor " of the present invention) via distribution 12 (example of " the 3rd distribution " of the present invention).Flying capacitor C2 also is the CSET that is arranged at outside the glass substrate 100.Distribution 12 is the distributions that are connected in square end of flying capacitor C2 from described connected node via being located at the terminals P 2 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 12 is made as R2.
In addition, the grid of MN1 and MP1 is connected in the connected node of MN2 and MP2, and the grid of MN2 and MP2 is connected in the connected node of MN1 and MP1.
The source electrode that N channel-type electric charge transmits transistor MN1, MN2 interconnects, and forms common source electrode.In described common source electrode, be applied with positive power supply potential VDD as the input current potential from driver IC 3 (input power supply) via distribution 14 (example of " first distribution " of the present invention).Distribution 14 is the distributions in order to the power supply terminal VDD that connects described common source electrode and driver IC 3, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 14 is made as R4.The drain electrode of MP1 and MP2 interconnects and forms common drain electrode (output terminal).Described common drain electrode is connected in square end of output capacitor C3 (example of " output capacitor " of the present invention) via distribution 13.The opposing party's terminal ground connection of output capacitor C3.Distribution 13 is the distributions that are connected in square end of output capacitor C3 from common drain electrode via being located at the terminals P 3 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 13 is made as R3.
In addition, be applied to the opposing party's terminal of flying capacitor C2 from the clock frequency DCCLK (example of " second clock frequency " of the present invention) of driver IC 3, and then be applied to the opposing party's terminal of flying capacitor C1 from the clock frequency XDCCLK (example of " first clock frequency " of the present invention) (the counter-rotating clock frequency of DCCLK) of driver IC 3.
The elemental motion of above-mentioned positive electricity source generating circuit 1 is described with reference to Fig. 2.When clock frequency DCCLK is L current potential (VSS), counter-rotating clock frequency XDCCLK is H current potential (VDD), and MN1, MP2 are off state, MN2, MP1 are conducting state, the current potential V1 of the connected node of MN1 and MP1 boosts by the capacitive coupling of flying capacitor C1 and is 2VDD, and its current potential is exported by MP1.The current potential V2 of the connected node of MN2 and MP2 is charged as VDD.
Then, when clock frequency DCCLK was H current potential (VDD), MN1, MP2 were conducting state, and MN2, MP1 are off state, the current potential V2 of the connected node of MN2 and MP2 boosts by the capacitive coupling of flying capacitor C2 and is 2VDD, and its current potential is exported via MP2.Current potential V1 is charged as VDD.Generally speaking, transmit by electric charge, the cascade transistor circuit from about the positive electricity source generating circuit 1 is alternately exported the output potential VPP of 2VDD.
Yet, because the time constant due to the grid capacitance of resistance value R1, the R2 of distribution 11,12 and electric charge transmission transistor MN1, MN2, MP1, MP2, and have in rise time, the fall time of the clock frequency of the connected node of connected node, MN2 and the MP2 of MN1 and MP1 elongatedly, make unnecessary through current be circulated to electric charge and transmit transistorized situation.Describe its reason in detail with reference to Fig. 1 and Fig. 2.
As previously mentioned, when clock frequency DCCLK was the L current potential, MN1, MP2 were off state, and MN2, MP1 are conducting state.Thereafter, when clock frequency DCCLK when L current potential (VSS) is reversed to H current potential (VDD), then current potential V2 transfers 2VDD to from VDD, current potential V1 then is reversed to VDD from 2VDD.Yet because the influence of described time constant, the fall time of the rise time of current potential V2 and current potential V1 can be elongated.Thus, during this period, still be in conducting state because MP1, MN2 can not turn-off fully, therefore unnecessary through current I1 can be circulated to the power supply terminal VDD of driver IC 3 from distribution 12 via MN2.In addition, unnecessary through current I2 then circulates in distribution 11 from output terminal via MP1.
That is, if MN2 can't turn-off, then current potential V2 will be difficult to reach 2VDD because of through current I1, and the current sinking of driver IC 3 is increased.Moreover if current potential V2 does not reach 2VDD, then MP1 can't turn-off, and produces through current I2, and current potential V1 is difficult to reach VDD, and makes MN2 be difficult to turn-off, and output potential VPP also reduces.
Current potential V2 charges to 10V gradually though described state is temporary transient continuing, and current potential V1 charges to 5V gradually, if the gate source voltage across poles Vgs of MN2, MP1 becomes below the threshold value, then MN2, MP1 turn-off, and through current I1, I2 stop.
Therefore, in the present embodiment, transitional through current I1, I2 when reversing, and the reduction of inhibition output potential VPP in order to suppress above-mentioned clock frequency DCCLK, and set resistance value R1, R2, R4 in the mode that satisfies following relation:
The resistance value R1 of the resistance value R4 of distribution 14＞distribution 11,
The resistance value R2 of the resistance value R4 of distribution 14＞distribution 12.
That is, by resistance value R1, R2 are reduced, can make because of the counter-rotating of current potential V1, V2 due to the counter-rotating of clock frequency DCCLK and carry out rapidly, thereby can suppress through current I1, I2.In addition, bigger by resistance value R4 is set for than resistance value R1, R2, can suppress through current I1, and suppress the reduction of output potential VPP.In addition, for the effect that fully obtains to suppress through current I1, I2, the effect that suppresses the reduction of output potential VPP, resistance value R4 be preferably than each resistance value R1, R2 high about 1.5 times or more than, this point has obtained to confirm in experiment.
Part on the glass substrate 100 of distribution 11,12,14 for example can form by aluminum wiring.As shown in Figure 3, distribution 11,12 is disposed between positive electricity source generating circuit 1 and terminals P 1, the P2.In addition, distribution 14 is disposed between the power supply terminal VDD of positive electricity source generating circuit 1 and driver IC 3.Moreover described distribution length L about equally and can be different and resistance value R1, R2, R4 be adjusted into satisfy above-mentioned relation by making the distribution width.That is, be made as W4, then form the relation of W4＜W1, W4＜W2 if the distribution width that the distribution width of distribution 11 is made as W1, distribution 12 is made as the distribution width of W2, distribution 14.
Then illustrate that with reference to Fig. 1 the circuit of negative electricity source generating circuit 2 constitutes.N channel-type electric charge transmits transistor MN11 and P channel-type electric charge transmission transistor MP11 is connected in series, and is connected with square end of flying capacitor C11 via distribution 21 at described transistorized connected node.Flying capacitor C11 is a CSET.Distribution 21 is the distributions that are connected in square end of flying capacitor C11 from described connected node via being located at the terminals P 11 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of this distribution 21 is made as R11.
In addition, N channel-type electric charge transmits transistor MN12 and P channel-type electric charge transmission transistor MP12 is connected in series, and is connected with square end of flying capacitor C12 via distribution 22 at described transistorized connected node.Flying capacitor C12 also is the CSET of being located at outside the glass substrate 100.Distribution 22 is the distributions that are connected in square end of flying capacitor C12 from described connected node via being located at the terminals P 12 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 22 is made as R12.
In addition, the grid of MN11 and MP11 is connected in the connected node of MN12 and MP12, and the grid of MN12 and MP12 is connected in the connected node of MN11 and MP11.
The source electrode that P channel-type electric charge transmits transistor MP11, MP12 interconnects and forms common source electrode.In described common source electrode, be applied with earthing potential VSS as the input current potential from driver IC 3 via distribution 24.Distribution 24 is the distributions that are connected with the ground terminal VSS of driver IC 3 in order to described common source electrode, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 24 is made as R14.
The drain electrode of MN11 and MN12 interconnects and forms common drain electrode (output terminal).Described common drain electrode is connected in square end of output capacitor C13 via distribution 23.The opposing party's terminal ground connection of output capacitor C13.Distribution 23 is the distributions that are connected in square end of output capacitor C13 from common drain electrode via being located at the terminals P 13 on the glass substrate 100, and it comprises distribution part and glass substrate 100 installation distribution part outward on the glass substrate 100.The resistance value of described distribution 23 is made as R13.
In addition, put on the opposing party's terminal of flying capacitor C12, and put on the opposing party's terminal of flying capacitor C11 from the clock frequency XDCCLK (the counter-rotating clock frequency of DCCLK) of driver IC 3 from the clock frequency DCCLK of driver IC 3.
The elemental motion of above-mentioned negative electricity source generating circuit 2 is described with reference to Fig. 4.When clock frequency DCCLK is L current potential (VSS), counter-rotating clock frequency XDCCLK is H current potential (VDD), and MN11, MP12 are off state, MN12, MP11 are conducting state, the current potential V3 of the connected node of MN11 and MP11 is charged as VSS, and the capacitive coupling of the current potential V4 of the connected node of MN12 and MP12 by flying capacitor C12 be reduced to-the VDD current potential, and its current potential is exported via MN12.
If clock frequency DCCLK becomes H current potential (VDD), then MN11, MP12 are conducting state, and MN12, MP11 are off state, and the capacitive coupling of current potential V3 by flying capacitor C11 be reduced to-VDD, and its current potential is exported via MN11.Current potential V4 is charged as VSS.Generally speaking, transmit by electric charge, the cascade transistor circuit from about negative electricity source generating circuit 2 replaces the current potential of output-VDD as output potential VBB.
At described negative electricity source generating circuit 2, transitional through current I3, I4 during the clock frequency that also circulates DCCLK counter-rotating.(with reference to Fig. 1) but is in the other direction with through current I1, the I2 of positive electricity source generating circuit 1.
Transitional through current I3, I4 when reversing, and the rising of inhibition output potential VBB in order to suppress above-mentioned clock frequency DCCLK, and set resistance value R11, R12, R14 in the mode that satisfies following relation:
The resistance value R11 of the resistance value R14 of distribution 24＞distribution 21,
The resistance value R12 of the resistance value R14 of distribution 24＞distribution 22.
That is, by resistance value R11, R12 are reduced, the counter-rotating of current potential V3, V4 due to the clock frequency DCCLK counter-rotating is carried out rapidly, thereby can be suppressed through current I3, I4.In addition, also bigger by resistance value R14 is set for than resistance value R11, R12, can suppress through current I3, and suppress the rising of output potential VBB.In addition, for the effect that fully obtains to suppress through current I3, I4, the effect that suppresses the rising of output potential VBB, resistance value R14 be preferably than each resistance value R11, R12 big 2 times or more than.
Part on the glass substrate 100 of distribution 21,22,24 can form by for example aluminum wiring.As shown in Figure 3, distribution 21,22 is disposed between negative electricity source generating circuit 2 and terminals P 11, the P12.In addition, distribution 24 is disposed between the power supply terminal VSS of negative electricity source generating circuit 2 and driver IC 3.Moreover described distribution length L about equally and can be different and resistance value R11, R12, R14 be adjusted into satisfy above-mentioned relation by making the distribution width.That is, be made as W14, then form the relation of W14＜W11, W14＜W12 if the distribution width that the distribution width of distribution 21 is made as W11, distribution 22 is made as the distribution width of W12, distribution 24.
Second embodiment
In present embodiment, in above-mentioned positive electricity source generating circuit 1, transitional through current I1, I2 when reversing, and the reduction of inhibition output potential VPP in order to suppress above-mentioned clock frequency DCCLK, and set resistance value R1, R2, R3 in the mode that satisfies following relation:
The resistance value R1 of the resistance value R3＞distribution 11 of distribution 13 (example of " the 4th distribution " of the present invention),
The resistance value R2 of the resistance value R3 of distribution 13＞distribution 12.
That is, by resistance value R1, R2 are reduced, can make because of the counter-rotating of current potential V1, V2 due to the clock frequency DCCLK counter-rotating and carry out rapidly, thereby can suppress through current I1, I2.In addition, also bigger by resistance value R3 is set for than resistance value R1, R2, can suppress through current I2, and suppress the reduction of output potential VPP.In addition, for the effect that fully obtains to suppress through current I1, I2, the effect that suppresses the reduction of output potential VPP, resistance value R3 be preferably than each resistance value R1, R2 big 2 times or more than.
Part on the glass substrate 100 of distribution 11,12,13 can form by for example aluminum wiring.As shown in Figure 3, distribution 11,12,13 is disposed between positive electricity source generating circuit 1 and terminals P 1, P2, the P3.Moreover described distribution length L equates, and can be different and resistance value R1, R2, R3 be adjusted into satisfy above-mentioned relation by making the distribution width.That is, be made as W3, then form the relation of W3＜W1, W3＜W2 if the distribution width that the distribution width of distribution 11 is made as W1, distribution 12 is made as the distribution width of W2, distribution 13.
In addition, in negative electricity source generating circuit 2, transitional through current I3, I4 when reversing, and the rising of inhibition output potential VBB in order to suppress clock frequency DCCLK, and set resistance value R11, R12, R13 in the mode that satisfies following relation:
The resistance value R11 of the resistance value R13 of distribution 23＞distribution 21,
The resistance value R12 of the resistance value R13 of distribution 23＞distribution 22.
That is, by resistance value R11, R12 are reduced, can make because of the counter-rotating of current potential V3, V4 due to the clock frequency DCCLK counter-rotating and carry out rapidly, thereby can suppress through current I3, I4.In addition, also bigger by resistance value R13 is set for than resistance value R11, R12, can suppress through current I3, and suppress the rising of output potential VBB.In addition, for the effect that fully obtains to suppress through current I3, I4, the effect that suppresses the rising of output potential VBB, resistance value R13 be preferably than each resistance value R11, R12 big 2 times or more than.
Part on the glass substrate 100 of distribution 21,22,23 for example can form by aluminum wiring.As shown in Figure 3, distribution 21,22,23 is disposed between negative electricity source generating circuit 2 and terminals P 11, P12, the P13.Moreover described distribution length L equates, and can be different and resistance value R11, R12, R13 be adjusted into satisfy above-mentioned relation by making the distribution width.That is, be made as W13, then form the relation of W13＜W11, W13＜W12 if the distribution width that the distribution width of distribution 21 is made as W11, distribution 22 is made as the distribution width of W12, distribution 23.
The 3rd embodiment
The power circuit of first embodiment, second embodiment produces special-purpose clock frequency with driver IC 3, and in the power circuit of present embodiment, horizontal clock frequency HCLK, the vertical clock frequency VCLK of the existing signal of conduct that horizontal time-base, the vertical scanning signal of utilization generation active array type LCD is required produce clock frequency DCCLK, XDCCLK that power circuit drives usefulness.
As shown in Figure 5, horizontal clock frequency HCLK, vertical clock frequency VCLK export from driver IC 3A.The situation that the driving force of horizontal clock frequency HCLK, vertical clock frequency VCLK is not high is a lot.Therefore, horizontal clock frequency HCLK, vertical clock frequency VCLK carry out shaping by buffering (buffer) circuit 4 (example of " buffer circuit " of the present invention) with its waveform, and form clock frequency DCCLK, XDCCLK that power circuit drives usefulness.Buffer circuit 4 can be made of a plurality of phase inverters (inverter).Clock frequency DCCLK, XDCCLK put on corresponding flying capacitor C1, C2, C11, C12 equally with first embodiment.Driver IC 3A, buffer circuit 4 are arranged on the glass substrate 100 of active array type LCD.
Identical as for other formation with first embodiment or second embodiment, as first embodiment, resistance value by making the distribution from the flying capacitor to the power generation circuit is less than the resistance value from the input power supply of driver IC to the distribution of power generation circuit, or as second embodiment, resistance value by making the distribution from the flying capacitor to the power generation circuit is less than the resistance value of the distribution from the output capacitor to the power generation circuit, the unnecessary through current that is produced in the time of can suppressing the clock frequency counter-rotating, and the deficiency of inhibition output potential, consume the increase of electric power.
The 4th embodiment
In the power circuit of this embodiment, as shown in Figure 6, flying capacitor C1, C2, C11, C12 are formed on the glass substrate 100 of active array type LCD.Flying capacitor C1, C2, C11, C12 can form by low temperature polycrystalline silicon TFT manufacturing technology.In this case, though the capacitance of flying capacitor C1, C2, C11, C12 is subjected to this point restriction of circuit pattern area, but under the situation that is not sought after the power circuit ability and no problem, and can cuts down outer relay part and seek to reduce cost.
Identical when constituting with first embodiment or second embodiment as for other, as first embodiment, by making wired electric resistance from the flying capacitor to the power generation circuit less than wired electric resistance from the input power supply of driver IC to power generation circuit, or as second embodiment, by making wired electric resistance from the flying capacitor to the power generation circuit less than the wired electric resistance from the output capacitor to the power generation circuit, the unnecessary through current that is produced in the time of can suppressing the clock frequency counter-rotating, and suppress the deficiency of output potential, the increase that consumes electric power.
At the embodiment that this disclosed, all only be exemplary from every side, rather than in order to limit the present inventor.Scope of the present invention, it is not the explanation that is defined in above-mentioned embodiment, but be scope with the content that claim was disclosed, and also include and the implication of claim equalization and all changes in the scope, for example, in the power circuit of first embodiment to the, four embodiments, though be set side by side with positive electricity source generating circuit 1 and negative electricity source generating circuit 2, also wherein arbitrary circuit can only be set.In addition, though the power circuit of first embodiment to the, three embodiments for the counter-rotating of the polarity of foundation clock frequency from about cascade transistor circuit with the output potential power circuit of bipolar clamper (clamp) mode of output alternately, but the present invention is equally also applicable to the power circuit of the one pole clamper mode of using a cascade transistor circuit.
In addition, power generation circuit is so long as flying capacitor, provide clock frequency clock generation circuit to flying capacitor, utilize electric charge to transmit transistor and will import the circuit that the current potential conversion is exported, then be not limited to the circuit of embodiment first to the 3rd embodiment, also can be the circuit of other form.
In addition, the power circuit of first embodiment to the, three embodiments, though utilize TN pattern, vertical alignment mode (VA pattern), utilize the transverse electric field IPS (In-Plane Switching) pattern, utilize the liquid crystal indicator of FFS (Fringe Field Switching) pattern etc. of edge (fringe) electric field also harmless.In addition, not only full penetrating type is used in fully-reflected type, that reflection penetrates the dual-purpose type liquid crystal indicator is also harmless.In addition, be not used in liquid crystal indicator, and be used in OLED display, the emission (field emission) escope also passable.
Claims (17)
1. power circuit is characterized in that possessing:
First electric charge through being connected in series transmits transistor and second electric charge transmits transistor;
First distribution provides to described first electric charge and transmits transistorized source electrode in order to will import current potential;
Output capacitor, it is connected in described second electric charge and transmits transistor drain; And
Flying capacitor, the terminal of one side is connected in described first electric charge transmission transistor AND gate, second electric charge via second distribution and transmits transistorized connected node, and is applied with clock frequency at the opposing party's terminal;
The resistance value of described first distribution is bigger than the resistance value of described second distribution.
2. power circuit according to claim 1 is characterized in that, the resistance value of described first distribution and second distribution is adjusted by the distribution width respectively.
3. power circuit according to claim 1 is characterized in that, possesses in order to described clock frequency is carried out the buffer circuit of wave shaping.
4. power circuit according to claim 1 is characterized in that, described flying capacitor is formed at described first electric charge transmission transistor and second electric charge and transmits on the identical substrate of transistor.
5. power circuit is characterized in that possessing:
First electric charge through being connected in series transmits transistor and second electric charge transmits transistor;
Tricharged through being connected in series transmits transistor and the 4th electric charge transmits transistor;
First distribution provides to described first electric charge and transmits transistor and tricharged transmits transistorized common source electrode in order to will import current potential;
Output capacitor, it is connected in, and described second electric charge transmits transistor and the 4th electric charge transmits transistorized common drain electrode;
First flying capacitor, the terminal of one side are connected in as described first electric charge transmission transistor AND gate, second electric charge via second distribution and transmit first connected node of transistorized connected node, and are applied with first clock frequency at the opposing party's terminal; And
Second flying capacitor, one square end is connected in as described tricharged transmission transistor AND gate the 4th electric charge via the 3rd distribution and transmits second connected node of transistorized connected node, and is applied with the second clock frequency anti-phase with described first clock frequency at the opposing party's terminal;
Described second connected node is connected in described first electric charge transmission transistor and second electric charge transmits transistorized grid, and described tricharged transmits transistor and the 4th electric charge transmits transistorized grid and described first connected node is connected in;
The resistance value of described first distribution is bigger than each resistance value of described second distribution and described the 3rd distribution.
6. power circuit according to claim 5 is characterized in that, the resistance value of described first distribution is that the resistance value than described second distribution and the 3rd distribution is high more than 1.5 times respectively.
7. power circuit according to claim 5 is characterized in that, the resistance value of described first distribution, second distribution and the 3rd distribution is adjusted by the distribution width respectively.
8. power circuit is characterized in that possessing:
First electric charge through being connected in series transmits transistor and second electric charge transmits transistor;
First distribution provides to described first electric charge and transmits transistorized source electrode in order to will import current potential;
Output capacitor, it is connected in described second electric charge and transmits transistor drain via the 4th distribution; And
Flying capacitor, the terminal of one side are connected in described first electric charge transmission transistor AND gate, second electric charge and transmit transistorized connected node via second distribution, and are applied with clock frequency at the opposing party's terminal;
The resistance value of described the 4th distribution is bigger than the resistance value of described second distribution.
9. power circuit according to claim 8 is characterized in that, the resistance value of described the 4th distribution and second distribution is adjusted by the distribution width respectively.
10. power circuit according to claim 8 is characterized in that, described flying capacitor is formed on described first electric charge transmission transistor and second electric charge and transmits on the identical substrate of transistor.
11. a power circuit is characterized in that possessing:
First electric charge through being connected in series transmits transistor and second electric charge transmits transistor;
Tricharged through being connected in series transmits transistor and the 4th electric charge transmits transistor;
First distribution provides to described first electric charge and transmits transistor and tricharged transmits transistorized common source electrode in order to will import current potential;
Output capacitor, it is connected in via the 4th distribution, and described second electric charge transmits transistor and the 4th electric charge transmits transistorized common drain electrode;
First flying capacitor, the terminal of one side are connected in via second distribution as described first electric charge transmission transistor AND gate, second electric charge and transmit first connected node of transistorized connected node, and are applied with first clock frequency at the opposing party's terminal; And
Second flying capacitor, the terminal of one side is connected in via the 3rd distribution as described tricharged transmission transistor AND gate the 4th electric charge and transmits second connected node of transistorized connected node, and is applied with the second clock frequency anti-phase with described first clock frequency at the opposing party's terminal;
Described second connected node is connected in described first electric charge transmission transistor and second electric charge transmits transistorized grid, and described tricharged transmits transistor and the 4th electric charge transmits transistorized grid and described first connected node is connected in;
The resistance value of described the 4th distribution is bigger than the resistance value of described second distribution and the 3rd distribution.
12. power circuit according to claim 11 is characterized in that, the resistance value of described the 4th distribution is that the resistance value than described second distribution and the 3rd distribution is high more than 2 times respectively.
13. power circuit according to claim 11 is characterized in that, the resistance value of described the 4th distribution, second distribution and the 3rd distribution is adjusted by the distribution width respectively.
14. a display device is characterized in that, possesses the described power circuit of claim 1.
15. display device according to claim 14 is characterized in that, described power circuit is formed on the glass substrate by the low-temperature polysilicon film transistor manufacture process.
16. a display device is characterized in that, possesses the described power circuit of claim 8.
17. display device according to claim 16 is characterized in that, described power circuit is formed on the glass substrate by the low-temperature polysilicon film transistor manufacture process.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-080918 | 2007-03-27 | ||
| JP2007080918A JP4642794B2 (en) | 2007-03-27 | 2007-03-27 | Power supply circuit and display device |
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| CN101277562A CN101277562A (en) | 2008-10-01 |
| CN101277562B true CN101277562B (en) | 2011-12-28 |
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| US (1) | US7675349B2 (en) |
| JP (1) | JP4642794B2 (en) |
| KR (1) | KR100942876B1 (en) |
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| KR101868144B1 (en) * | 2011-09-29 | 2018-06-18 | 엘지디스플레이 주식회사 | Display Device |
| US9634562B1 (en) * | 2016-06-09 | 2017-04-25 | Stmicroelectronics International N.V. | Voltage doubling circuit and charge pump applications for the voltage doubling circuit |
| US10333397B2 (en) | 2017-07-18 | 2019-06-25 | Stmicroelectronics International N.V. | Multi-stage charge pump circuit operating to simultaneously generate both a positive voltage and a negative voltage |
| US10050524B1 (en) | 2017-11-01 | 2018-08-14 | Stmicroelectronics International N.V. | Circuit for level shifting a clock signal using a voltage multiplier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1805285A (en) * | 2005-01-14 | 2006-07-19 | 凌阳科技股份有限公司 | Low voltage differential amplitude driver with high power supply noise suppression ratio |
| CN1885375A (en) * | 2005-06-20 | 2006-12-27 | 先锋株式会社 | Drive circuit and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6552712B1 (en) * | 1997-06-11 | 2003-04-22 | Seiko Epson Corporation | Semiconductor device, liquid crystal display, and electronic equipment including the same |
| JP2004146082A (en) | 2002-10-21 | 2004-05-20 | Semiconductor Energy Lab Co Ltd | Display device |
| KR100528545B1 (en) * | 2003-02-25 | 2005-11-15 | 매그나칩 반도체 유한회사 | Charge pump circuit |
| KR100562651B1 (en) * | 2003-10-30 | 2006-03-20 | 주식회사 하이닉스반도체 | Multi stage voltage pump circuit |
| JP4557577B2 (en) | 2004-03-26 | 2010-10-06 | 三洋電機株式会社 | Charge pump circuit |
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|---|---|---|---|---|
| CN1805285A (en) * | 2005-01-14 | 2006-07-19 | 凌阳科技股份有限公司 | Low voltage differential amplitude driver with high power supply noise suppression ratio |
| CN1885375A (en) * | 2005-06-20 | 2006-12-27 | 先锋株式会社 | Drive circuit and display apparatus |
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| Publication number | Publication date |
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| JP4642794B2 (en) | 2011-03-02 |
| TWI373698B (en) | 2012-10-01 |
| US7675349B2 (en) | 2010-03-09 |
| TW200839478A (en) | 2008-10-01 |
| US20080238535A1 (en) | 2008-10-02 |
| KR20080087736A (en) | 2008-10-01 |
| KR100942876B1 (en) | 2010-02-17 |
| JP2008245396A (en) | 2008-10-09 |
| CN101277562A (en) | 2008-10-01 |
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