200818109 九、發明說明： 【發明所屬之技術領域】 本發明係關於液晶顯示裝置，尤其是關於一種具備有 電源電路之液晶顯示裝置，該電源電路係產生用以控制像 素電晶體的導通（0N)或不導通（〇FF)的電源電位。 【先前技術】 以往，於利用低溫多晶矽TFT(Thin Film Transistor:薄膜電晶體）製程所製造的主動矩陣型液晶顯 不I置中，為了降低驅動Ic(積體電路）的成本，係在液晶 面板的TFT基板上形成有產生用以控制像素TFT的導通或 不導通之電源電位的電源電路。電源電路一言而言係使用 充電泵型的DC-DC變換器（converter)，並將分別使用於液 晶面板的水平移位暫存器、垂直移位暫存器的水平傳輸時 脈、垂直傳輸時脈予以使用作為其驅動訊號。 該種主動矩陣型液晶顯示裝置已揭示於專利文獻i 中。 (專利文獻1)日本特開2004-146082號公報 【發明内容】 (發明所欲解決之課題） 一 ^而 般而"由於水平傳輸時脈、垂直傳輸時脈的 振中田係J 1 3V左右’為了獲得用以使像素導通或不導 通的足夠電源電位，而必須進行+ 3倍昇壓、—2倍昇壓， 因此存在電源電路的電路規模變大之問題。 而且，將水平傳輸時脈、垂直傳輸時脈併用作為驅動 319489 5 200818109 電源電路用的訊號時，由於 時脈的放大器之驅動能力較小，7平傳輸時脈、垂直傳輪 設置緩衝電路，而有雷=所以有必要在了叮基板上 ’电路面稽、讎士 降之問題。 、 ’且笔源電路的效率下 再者，將水平傳輸時脈Μ 動訊號使用時，亦會有由於分頻時脈轉時=路的驅 而對顯示帶來不良影響之虞。 ）反轉蚪序⑴叫) 必要傳輪時脈或垂直傳輪時脈時，因常有 配線將該等時脈傳送到電源電路用的長 ⑶咖.^ 夜晶面板的框緣面積增大，或者在將 由^^Γglass ••玻璃覆晶）安裝在玻璃基板上等時， 再者有無法形成該種喊之情形。 自驅動ic的專用時脈時，有液晶面板的端 (解決課題的手段） 本發明之液晶顯示裝置係有鑑於上述的課題而研創 :、’該液晶顯示裝置係具備有：切換元件；經由該切換元 ^皮施加影像訊號之像素電極；被施加有反覆高位準與低 位準的共用電極訊號之共用電極；依據該共用電極及前述 $素電極之間的電場而被配向的液晶；以及產生用以控制 =述切換元件的切換的電源電位之電源電路，該液晶顯示 衣置之知'破為，前述電源電路係具備：第1及第2電荷傳 輸元件，係經串聯連接，並依據前述共用電極訊號互補性 地進行切換；以及第丨電容器，係結合於第丨及第2電荷 319489 6 200818109 傳輸兀件的連接點，並被施加有前述共用電極訊號。 此外，本發明的液晶顯示裝置係具備有形成在第工 二反土：：換元件;形成在前述第1基板上且經由前述切 、兀不施加影像訊號之像素電極；與前述第i基板相向 =置之：2基板；形成在前述第2基板上，且被施加有 準及低位準的共用電極訊號之共用電極；依據該 ，=極及前述像素電極之間的電場而被配向的液晶；以 =制前述切換元件的切換的電源電位之電源電 路該液:顯示裝置之特徵為，前述電源電路係具備：第 及弟2电何傳輸元件’係形成在前述第 上 聯連接；電容器，係具有第】端子及第 扳上且二串 子逵桩糾筮彳Ώ Μ π 愐卞及弟2知子，且第1端 及弟2電荷傳輪元件的連接點；緩衝電路， 述第7板上，且其輸出被施加在前述電容器 的弟2、子，以及輸入電容哭 鈐入嫂工“以 电谷係形成在前述緩衝電路的 輸為子與相對向之前述共用電極之間。 ，本發明的電源電路之特徵為具備：經串聯連接 罘1及弟2電荷傳輸元件；電容器，係具有第 端子m端子連接到第1及第2電荷 點；緩衝電路，其輸出被施加到前述電容器的第2牛=接 以及輪入電容器’係具有第3端子及第4端子端 子連接到前述缓衝電路的輸入端子，並 ：广 有時脈訊號。 而子被施加 (發明的效果） 根據本發明的液晶顯示袁置，由於利用了^電㈣ 319489 7 200818109 號作為電源電路的驅動訊號，所以只要作+ 2倍昇壓叫 倍升塵即足夠，而可將電源電路的電路規模縮小。再者， 輸出共用電極訊號的放大器之驅動能力較大，所以不需要 °又置緩衝1路’而可削減電路面積並提昇電路效率。而且， ί於共用電極訊號的反轉時序（從Η位準遷移到w準的時 和或從L位準遷移到Η位準的時序)係在水平返馳期間進 订，故亦具有不會對顯示帶來不良影響的優點。此外，供 應共用電極訊號的配線係設置在面板的整體外周，所以即 =電源電路配置在面板上的任何處，亦可湘該配線將 』電極訊號供應至電源電路’故也具有圖案佈局 限少的優點。 根據ί發明的液晶顯示裝置，由於利用輸入電 s : ^致之電痛合將共用電極訊號當作驅動時脈供應 電源電路’所以可減少驅動時脈用配線的圖案佈局之限 彳’且能防止液晶面板框緣面積的增大及端子數的增加。 再者，根據本發明的電源電路，由於利用電容器所導 =電容器輕合來接受驅動時脈的供應，所以可減少驅動 日禮用配線的圖案佈局限制，並能防止電路面積的增大。 【實施方式】 、 ^ ^下，一面參照圖式一面說明本發明的實施形態。 (弟1實施形態） 第1圖係顯示液晶面板100之圖。於TFT基板上形成 =驅動電路110、垂直驅動電路i2〇，並於顯示區域矩 陣式地配置有複數個像素（在第1圖僅顯示4像素）。水平 319489 8 200818109 驅動電路110係為根據水平傳輸時脈CKH而依序轉送水平 起動訊號的移位暫存器，並按照其輸出供應的影像訊 號至各資料線DL。垂直驅動電路120係為根據垂直傳輸時 脈m依序轉送垂直起動訊號的移位暫存器，並按照其輸 出供應閘極訊號至各閘極線GL。 由各像素的TFT所構成的像素電晶體GT的汲極係連接 到對應的資料線DL，像素電晶體Gτ係藉由閘極訊號控制 其導通或不導通。像素電晶體GT的源極係連接到像素電極 12卜此外，係與TFT基板相對向地設有對向基板，並於對 向基板上與像素電極121相對向地形成有共用電極M2。 於m基板與對向基板之間封入有液晶lc。如第之圖所 示，為了進行線反轉驅動，從液晶面板1〇〇的外部或設置 在液晶面板1〇0的TFT基板上的驅動iC2〇〇將於每一水平 期間反覆高⑻位準與低α)位準的共用電極訊號觀施 加至共用電極122。 當將像素電晶體GT設為W道型時，若閑極訊號變為 位準’像素電晶體GT即導通。藉此，影像訊號從資料線 DL經由像素電晶體_加到像素電極121，而藉由產生在 共用，極122與像素電極121之間的電場使液晶lc被配 向’藉此進行液晶顯示。 ；在此，由於共用電極訊號VC0M係反覆H位準與l位 ^所以像素電極121的電位會因為透過液晶LC的電容器 馬°而產生變動。因此，為了使像素電晶體GT導通，需要 有’、振巾胃兩倍的VGQMHx2之正電源電位作相極訊號的Η 319489 9 200818109 4準而為了使像素電晶體GT不導通，需要有其振幅負一 倍的VCOMHx-1之負電源電位作為閘極訊號的[位準。其 中’ VC0MH係在4. 5V左右。 為了產生上述閘極訊號，在液晶面板1 〇〇的TFT基板 上利用system-on-glass(簡稱S0G，即系統製作在玻璃面 板上）技術形成電源電路130,並將其輸出供應至垂直驅動 電路120。電源電路} 3〇係由：產生正電源電位的沉一此 變換器、以及產生負電源電位的DC_DC變換器所構成。在 本鲞明中，係使用共用電極訊號vc〇M作為該等變換 器的驅動訊號。 、 第3圖為顯示產生正電源電位的DC_DC變換器電路 圖二。經由設置在液晶面板100的輸入端子piN輸二共用電 極訊號则。所輸入的共用電極訊號_係經由緩衝電 路BF輸入到第丨飛馳電容器（flying 的一 侧端，以作為第1共用電極訊號vc〇M卜並將第i共用電 極訊號聰1經反轉的訊㈣為第2以電極訊號％⑽ 輸入到第2飛馳電容器u的—側端子。又，將n通道 何傳輸電晶體削及p通道㈣荷傳輸電晶體Μιρ :，且將第2飛馳電容器以的另一側端子連接至該等電曰 :的閑極。而且’騎道型電荷傳輸電晶體_及P: 道型電荷傳輸電晶體M2P串聯連接，且將第！㈣電容哭 mi側端子連接至該等電晶體的閑極。第1飛200818109 IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a power supply circuit for controlling conduction (0N) of a pixel transistor Or does not turn on (〇FF) the power supply potential. [Prior Art] Conventionally, active matrix liquid crystals manufactured by a low-temperature polysilicon TFT (Thin Film Transistor) process have been used, and in order to reduce the cost of driving Ic (integrated circuit), liquid crystal panels are used. A power supply circuit for generating a power supply potential for controlling conduction or non-conduction of the pixel TFT is formed on the TFT substrate. In principle, the power supply circuit uses a charge pump type DC-DC converter, and will be used for horizontal transmission of the liquid crystal panel, vertical shift register, horizontal transmission clock, vertical transmission. The clock is used as its drive signal. Such an active matrix type liquid crystal display device has been disclosed in Patent Document i. (Patent Document 1) Japanese Laid-Open Patent Publication No. 2004-146082 (Summary of the Invention) (The problem to be solved by the invention) is as follows: "When the horizontal transmission is transmitted, the clock of the vertical transmission is in the range of J 1 3V. In order to obtain a sufficient power supply potential for turning on or off the pixel, it is necessary to perform +3 times boosting and -2 times boosting, so that the circuit scale of the power supply circuit becomes large. Moreover, when the horizontal transmission clock and the vertical transmission clock are used as signals for driving the power circuit of 319489 5 200818109, since the driving ability of the amplifier of the clock is small, the 7-level transmission clock and the vertical transmission are provided with the buffer circuit. There is Ray = so it is necessary to have a problem with the circuit surface and the gentleman's drop on the 叮 substrate. </ br /> </ RTI> </ RTI> and the efficiency of the pen source circuit, when the horizontal transmission of the clock sway signal, there will be a negative impact on the display due to the frequency-dependent clock transition = road drive. ) Inverted sequence (1) is called) When it is necessary to transmit the clock or the vertical transmission clock, the length of the frame edge of the night crystal panel is increased due to the frequent wiring of the clock to the power supply circuit. Or when it is mounted on a glass substrate by ^^Γglass••glass flip-chip, etc., there is a case where such a shout cannot be formed. The liquid crystal display device of the present invention has been developed in view of the above-mentioned problems when the dedicated clock of the ic is driven by the dedicated clock of the ic. The liquid crystal display device includes: a switching element; a pixel electrode to which an image signal is applied; a common electrode to which a common electrode signal of a high level and a low level is applied; a liquid crystal to be aligned according to an electric field between the common electrode and the first element; and a generating In the power supply circuit for controlling the power supply potential of the switching element, the liquid crystal display device is broken, and the power supply circuit includes: the first and second charge transfer elements are connected in series, and are shared according to the foregoing The electrode signals are complementarily switched; and the second capacitor is coupled to the junction of the second and second charges 319489 6 200818109 to transmit the component and is applied with the aforementioned common electrode signal. Further, the liquid crystal display device of the present invention includes: a replacement electrode formed on the second surface of the second substrate; and a pixel electrode formed on the first substrate and not applying the image signal via the cutting or the splicing; and the ith substrate = 2: a substrate; a common electrode formed on the second substrate and having a common electrode signal with a quasi-low level; and a liquid crystal aligned according to an electric field between the pixel and the pixel electrode; A power supply circuit for controlling a switching power supply potential of the switching element. The liquid: display device is characterized in that the power supply circuit includes: a first and a second power transmission element is formed in the first connection; a capacitor a connection point having a first terminal and a first and a second string of 筮彳Ώ 筮彳Ώ π π 弟 and 2 2 知 子, and the first end and the second charge transfer member; the snubber circuit, the seventh board, and The output is applied to the second and second sub-capacitors of the capacitor, and the input capacitor is cried into the work. "The electric valley is formed between the input of the buffer circuit and the opposite common electrode." The power supply circuit is characterized in that: the capacitor is connected in series with the first and second charge transfer elements; the capacitor has a terminal m terminal connected to the first and second charge points; and the buffer circuit has an output applied to the second capacitor. The cow=connection and the wheel-in capacitor' have the third terminal and the fourth terminal which are connected to the input terminal of the snubber circuit, and have a wide pulse signal. The sub-application is applied (the effect of the invention) The liquid crystal according to the present invention Yuan set, because the use of ^ (4) 319489 7 200818109 as the drive signal of the power circuit, so as long as + 2 times the boost is enough to double the dust, but the circuit scale of the power circuit can be reduced. The amplifier with the common electrode signal has a large driving capability, so it is not necessary to set the buffer 1 channel to reduce the circuit area and improve the circuit efficiency. Moreover, the reverse timing of the common electrode signal (from the Η position to the w The quasi-time and the timing from the L-level to the Η level are ordered during the horizontal hopping period, so there is also an advantage that the display will not be adversely affected. The wiring of the electrode signal is disposed on the entire outer circumference of the panel, so that = the power supply circuit is disposed anywhere on the panel, and the wiring can supply the "electrode signal to the power supply circuit", so that the layout layout is limited. In the liquid crystal display device of the invention, since the common electrode signal is used as the driving clock supply power supply circuit by the input electric s: ^, the limitation of the pattern layout of the driving clock wiring can be reduced and can be prevented. Further, according to the power supply circuit of the present invention, since the power supply circuit of the present invention is used to receive the driving of the driving clock by the coupling of the capacitor and the capacitor, the wiring for driving the ceremonial wiring can be reduced. The pattern layout is limited, and the increase in the circuit area can be prevented. [Embodiment] An embodiment of the present invention will be described with reference to the drawings. (Brief 1 embodiment) Fig. 1 is a view showing a liquid crystal panel 100. The = drive circuit 110 and the vertical drive circuit i2 are formed on the TFT substrate, and a plurality of pixels are arranged in a matrix in the display region (only four pixels are displayed in Fig. 1). Level 319489 8 200818109 The drive circuit 110 is a shift register that sequentially transfers the horizontal start signal according to the horizontal transmission clock CKH, and outputs the supplied image signal to each data line DL according to the output. The vertical driving circuit 120 is a shift register for sequentially transferring the vertical start signal according to the vertical transfer clock m, and supplies the gate signal to each gate line GL according to the output. The drain of the pixel transistor GT formed by the TFTs of the respective pixels is connected to the corresponding data line DL, and the pixel transistor Gτ is controlled to be turned on or off by the gate signal. The source of the pixel transistor GT is connected to the pixel electrode 12, and a counter substrate is provided opposite to the TFT substrate, and a common electrode M2 is formed on the counter substrate opposite to the pixel electrode 121. A liquid crystal lc is sealed between the m substrate and the counter substrate. As shown in the figure, in order to perform the line inversion driving, the drive iC2 from the outside of the liquid crystal panel 1 or the TFT substrate provided on the liquid crystal panel 110 will repeat the high (8) level in each horizontal period. The common electrode signal view with the low α) level is applied to the common electrode 122. When the pixel transistor GT is set to the W-channel type, if the idler signal becomes a level, the pixel transistor GT is turned on. Thereby, the image signal is supplied from the data line DL to the pixel electrode 121 via the pixel transistor _, and the liquid crystal lc is aligned by the electric field generated between the common electrode 122 and the pixel electrode 121, thereby performing liquid crystal display. Here, since the common electrode signal VC0M overlaps the H level and the 1st position, the potential of the pixel electrode 121 fluctuates due to the capacitance of the capacitor passing through the liquid crystal LC. Therefore, in order to turn on the pixel transistor GT, it is necessary to have a positive power supply potential of VGQMHx2 twice as the phase of the vibrating towel. 319489 9 200818109 4 In order to make the pixel transistor GT non-conducting, it is necessary to have its amplitude. The negative power supply potential of VCOMHx-1 is doubled as the [level of the gate signal. 5伏左右。 The 'VC0MH is around 4. 5V. In order to generate the above-mentioned gate signal, the power supply circuit 130 is formed on the TFT substrate of the liquid crystal panel 1 by using a system-on-glass (referred to as SOG, that is, the system is fabricated on a glass panel) technology, and the output thereof is supplied to the vertical driving circuit. 120. The power supply circuit consists of a converter that generates a positive power supply potential and a DC_DC converter that generates a negative power supply potential. In the present specification, the common electrode signal vc〇M is used as the drive signal for the converters. Figure 3 shows the DC_DC converter circuit that produces a positive power supply potential. The common electrode signal is input via the input terminal piN provided in the liquid crystal panel 100. The input common electrode signal _ is input to the second flying capacitor (the side of the flying via the buffer circuit BF) as the first common electrode signal vc〇Mb and the i-th common electrode signal is inverted. (4) The second electrode signal %(10) is input to the -side terminal of the second flying capacitor u. Further, the n-channel transmission transistor is cut and the p-channel (four)-transmission transistor Μιρ: and the second flying capacitor is used. The other terminal is connected to the idle pole of the electric cymbal: and the 'riding-type charge transfer transistor _ and P: the territorial charge transport transistor M2P are connected in series, and the (4) capacitor crying mi side terminal is connected to The idle pole of the transistors. The first flight
Cl的另-側端子係連接到電荷傳輸電晶體削 輸電晶體M1P的連接點，而第2飛馳電 7專 奋态C2的另—側端 10 319489 200818109 子係連接到電荷傳輸電晶體M2N及電荷傳輸電晶體M2P的 連接點。 N通道型電荷傳輸電晶體Ml N、M2N的共通源極係施加 有共用電極訊號VC0M的Η位準之VC0MH。若不考慮電晶體 導致的電壓損失，則從Ρ通道型電荷傳輸電晶體Μ1Ρ、Μ2Ρ 的共通汲極會輸出兩倍VC0MH的VC0MHx2之正電源電位、 輸出電流lout ◦此外，Cout為平流用電容器，R為負載電 阻，垂直驅動電路120係對應於此負載電阻R。再者，電 f 荷傳輸電晶體係由TFT所構成。 參照第4圖的波形圖說明此DC-DC變換器的平常狀態 之動作。於第1共用電極訊號VC0M1為Η位準時，M1N、M2P 為不導通，M2N、M1P為導通，M1N與M1P的連接節點電位 VI被昇壓至VC0MHx2,其位準經由M1P被輸出。M2N與M2P 的連接節點電位V2被充電至VC0MH。其次，當第1共用電 極訊號VC0M1成為L位準時，MIN、M2P為導通，M2N、M1P 為不導通，電位V2被昇壓至VC0丽x2，其位準經由M2P被 輸出。電位VI被充電至VC0MH。亦即，從DC-DC變換器的 左右的串聯電晶體電路交替地輸出VC0MHx2。不過，在此 係忽略電晶體所導致的電壓損失。 根據此DC-DC變換器，可獲得適於使像素電晶體GT 導通用的VC0MHx2之電位。（設VC0MH=4. 5V，若忽略電壓 損失則為9. 0V)因此，變得不需要如以往的3倍昇壓，而 可縮小電路規模且能提高電路效率。再者，由於共用電極 訊號VC0M的反轉時序（從Η位準遷移到L位準的時序，或 11 319489 200818109 從L位準遷移到η位準的時序）係於水平返馳期間進行，故 不會對顯示帶來不良影響。而且，由於供應共用電極訊號 VC0M的配線係設置在液晶面板1〇〇的整個外周，所以即使 將電源電路130配置在液晶面板1〇〇的TFT基板上之任何 處，也可利用該配線將共用電極訊號冗⑽供應至電源電路 130，因此亦具有圖案佈局上之限制少的優點。 再者，在如上述例所示之於對向基板上相對向於像素 電極121形成共用電極122的液晶顯示裝置中，當將第玉 及第2飛馳電容器^、以形成在液晶面板1〇〇上由於 第1飛馳電容器C1的電位變動與對向基板上的共用電極之 電2變動係與共用電極訊號咒⑽形成同電位，所以可防止 因第1飛馳電容器C1所進行的電容分壓所導致的效率下 另一方面，在如 FFS(FieldFringeswitching;邊緣 %切換）方式或IPS(In_plane_Switching;平面切換）方式 將：素電極與共用電極形成在同一基板上的液晶顯示裝置 =情形中，纟於在對向基板沒有電極，所以不會產生電位 文動因此，根據本發明的構成，無論在任何一種方式的 液曰一曰頭不I置中’均可實現不會產生效率下降的良好液晶 顯示裝置。 (第2實施形態） 第5圖係顯不產生正電源電位的Dc—此變換器電路 圖°於該DC-DC變換器中’由於用以輪出共用電極訊號職 j驅動IC200側之放大器'的驅動能力大，所以削除了緩衝 電路BF。如此一來，可削減電路面積，且能提高電路效率。 319489 12 200818109 再者ΰ又成為，削除第2飛馳電容器C2，並僅對第1飛馳 電容器C1施加共用電極訊號VC0M。 兒月此DC DC變換器平常狀態的動作。於共用電極訊 5虎VC0M為H位準時’ M1N、M2p不導通，謂、導通， 则與M1P的連接節點之電位皮昇壓jl VC0MHx2，其位 準I由M1P被輪出。M2N與M2p的連接節點之電位π被充 電至VC0MH。其：：欠，當共用電極訊號vc〇M變成l位準時， M1N12P導通，M2N、Mlp不導通。由於M2p導通，電位 V2係因來自輸出側的電荷移動而被充電至VC0MHX2。因 此，根據此DC-DC變換器，共用電極訊號vc〇M僅於H位 時進行昇壓動作。 上根據此DC-DC變換器，更可削減電路面積，並提高電 路效率。再者’在第2實施形態中，於對向基板上對向於 像素電極121而形成有共用電極122的液晶顯示裝置中， 由於Ϊ液曰曰面板1〇0上僅形成第1飛馳電容器C1 ,所以較 上述第1貫施形態者更能防止因電容分壓所導致的效率下 、至於其他的構成係與第i實施形態的電路相同，而可 獲件相同效果。 (弟3實施形態） 第6圖係顯示產生正電源電位的DC_D(：變換器電路 圖。於該DC_DC變換器中，與第2實施形態相同，削 :衝電路BF，不過設置有第2飛，馳電容器C2，且設置有將 /、用電極訊號VC0M予以反轉並施加到第2飛馳電容哭a 319489 13 200818109 的反相器m。在此，第2飛桃電容器C2的電容 1飛馳電容器C1的電容值小A啻$认甘凡 ^錄其他的構成係與第 2貝鈿形m的電路相同，而可獲得相同效果。 (第4實施形態） 在第1至第3實施形態中係顯示產生正電源電位的 DC-DC變換器，而在本實施形態中係就產生負電源電位的 匕C-DC變換器加以說明。如第7圖所示，於此職變換 器中，將共用電極訊號VC0M施加至第i飛馳電容哭U，、 並將共用電極訊號VC0M的反轉訊號施加至第2飛秘電容器 C2在M1P與M2P的共通源極施加接地電位，且 從Μ1N與M2N的共通汲極獲得將vc〇M乘上負一倍的vc〇Mx 電位如此來，可作成適於用以使像素電晶體gt =導通的閘極訊號。因此，不需要如習知進行_2倍的昇 【而可縮小電路規模並能提高電路效率。至於其他的效 果係與第1至第3實施形態的效果一樣。 就此DC-DC變換器的動作予以說明，於共用電極訊號 VCOM為Η位準時，M1N、M2p不導通，M2N、Mip導通，min 的連接筇點之電位V3被充電至Vss，M2N與M2P的 連接節點之電位V4下降至VCOMHx-1的電位，且其電位經 由M2N被輸出。 冨用電極5孔號VCOM變成L位準時，M1N、M2P導通’ M2N、M1P不導通，電位V3降至VCOMHx-1，且其位準經由 M1N被輸出。電位V4被充電至Vss，亦即，從DC-DC變換 器的左右的串聯電晶體電路交替地輸出VCOMHx-1的電 319489 14 200818109 損失不加考慮 位。不過，電晶體所導致的電壓 (第5實施形態） 在本貝施开/悲中，使用共用兰^ ^ ^ ^ ^ 改Π0的Ι)Γ ΠΓ%拉汛唬VC0M作為電源電 路^的DC-DC交換器的驅動訊號這點雖與第^ 施形恶相同，但將共用電極訊铲 貝 电往Λ說VC0M經由輪入雷交鈐 | DC-DC變換器這點相異。 私合輸入到 第8圖係顯示產生正電源電位的DC-DC變換哭電路 圖。為了整形驅動時脈的波形，於dc_dc變換器:時脈輸 入部設有前段緩衝電路131、後& g n 剧 俊蚊綾衝電路132，並在前段 緩衝電路131的輸入端子I”盥丘 用電極122之間形成有 輸入電谷器C i η。别段緩衝電路13】孫由The other side terminal of Cl is connected to the connection point of the charge transporting transistor M1P, and the other side of the second flying circuit 7 is 319489. The 200818109 subsystem is connected to the charge transporting transistor M2N and the charge. The connection point of the transmission transistor M2P. The common source of the N-channel type charge transfer transistors M1 N, M2N is applied with VC0MH of the common electrode signal VC0M. If the voltage loss caused by the transistor is not considered, the common drain potential of VC0MHx2 of twice VC0MH is output from the common drain of the channel-type charge transfer transistors Μ1Ρ, Μ2Ρ, and Cout is a capacitor for advection. R is a load resistor, and the vertical drive circuit 120 corresponds to the load resistor R. Furthermore, the electrical f-charge transmission electron crystal system is composed of TFTs. The operation of the normal state of this DC-DC converter will be described with reference to the waveform diagram of Fig. 4. When the first common electrode signal VC0M1 is clamped, M1N and M2P are non-conducting, M2N and M1P are turned on, and the connection node potential VI of M1N and M1P is boosted to VC0MHx2, and the level is output via M1P. The connection node potential V2 of M2N and M2P is charged to VC0MH. Next, when the first shared electrode signal VC0M1 is at the L level, MIN and M2P are turned on, M2N and M1P are turned off, the potential V2 is boosted to VC0 丽 x2, and the level is output via M2P. The potential VI is charged to VC0MH. That is, VC0MHx2 is alternately outputted from the left and right series transistor circuits of the DC-DC converter. However, the voltage loss caused by the transistor is ignored here. According to this DC-DC converter, the potential of VC0MHx2 suitable for making the pixel transistor GT common can be obtained. (Set VC0MH = 4. 5V, if the voltage loss is neglected, it is 9. 0V) Therefore, it is not necessary to increase the circuit scale as much as 3 times, and the circuit efficiency can be improved. Furthermore, due to the inversion timing of the common electrode signal VC0M (the timing from the Η level to the L level, or the timing of the 11 319 489 200818109 transition from the L level to the η level) is performed during the horizontal flyback period, Will not adversely affect the display. Further, since the wiring for supplying the common electrode signal VC0M is provided on the entire outer circumference of the liquid crystal panel 1 ,, even if the power supply circuit 130 is disposed anywhere on the TFT substrate of the liquid crystal panel 1 , the wiring can be shared by the wiring. The electrode signal redundancy (10) is supplied to the power supply circuit 130, and therefore has the advantage of less restriction on the pattern layout. Further, in the liquid crystal display device in which the common electrode 122 is formed on the counter substrate opposite to the pixel electrode 121 as shown in the above example, the jade and the second flying capacitor are formed on the liquid crystal panel 1A. Since the potential fluctuation of the first flying capacitor C1 and the electric 2 fluctuation of the common electrode on the counter substrate form the same potential as the common electrode signal (10), the capacitance division by the first flying capacitor C1 can be prevented. On the other hand, in the case of a liquid crystal display device in which the element electrode and the common electrode are formed on the same substrate as in the FFS (Field Fringe Switching) or IPS (In_plane_Switching) mode, the situation is Since there is no electrode in the counter substrate, no potential motion is generated. Therefore, according to the configuration of the present invention, a liquid crystal display device which does not cause a decrease in efficiency can be realized regardless of the liquid helium head in any of the modes. . (Second Embodiment) Fig. 5 shows Dc which does not generate a positive power supply potential. This converter circuit diagram is used in the DC-DC converter because of the 'amplifier for driving the IC 200 side of the common electrode signal'. The drive capability is large, so the buffer circuit BF is removed. In this way, the circuit area can be reduced and the circuit efficiency can be improved. 319489 12 200818109 Furthermore, the second flying capacitor C2 is removed, and the common electrode signal VC0M is applied only to the first flying capacitor C1. The action of this DC DC converter in the normal state. In the common electrode signal 5 tiger VC0M is H-bit punctuality ' M1N, M2p is not conducting, said, conduction, then the potential node of the connection node with M1P boosts jl VC0MHx2, its level I is rotated by M1P. The potential π of the connection node of M2N and M2p is charged to VC0MH. Its:: Under, when the common electrode signal vc〇M becomes l-level, M1N12P is turned on, and M2N and Mlp are not turned on. Since M2p is turned on, the potential V2 is charged to VC0MHX2 due to the movement of charges from the output side. Therefore, according to this DC-DC converter, the common electrode signal vc 〇 M is boosted only when it is at the H position. According to this DC-DC converter, the circuit area can be reduced and the circuit efficiency can be improved. In the second embodiment, in the liquid crystal display device in which the common electrode 122 is formed on the counter substrate opposite to the pixel electrode 121, only the first flying capacitor C1 is formed on the sputum panel 1〇0. Therefore, it is possible to prevent the efficiency due to the capacitance division from being higher than that of the first embodiment, and the other components are the same as those of the circuit of the i-th embodiment, and the same effect can be obtained. (Embodiment 3) FIG. 6 shows a DC_D (inverter circuit diagram) for generating a positive power supply potential. In the DC-DC converter, as in the second embodiment, the rushing circuit BF is cut, but the second flying is provided. The capacitor C2 is provided with an inverter m for inverting the electrode signal VC0M and applying it to the second flying capacitor cries a 319489 13 200818109. Here, the capacitance 1 of the second flying peach capacitor C2 scatters the capacitor C1 The capacitance value is small, and the other components are the same as the circuit of the second bellows m, and the same effect can be obtained. (Fourth Embodiment) In the first to third embodiments, the display is performed. A DC-DC converter that generates a positive power supply potential is described. In the present embodiment, a 匕C-DC converter that generates a negative power supply potential is described. As shown in Fig. 7, in this service converter, a common electrode is used. The signal VC0M is applied to the ith flying capacitor crying U, and the reverse signal of the common electrode signal VC0M is applied to the second flying capacitor C2. The ground potential is applied to the common source of M1P and M2P, and the common Μ1N and M2N are used. Extremely get the vc〇Mx potential multiplied by vc〇M It can be made into a gate signal suitable for turning on the pixel transistor gt =. Therefore, it is not necessary to perform a _2-fold increase as in the prior art [which can reduce the circuit scale and improve the circuit efficiency. As for other effects and The effects of the first to third embodiments are the same. The operation of the DC-DC converter will be described. When the common electrode signal VCOM is in the Η position, M1N and M2p are not turned on, M2N and Mip are turned on, and the potential of the connection point of min is V3 is charged to Vss, the potential V4 of the connection node of M2N and M2P drops to the potential of VCOMHx-1, and its potential is output via M2N. When the electrode 5 hole number VCOM becomes L level, M1N, M2P conducts 'M2N, M1P is not turned on, potential V3 falls to VCOMHx-1, and its level is output via M1N. Potential V4 is charged to Vss, that is, VCOMHx-1 is alternately output from the left and right series transistor circuits of the DC-DC converter. Electricity 319489 14 200818109 Loss is not taken into account. However, the voltage caused by the transistor (5th embodiment) is used in this Becker open/sad, using the common blue ^ ^ ^ ^ ^ Π 0 Ι) Γ ΠΓ% Pulling VC0M as the DC-DC converter of the power supply circuit ^ Although this actuating signals applied to the first ^ evil the same shape, but the common electrode to electrically Λ inquiry blade shell via said VC0M cross seal wheel into Ray | DC-DC converter that different points. The private input is shown in Figure 8 to show the DC-DC conversion crying circuit diagram that produces the positive power supply potential. In order to shape the waveform of the driving clock, the dc_dc converter: the clock input portion is provided with a front buffer circuit 131, a rear & gn drama coil circuit 132, and is used at the input terminal I" of the front buffer circuit 131. An input electric grid C i η is formed between the electrodes 122. Another section of the buffer circuit 13]
可电格丄係串聯連接複數個CMOS 反相器INV1、INV2、···而構成。 、CMOS反相器INn、INV2、...係如第9圖所示，由p 通道型電晶體與N通道型電晶體所構成，並於？通道型電 晶體的源極施加有正電源電位PVDD，於1^通道型電晶體施 加有接地電位PVSS(〇V)。？通道型電晶體及N通道=電曰^ 體係由TFT所形成。 輸入電容Cin的構造係顯示於第1〇圖。第1〇圖係液 晶面板100的局部剖面圖，前段緩衝電路13ι的輸入端子 133係形成在TFT玻璃基板1〇上。輸入端子133係由鋁等 金屬層形成，並由絕緣膜11所覆蓋。在TFT玻璃基板1〇 上配置有對向玻璃基板2〇並於其間夾置液晶lc。 亦即，輸入電容器Cin係為將輸入端子133作為一方 的電容電極、並將形成在對向玻璃基板2〇上的共用電極 319489 15 200818109 作為另一方電容電極、且將絕緣膜11與液晶LC作為 電容絕緣膜的電容器。依據電源電路130的配置位置，亦 可在輸^入端子133與共用電極122之間介設用以密封液晶 LC的松封樹月旨12。在此情形下，密封樹脂12係成為電容 絕緣膜的一部分。 藉由作成上述構成，由於輸入電容器Cin的耦合作 用，與共用電極訊號·Μ同步的訊號係被輸入至輸入端子 ,133。由於不需要用以供應共用電極訊號vc⑽的長配線， 而且，共用電極訊號VC0M可從形成在對向玻璃基板2〇大 致整個的共用電極122取出，故圖案佈局的限制也較少。 再者由於利用了共用電極訊號VC0M，所以亦可防止液晶 面板的端子數增加。 前段緩衝電路131的第1段CMOS反相器ΙΝΠ係具有 寄生輸入電容CP(主要為P通道型電晶體與N通道型電晶 體的閘極電容）。因此，被輸入到輸入端子133的訊號之電 、位因寄生輸入電容Cp與輸入電容器cin的電容分壓而衰減 其對應份。 因此，輸入電容器Cin的電容值較宜設成較寄生輸入 電谷Cp足夠地大者。例如，於前述電晶體尺寸為w几= = 時，以設定成Cin>〇.5F為宜。為了加大輸入電 容器Cin的電容值，只要將輪入端子133的平面性圖案尺 寸設計成較大即可。 同步於被輸入到輸入端子133的共用電極訊號冗⑽ 之驅動時脈係經由前段緩衝電路131及後段緩衝電路i32 319489 16 200818109 被輸入到第i㈣電容㈣的—方端子以作為第！驅動時 脈CPCLK，且被輸入到第2飛馳電容器以的一方端子而 為將第1驅動時脈CPCLK反轉後之第2驅動時脈xcpcLK。 第1驅動時脈CPCLK及第2驅動時脈xcpcu雖為逆相的日士 脈，但該等時脈的振幅為PVDD。 守 、、於充電泵部中，N通道型的電荷傳輪電晶體賴 通道型電荷傳輸電晶體MP1為串聯連接，且在該等電晶體 ，的閘極連接有第2飛馳電容器以白勺另一方端子。再者曰曰，N 通道型的電荷傳輸電晶體齡與p通道型電荷傳輪電晶體 MP2為串聯連接，且在該等電晶體的閘極連接有第工θ 電容器C1的另-方端子。第1飛馳電容器Cl的另—方端 子係連接於電荷傳輸電晶體MN1與電荷傳輸電晶體的 連接點，第2飛馳電容器⑽另—方端子係連接於 輸電晶體MN2與電荷傳輸電晶體MP2的連接點。 N通遏型的電荷傳輸電晶體丽卜丽2的共通源極係施 i加有電源電位PVDD。若忽略電晶體所導致的電壓損失'，、則 從p通道型電荷傳輸電晶體MP丨、MP2的共通汲極輸出 的兩倍之2PVDD正電源電位及輸出電流Ivpp，以作為輸出 電位VPP。此外’於p通道型電荷傳輸電晶體肝卜^的 ^汲極連接有平流用電容器C3。再者，電荷傳輸電晶體 係由TFT所形成。 參照第11圖的波形圖說明此DC-DC變換器的平常狀能 動作。於第1驅動時脈CPCLK為Η位準（PVDD>f，顧 不導通，MN2、MP1 *通，腿與MP1的連接節點的電位η 319489 17 200818109 係藉由第1飛馳電容器C1的電容耦合而被昇壓至_， 亚經由刪輸出該位準。聰與MP2的連接節點 被充電至PVDD。 接者田弟1驅動時脈CPCLK下降至乙位 MN1、MP2 導通，龍？、MP1 尤遒^ 馳雪一Γ9 導通’電位V2係藉由第2飛 一合时的電容耦合而被昇壓至2pvDD，並經由脱2輸 。位準。電位V1被充電至_D。亦即，從DC—DC變換 器左右的$聯電晶體電路交替地輪出2ρ_。 、 體所導致的電壓損失未予考慮。 (弟6實施形態） 其次，就使用輸入電容器Cin之產生負電源電位的 =-DC變換—器加以說明。如第12圖所示，於該π—%變換 益中’與第5實施形態的電路相同，可獲得同步於被輸入 到輸，端子133的共用電極訊號聰之驅動時脈，並達到 相同效果。驅動時脈係經由前段緩衝電路13〗及後段緩衝 電路132被輸人到第！㈣電容器⑴的—方端子以作為 第1驅動時脈CPCLK，並被輸入到第2飛馳電容器ci2的 一方端子以作為第2驅動時脈XCPCLK。 、、於充電泵部中，N通道型的電荷傳輸電晶體随與？ 通道型電荷傳輸電晶體MP1丨雖串聯連接，但肝丨1與肝u =共通源極係施加有接地電位pvss之點，係與第5實施形 態的電路不同，而從丽11與膽12的共通汲極獲得將觸 予以乘上-1倍的_PVDD電位。再者，在顧丨卜顧12的共通 汲極連接有平流用電容器C13。 319489 18 200818109 參照第13圖就此DC-DC變換器的動作予以說明。在第 1驅動時脈CPCLK為Η位準（PVDD)時，㈣n、奶2為不導 通，MN12、MP11為導通’MN11與MP11的連接節點之電位 V3被充電至PVSS，MN12與MP12的連接節點之電位y4係 下降至-PVDD，並經由MN12輸出其電位。 當第1驅動時脈CPCLK成為L位準（pvss)時，丽〗1、 MP12為導通，^^、肝丨丨為不導通，電位v3下降至_pv⑽， 且其位準經由MN11被輸出。電位^被充電至Μ%。也就 是說，從負電源產生電路左右的串聯電晶體電路 出-PVDD電位。 再者，只要DC—DC變換器若為利用飛馳電容器及電荷 傳，元件來轉換輸出輸入電位的電路的話，則不限定於上 述實施形態的電路’亦可將其變形，或使用其他型態的電 路。再者，DC-DC變換器的前段緩衝電路13卜後段緩衝電 路^並不限定實施形態者’亦可將其變形，或使用其他 里先、的'緩衝電路。更且’緩衝電路亦可共用於產生正電位 的DC DC ’又換态、產生負電位的沉—沉變換器。 【圖式簡單說明】 第1圖係顯示本發明第1實施形態的液晶顯示裝置之 電路圖。 ^ 第2圖係本發明第1實施形態的液晶顯示裝置之動作 波形圖。 勃作 弟3圖係本發明第1實施形態的DC—DC變換器之電 圖。 319489 19 200818109 第4圖係本發明第丄施例形態的Dc— 作波形圖。 m% 第5圖係本發明第2實施形態的DC_Dc變換哭 圖。 -〜兔略 第6圖係本發明第3實施形態的DC-DC變換器之電路 圖0 第7圖係本發明第4實施形態的DC-DC變換器之電路 圖。 第8圖係本發明第5實施形態的DC-DC變換器之電路 圖〇The electrical grid is connected in series to a plurality of CMOS inverters INV1, INV2, . The CMOS inverters INn, INV2, ... are composed of a p-channel type transistor and an N-channel type transistor as shown in Fig. 9, and ? The source of the channel type transistor is applied with a positive power supply potential PVDD, and a ground potential PVSS (〇V) is applied to the channel type transistor. ? The channel type transistor and the N channel = 曰^ system are formed by TFTs. The structure of the input capacitor Cin is shown in the first diagram. The first drawing is a partial cross-sectional view of the liquid crystal panel 100, and the input terminal 133 of the front-stage buffer circuit 13i is formed on the TFT glass substrate 1A. The input terminal 133 is formed of a metal layer such as aluminum and is covered by the insulating film 11. The opposite glass substrate 2 is placed on the TFT glass substrate 1A with the liquid crystal lc interposed therebetween. In other words, the input capacitor Cin has the input terminal 133 as one of the capacitor electrodes, and the common electrode 319489 15 200818109 formed on the opposite glass substrate 2 is the other capacitor electrode, and the insulating film 11 and the liquid crystal LC are used. Capacitor for capacitor insulation film. Depending on the arrangement position of the power supply circuit 130, a sealing layer 12 for sealing the liquid crystal LC may be interposed between the input terminal 133 and the common electrode 122. In this case, the sealing resin 12 is a part of the capacitor insulating film. With the above configuration, the signal synchronized with the common electrode signal Μ is input to the input terminal 133 by the coupling effect of the input capacitor Cin. Since the long wiring for supplying the common electrode signal vc(10) is not required, and the common electrode signal VC0M can be taken out from the entire common electrode 122 formed on the opposite glass substrate 2, the layout of the pattern is less restricted. Further, since the common electrode signal VC0M is utilized, the number of terminals of the liquid crystal panel can be prevented from increasing. The first stage CMOS inverter of the front stage buffer circuit 131 has a parasitic input capacitance CP (mainly a gate capacitance of a P channel type transistor and an N channel type transistor). Therefore, the electric power of the signal input to the input terminal 133 is divided by the parasitic input capacitance Cp and the capacitance of the input capacitor cin to attenuate the corresponding portion. Therefore, the capacitance value of the input capacitor Cin is preferably set to be sufficiently larger than the parasitic input electric valley Cp. For example, when the crystal size is w == =, it is preferable to set Cin > 〇.5F. In order to increase the capacitance value of the input capacitor Cin, the planar pattern size of the wheel-in terminal 133 may be designed to be large. The driving clock synchronized with the common electrode signal redundancy (10) input to the input terminal 133 is input to the - terminal of the i-th (fourth) capacitor (four) via the front-stage buffer circuit 131 and the rear-stage buffer circuit i32 319489 16 200818109 as the first! The drive circuit CPCLK is input to one terminal of the second flying capacitor and is the second drive clock xcpcLK after inverting the first drive clock CPCLK. The first drive clock CPCLK and the second drive clock xcpcu are inverse phase Japanese pulses, but the amplitudes of the clocks are PVDD. In the charge pump unit, the N-channel type charge transfer transistor-based channel-type charge transfer transistor MP1 is connected in series, and in the transistors, the gate is connected to the second flying capacitor to be another One terminal. Further, the N-channel type charge transfer transistor is connected in series with the p-channel charge transfer transistor MP2, and the other terminal of the θ capacitor C1 is connected to the gate of the transistors. The other terminal of the first flying capacitor C1 is connected to the connection point of the charge transfer transistor MN1 and the charge transfer transistor, and the other terminal of the second flying capacitor (10) is connected to the connection of the power transmission crystal MN2 and the charge transfer transistor MP2. point. The common source of the N-conductor charge transfer transistor Ripley 2 is supplied with a power supply potential PVDD. If the voltage loss caused by the transistor is ignored, the 2PVDD positive power supply potential and the output current Ivpp are twice as the output potential VPP from the common drain output of the p-channel type charge transfer transistors MP丨 and MP2. Further, a drain capacitor C3 is connected to the drain of the p-channel type charge transfer transistor. Further, the charge transporting transistor is formed of a TFT. The normal-state operation of this DC-DC converter will be described with reference to the waveform diagram of Fig. 11. The first driving clock CPCLK is at the Η level (PVDD>f, and the MN2, MP1* is connected, and the potential η 319489 17 200818109 of the connection node between the leg and the MP1 is capacitively coupled by the first flying capacitor C1. It is boosted to _, and the output is outputted by sub-distribution. The connection node of Satco and MP2 is charged to PVDD. The receiver Tianshi 1 drives the clock CPCLK to drop to the MN1, MP2, and the ?1, MP1 遒^ Chichi 9 turns on 'potential V2' is boosted to 2pvDD by the capacitive coupling of the second fly-in and the second pass, and is turned off. The potential V1 is charged to _D. That is, from DC- The DC circuit of the left and right DC converters alternately rotates 2ρ_. The voltage loss caused by the body is not considered. (Embodiment 6) Next, the input capacitor Cin is used to generate the negative power supply potential =-DC conversion. As shown in Fig. 12, in the π-% conversion benefit, as in the circuit of the fifth embodiment, the driving clock of the common electrode signal Cong, which is input to the input terminal 133, can be obtained. And achieve the same effect. Drive the clock system via the front section buffer circuit 13 The rear-stage buffer circuit 132 is input to the terminal of the (fourth) capacitor (1) as the first drive clock CPCLK, and is input to one terminal of the second flying capacitor ci2 as the second drive clock XCPCLK. In the charge pump unit, the N-channel type charge transfer transistor is connected in series with the channel-type charge transfer transistor MP1丨, but the point of the ground potential pvss is applied to the liver 丨1 and the liver u=common source system. In the circuit of the fifth embodiment, the _PVDD potential obtained by multiplying the touch by a factor of -1 is obtained from the common drain of the MN11 and the biliary 12. Further, the common drain of the Gurubu 12 is connected to the advection. Capacitor C13 319489 18 200818109 The operation of this DC-DC converter will be described with reference to Fig. 13. When the first driving clock CPCLK is at the Η level (PVDD), (4) n, milk 2 is non-conductive, and MN12 and MP11 are turned on. The potential V3 of the connection node of MN11 and MP11 is charged to PVSS, and the potential y4 of the connection node of MN12 and MP12 is lowered to -PVDD, and its potential is output via MN12. When the first driving clock CPCLK becomes the L level (pvss) ), Li 〗 1, MP12 is conductive, ^^, liver 丨For non-conduction, the potential v3 drops to _pv(10), and its level is output via MN11. The potential ^ is charged to Μ%. That is, the series-transistor circuit from the negative power supply generating circuit outputs the -PVDD potential. As long as the DC-DC converter is a circuit that converts the output input potential by using a flying capacitor and a charge transfer, the circuit of the above-described embodiment is not limited to being deformed, or a circuit of another type is used. Further, the front-stage buffer circuit 13 of the DC-DC converter is not limited to the embodiment, and may be modified or used in other snubber circuits. Furthermore, the 'snubber circuit can also be used in common to generate a positive potential DC DC' which is in a state of change and produces a negative potential sink-sink converter. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a liquid crystal display device according to a first embodiment of the present invention. Fig. 2 is a waveform chart showing the operation of the liquid crystal display device of the first embodiment of the present invention. The diagram of the DC-DC converter according to the first embodiment of the present invention is shown in Fig. 3. 319489 19 200818109 Fig. 4 is a waveform diagram of Dc of the embodiment of the present invention. M% Fig. 5 is a DC_Dc conversion crying diagram according to the second embodiment of the present invention. - Figure 5 is a circuit diagram of a DC-DC converter according to a fourth embodiment of the present invention. Fig. 0 is a circuit diagram of a DC-DC converter according to a fourth embodiment of the present invention. Figure 8 is a circuit diagram of a DC-DC converter according to a fifth embodiment of the present invention.
第9圖係本發明第5實施形態的DC—DC變換器之吁 緩衝電路的電路圖。 & X 第10圖係顯示輪入電容器的構造之剖面圖。 第11圖係顯示本發明第5實施形態的DC—阢變 作之波形圖。 、 第12圖係本發明第6實施形態的DC—DC變換器之電路 作之:：係顯示本發明第6實施形態的™臭器動Fig. 9 is a circuit diagram of a snubber circuit of a DC-DC converter according to a fifth embodiment of the present invention. & X Figure 10 is a cross-sectional view showing the construction of a wheel-in capacitor. Fig. 11 is a waveform diagram showing a DC-阢 variation of the fifth embodiment of the present invention. Fig. 12 is a circuit diagram of a DC-DC converter according to a sixth embodiment of the present invention.
Li 要元件符號說明 10 TFT玻璃基板 12 密封樹脂 100 液晶面板 120 垂直驅動電路 Π 絕緣膜 20 對向玻璃基板 110 水平驅動電路 121 像素電極 319489 20 200818109Li Element Symbol Description 10 TFT Glass Substrate 12 Sealing Resin 100 Liquid Crystal Panel 120 Vertical Driving Circuit Π Insulating Film 20 Counter Glass Substrate 110 Horizontal Driving Circuit 121 Pixel Electrode 319489 20 200818109
122131 133 BF C2、 Cin DL GT INV MIN、 M1P、 MN1 ^ MP卜R 共用電極 前段緩衝電路 輸入端子 緩衝電路 130電源電路 132 後段 又、、是衝電路 〇 0 驅動I cci 、 cii 第 1 # 馬也電容哭 C12第2飛馳電容器 飛馳電 輸入電容器 Γ 、 平流用電容器 資料線 Tout平流用電容器 像素電晶體 閘極線 LL 液晶 反相器 IMiM2N N通道型電荷傳輪電晶：V2、..._S反相器 M2P P通道型電荷傳輪電晶體 MN2 、丽11 、 MN12 MP2 、 MP11 、 MP12 負載電阻 N通道型電荷傳輸電晶體 P通道型電荷傳輸電晶體 VC0M共用電極訊號 319489122131 133 BF C2, Cin DL GT INV MIN, M1P, MN1 ^ MP Bu R common electrode front snubber circuit input terminal snubber circuit 130 power supply circuit 132 rear stage, rush circuit 〇0 drive I cci , cii 1 # 马Capacitor crying C12 2nd flying capacitor flying speed electric input capacitor Γ, advection capacitor data line Tout advection capacitor pixel transistor gate line LL liquid crystal inverter IMiM2N N channel type charge transfer electric crystal: V2,..._S anti Phaser M2P P channel type charge transfer transistor MN2, MN11, MN12 MP2, MP11, MP12 load resistor N channel type charge transfer transistor P channel type charge transfer transistor VC0M common electrode signal 319489