JP2008225435A - Liquid crystal display device and power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale of a power supply circuit in a liquid crystal display device and increase the circuit efficiency. <P>SOLUTION: The power supply circuit 130 is formed on a TFT substrate of a liquid crystal panel 100 and an output from the power supply circuit 130 is supplied to a vertical drive circuit 120. The power supply circuit 130 is composed of a DC-DC converter for generating positive power supply potential and a DC-DC converter for generating negative power supply potential. These DC-DC converters are driven by a common electrode signal VCOM. An output from the DC-DC converter generating the positive power supply potential becomes VCOMH×2 and an output from the DC-DC converter generating the negative power supply potential becomes VCOMH×-1, so that potential levels suitable for turning on and off a pixel transistor can be obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device including a power supply circuit that generates a power supply potential for controlling on / off of pixel transistors.

  Conventionally, in an active matrix type liquid crystal display device manufactured by a low-temperature polysilicon TFT (Thin Film Transistor) process, on / off of the pixel TFT is controlled on the TFT substrate of the liquid crystal panel in order to reduce the cost of the drive signal IC. Therefore, a power supply circuit for generating a power supply potential for the purpose has been formed. Generally, a charge pump type DC-DC converter is used as a power supply circuit, and a horizontal transfer clock and a vertical transfer clock respectively used for a horizontal shift register and a vertical shift register of a liquid crystal panel are used as drive signals.

This type of active matrix type liquid crystal display device is described in Patent Document 1.
JP 2004-146082 A

  However, since the amplitude of the horizontal transfer clock and the vertical transfer clock is generally as small as about 3 V, it is necessary to perform +3 times boosting and -2 times boosting in order to obtain a sufficient power supply potential for turning on / off the pixel TFT. Therefore, there is a problem that the circuit scale of the power supply circuit becomes large.

  In addition, when the horizontal transfer clock and the vertical transfer clock are used together as signals for driving the power supply circuit, the amplifier that outputs the horizontal transfer clock and the vertical transfer clock has a low driving capability, so a buffer circuit is provided on the TFT substrate. There is a problem that the circuit area is increased and the efficiency of the power supply circuit is reduced.

  Further, when the horizontal transfer clock is divided and used as a drive signal for the power supply circuit, the display may be adversely affected by the inversion timing of the divided clock.

  Furthermore, when horizontal transfer clocks or vertical transfer clocks are used, it is often necessary to route long wires on the glass substrate to transmit these clocks to the power supply circuit, so the frame area of the liquid crystal panel increases. Alternatively, when a COG (chip on glass) is mounted on a glass substrate, such wiring may not be formed due to restrictions on the pattern layout. Further, when a dedicated clock from the driving IC is used, there is a problem that the number of terminals of the liquid crystal panel increases.

  The liquid crystal display device of the present invention has been made in view of the above-described problems. A switching element, a pixel electrode to which a video signal is applied through the switching element, and a common electrode signal that repeats a high level and a low level are applied. In a liquid crystal display device comprising: a common electrode; a liquid crystal aligned by an electric field between the common electrode and the pixel electrode; and a power supply circuit that generates a power supply potential for controlling switching of the switching element. A power supply circuit is coupled in series to the first and second charge transfer elements that are complementarily switched according to the common electrode signal, and a connection point of the first and second charge transfer elements, and the common electrode signal And a first capacitor to which is applied.

  The liquid crystal display device of the present invention includes a switching element formed on a first substrate, a pixel electrode formed on the first substrate, to which a video signal is applied through the switching element, and the first electrode A second substrate disposed opposite to the substrate; a common electrode formed on the second substrate to which a common electrode signal that repeats a high level and a low level is applied; and the common electrode and the pixel electrode In a liquid crystal display device comprising a liquid crystal aligned by an electric field between and a power supply circuit for generating a power supply potential for controlling switching of the switching element, the power supply circuit is formed on the first substrate. A capacitor having first and second charge transfer elements connected in series, a first terminal and a second terminal, the first terminal being connected to a connection point of the first and second charge transfer elements And before A buffer circuit formed on the first substrate, the output of which is applied to the second terminal of the capacitor, and an input capacitor formed between the common electrode facing the input terminal of the buffer circuit; It is characterized by providing.

  The power supply circuit according to the present invention includes first and second charge transfer elements connected in series, a first terminal and a second terminal, and the first terminal transfers the first and second charge transfer. A capacitor connected to the connection point of the element; a buffer circuit whose output is applied to the second terminal of the capacitor; a third terminal and a fourth terminal; and a second input terminal of the buffer circuit. And an input capacitor having a clock signal applied to the fourth terminal.

  According to the liquid crystal display device of the present invention, since the common electrode signal is used as the drive signal for the power supply circuit, it is sufficient to perform +2 times boosting and -1 times boosting, and the circuit scale of the power supply circuit can be reduced. . In addition, since the amplifier that outputs the common electrode signal has a large driving capability, it is not necessary to provide a buffer circuit, and the circuit area can be reduced and the circuit efficiency can be improved. In addition, since the inversion timing of the common electrode signal (timing to transition from H level to L level or timing to transition from L level to H level) is performed in the horizontal blanking period, there is an advantage that the display is not adversely affected. . Furthermore, since the wiring for supplying the common electrode signal is provided on the entire outer periphery of the panel, the common electrode signal can be supplied to the power supply circuit using the wiring regardless of where the power supply circuit is arranged on the panel. Since this is possible, there is an advantage that there are few restrictions on the pattern layout.

  In addition, according to the liquid crystal display device of the present invention, the common electrode signal is supplied to the power supply circuit as the drive clock by using the capacitive coupling by the input capacitor, so that the restrictions on the pattern layout of the drive clock wiring are reduced. In addition, an increase in the frame area of the liquid crystal panel and an increase in the number of terminals can be prevented.

  Further, according to the power supply circuit of the present invention, since the drive clock is supplied by using the capacitor coupling by the capacitor, the restriction on the pattern layout of the drive clock wiring can be reduced, and the circuit An increase in area can be prevented.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a liquid crystal panel 100. A horizontal drive circuit 110 and a vertical drive circuit 120 are formed on the TFT substrate, and a plurality of pixels (only four pixels are shown in FIG. 1) are arranged in a matrix in the display area. The horizontal drive circuit 110 is a shift register that sequentially transfers horizontal start signals based on the horizontal transfer clock CKH, and supplies RGB video signals to the data lines DL in accordance with the output. The vertical drive circuit 120 is a shift register that sequentially transfers vertical start signals based on the vertical transfer clock CKV, and supplies a gate signal to each gate line GL according to the output.

  The drain of the pixel transistor GT composed of the TFT of each pixel is connected to the corresponding data line DL, and the on / off of the pixel transistor GT is controlled by a gate signal. The source of the pixel transistor GT is connected to the pixel electrode 121. A counter substrate is provided to face the TFT substrate, and a common electrode 122 is formed to face the pixel electrode 121 on the counter substrate. Liquid crystal LC is sealed between the TFT substrate and the counter substrate. As shown in FIG. 2, a common electrode signal VCOM that repeats H level and L level for each horizontal period is external to the liquid crystal panel 100 or on the TFT substrate of the liquid crystal panel 100, as shown in FIG. It is applied from the driving IC 200 provided in the circuit.

  If the pixel transistor GT is an N-channel type, the pixel transistor GT is turned on when the gate signal becomes H level. Accordingly, a video signal is applied from the data line DL to the pixel electrode 121 through the pixel transistor GT, and the liquid crystal LC is aligned by an electric field generated between the common electrode 122 and the pixel electrode 121, whereby liquid crystal display is performed.

  Here, since the common electrode signal VCOM repeats the H level and the L level, the potential of the pixel electrode 121 varies due to the capacitor coupling via the liquid crystal LC. Therefore, in order to turn on the pixel transistor GT, a positive power supply potential of VCOMH × 2 that is twice the amplitude is required as the H level of the gate signal. To turn off the pixel transistor GT, the L level of the gate signal is required. As a result, a negative power supply potential of VCOMH × −1 that is −1 times the amplitude is required. Here, VCOMH is about 4.5V.

  In order to generate such a gate signal, a power supply circuit 130 is formed on the TFT substrate of the liquid crystal panel 100 by system-on-glass (SOG) technology, and its output is supplied to the vertical drive circuit 120. It has become. The power supply circuit 130 includes a DC-DC converter that generates a positive power supply potential and a DC-DC converter that generates a negative power supply potential. In the present invention, the common electrode signal VCOM is used as a drive signal for these DC-DC converters.

  FIG. 3 shows a circuit diagram of a DC-DC converter that generates a positive power supply potential. A common electrode signal VCOM is input through an input terminal PIN provided on the liquid crystal panel 100. The input common electrode signal VCOM is input to one terminal of the first flying capacitor C1 as the first common electrode signal VCOM1 via the buffer circuit BF, and the first common electrode signal VCOM1 is inverted. The second common electrode signal VCOM2 is input to one terminal of the second flying capacitor C2. An N-channel charge transfer transistor M1N and a P-channel charge transfer transistor M1P are connected in series, and the other terminal of the second flying capacitor C2 is connected to their gates. Further, an N-channel type charge transfer transistor M2N and a P-channel type charge transfer transistor M2P are connected in series, and the other terminal of the first flying capacitor C1 is connected to their gates. The other terminal of the first flying capacitor C1 is connected to a connection point between the charge transfer transistor M1N and the charge transfer transistor M1P, and the other terminal of the second flying capacitor C2 is connected to the charge transfer transistor M2N and the charge transfer. It is connected to the connection point with the transistor M2P.

  The common source of the N-channel type charge transfer transistors M1N and M2N is applied with VCOMH that is the H level of the common electrode signal VCOM. If the voltage loss due to the transistor is ignored, a positive power supply potential of VCOMH × 2, which is twice VCOMH, and the output current Iout are output from the common drain of the P-channel type charge transfer transistors M1P and M2P. Cout is a smoothing capacitor, R is a load resistance, and the vertical drive circuit 120 corresponds to the load resistance R. The charge transfer transistor is composed of a TFT.

  The steady-state operation of this DC-DC converter will be described with reference to the waveform diagram of FIG. When the first common electrode signal VCOM1 is at the H level, M1N and M2P are turned off, M2N and M1P are turned on, the potential V1 of the connection node between M1N and M1P is boosted to VCOMH × 2, and the level is output through M1P. The The potential V2 at the connection node between M2N and M2P is charged to VCOMH. Next, when the first common electrode signal VCOM1 becomes L level, M1N and M2P are turned on, M2N and M1P are turned off, the potential V2 is boosted to VCOMH × 2, and the level is output through M2P. The potential V1 is charged to VCOMH. That is, VCOMH × 2 is alternately output from the left and right series transistor circuits of the DC-DC converter. However, the voltage loss due to the transistor is ignored.

  According to this DC-DC converter, a potential of VCOMH × 2 suitable for turning on the pixel transistor GT is obtained. (If VCOMH = 4.5V and the voltage loss is neglected, 9.0V) Therefore, there is no need for triple boosting as in the prior art, and the circuit scale can be reduced and the circuit efficiency can be improved. In addition, since the inversion timing of the common electrode signal VCOM (timing for transition from H level to L level or timing for transition from L level to H level) is performed during the horizontal blanking period, the display is not adversely affected. In addition, since the wiring for supplying the common electrode signal VCOM is provided on the entire outer periphery of the liquid crystal panel 100, the power circuit can be used by using the wiring regardless of where the power circuit 130 is disposed on the TFT substrate of the liquid crystal panel 100. Since the common electrode signal VCOM can be supplied to 130, there is an advantage that there are few restrictions on the pattern layout.

  In the liquid crystal display device in which the common electrode 122 is formed opposite to the pixel electrode 121 on the counter substrate as in the above example, the first and second flying capacitors C1 and C2 are formed on the liquid crystal panel 100. Since the fluctuation of the potential of the first flying capacitor C1 and the fluctuation of the potential of the common electrode on the counter substrate become the same potential as the common electrode signal VCOM, a reduction in efficiency due to capacitance division by the first flying capacitor C1 is prevented. can do. On the other hand, in the case of a liquid crystal display device in which a pixel electrode and a common electrode are formed on the same substrate as in an FFS (Field Fringe Switching) method or an IPS (In-Place-Switching) method, there is no electrode on the opposite substrate. There will be no fluctuations. Therefore, according to the configuration of the present invention, it is possible to realize an excellent liquid crystal display device that does not cause a decrease in efficiency in any type of liquid crystal display device.

[Second Embodiment]
FIG. 5 shows a circuit diagram of a DC-DC converter that generates a positive power supply potential. In this DC-DC converter, since the driving capability of the amplifier on the side of the driving IC 200 that outputs the common electrode signal VCOM is large, the buffer circuit BF is omitted. Thereby, a circuit area can be reduced and circuit efficiency can be improved. Further, the second flying capacitor C2 is omitted, and the common electrode signal VCOM is applied only to the first flying capacitor C1.

  The steady state operation of this DC-DC converter will be described. When the common electrode signal VCOM is at the H level, M1N and M2P are turned off, M2N and M1P are turned on, the potential V1 of the connection node between M1N and M1P is boosted to VCOMH × 2, and the level is output through M1P. The potential V2 at the connection node between M2N and M2P is charged to VCOMH. Next, when the common electrode signal VCOM becomes L level, M1N and M2P are turned on, and M2N and M1P are turned off. When M2P is turned on, the potential V2 is charged to VCOMH × 2 by charge transfer from the output side. Therefore, according to the DC-DC converter, the boosting operation is performed only when the common electrode signal VCOM is at the H level.

  According to this DC-DC converter, the circuit area can be further reduced and the circuit efficiency can be improved. In the second embodiment, in the liquid crystal display device in which the common electrode 122 is formed on the counter substrate so as to face the pixel electrode 121, only the first flying capacitor C1 is formed on the liquid crystal panel 100. Therefore, it is possible to prevent a decrease in efficiency due to the capacity division, compared to the first embodiment.

  Other configurations are the same as those of the circuit of the first embodiment, and similar effects can be obtained.

[Third Embodiment]
FIG. 6 shows a circuit diagram of a DC-DC converter that generates a positive power supply potential. In this DC-DC converter, the buffer circuit BF is deleted as in the second embodiment, but the second flying capacitor C2 is provided, and the common electrode signal VCOM is inverted. An inverter INV is provided to be applied to the second flying capacitor C2. Here, the capacitance value of the second flying capacitor C2 is preferably smaller than the capacitance value of the first flying capacitor C1. Other configurations are the same as those of the circuit of the second embodiment, and the same effects can be obtained.

[Fourth Embodiment]
In the first to third embodiments, a DC-DC converter that generates a positive power supply potential is shown. However, in this embodiment, a DC-DC converter that generates a negative power supply potential will be described. As shown in FIG. 7, in this DC-DC converter, the common electrode signal VCOM is applied to the first flying capacitor C1, and the inverted signal of the common electrode signal VCOM is applied to the second flying capacitor C2. . A ground potential Vss (0 V) is applied to the common source of M1P and M2P, and a potential of VCOM × −1 obtained by multiplying VCOM by −1 is obtained from the common drain of M1N and M2N. Thereby, a gate signal suitable for turning off the pixel transistor GT can be created. Accordingly, there is no need for -2 boosting as in the prior art, and the circuit scale can be reduced and the efficiency of the circuit can be improved. Other effects are the same as those of the first to third embodiments.

  The operation of this DC-DC converter will be described. When the common electrode signal VCOM is at the H level, M1N and M2P are off, M2N and M1P are on, the potential V3 of the connection node between M1N and M1P is charged to Vss, and M2N and The potential V4 of the connection node of M2P is lowered to the potential of VCOMH × -1, and the potential is output through M2N.

  When the common electrode signal VCOM becomes L level, M1N and M2P are turned on, M2N and M1P are turned off, the potential V3 is lowered to VCOMH × −1, and the level is output through M1N. The potential V4 is charged to Vss. That is, the potential VCOMH × −1 is alternately output from the left and right series transistor circuits of the DC-DC converter. However, the voltage loss due to the transistor is ignored.

[Fifth Embodiment]
Also in the present embodiment, the common electrode signal VCOM is used as a drive signal for the DC-DC converter of the power supply circuit 130, as in the first to fourth embodiments. However, the common electrode signal VCOM is used as an input capacitor. The point of inputting to the DC-DC converter is different.

  FIG. 8 shows a circuit diagram of a DC-DC converter that generates a positive power supply potential. The clock input unit of the DC-DC converter is provided with a pre-stage buffer circuit 131 and a post-stage buffer circuit 132 for shaping the waveform of the drive clock, and between the input terminal 133 and the common electrode 122 of the pre-stage buffer circuit 131. An input capacitor Cin is formed. The pre-stage buffer circuit 131 is formed by connecting a plurality of CMOS inverters INV1, INV2,.

  As shown in FIG. 9, the CMOS inverters INV1, INV2,... Are composed of a P-channel transistor and an N-channel transistor, the positive power supply potential PVDD being the source of the P-channel transistor and the ground potential PVSS being the N-channel transistor. (0V) is applied. The P-channel transistor and the N-channel transistor are formed of TFTs.

  The structure of the input capacitor Cin is shown in FIG. FIG. 10 is a partial cross-sectional view of the liquid crystal panel 100, and the input terminal 133 of the pre-stage buffer circuit 131 is formed on the TFT glass substrate 10. The input terminal 133 is formed of a metal layer such as aluminum and is covered with the insulating film 11. On the TFT glass substrate 10, a counter glass substrate 20 is disposed with a liquid crystal LC interposed therebetween.

  That is, the input capacitor Cin is a capacitor in which the input terminal 133 is one capacitive electrode, the common electrode 122 formed on the counter glass substrate 20 is the other capacitive electrode, and the insulating film 11 and the liquid crystal LC are capacitive insulating films. is there. Depending on where the power supply circuit 130 is disposed, a sealing resin 12 for sealing the liquid crystal LC may be interposed between the input terminal 133 and the common electrode 122. In this case, the sealing resin 12 becomes a part of the capacitive insulating film.

  With this configuration, a signal synchronized with the common electrode signal VCOM is input to the input terminal 133 due to the coupling of the input capacitor Cin. A long wiring for supplying the common electrode signal VCOM is not necessary, and the common electrode signal VCOM can be taken out from the common electrode 122 formed on the substantially entire surface of the counter glass substrate 20, so that there are few restrictions on the pattern layout. . Further, since the common electrode signal VCOM is used, an increase in the number of terminals of the liquid crystal panel can be prevented.

  The first-stage CMOS inverter INV1 of the pre-stage buffer circuit 131 has a parasitic input capacitance Cp (mainly the gate capacitance of a P-channel transistor and an N-channel transistor). For this reason, the potential of the signal input to the input terminal 133 is attenuated by the capacitance division of the parasitic input capacitance Cp and the input capacitor Cin.

  Therefore, it is preferable that the capacitance value of the input capacitor Cin is sufficiently larger than the parasitic input capacitance Cp. For example, when the size of the transistor is W / L = 20 μm / 6 μm, it is preferable to set Cin> 0.5 pF. In order to increase the capacitance value of the input capacitor Cin, the planar pattern size of the input terminal 133 may be designed to be large.

  The drive clock synchronized with the common electrode signal VCOM input to the input terminal 133 is input to one terminal of the first flying capacitor C1 as the first drive clock CPCLK through the front-stage buffer circuit 131 and the rear-stage buffer circuit 132. The first driving clock CPCLK is input to one terminal of the second flying capacitor C2 as the inverted second driving clock XCPCLK. The first drive clock CPCLK and the second drive clock XCPCLK are opposite phase clocks, but their amplitude is PVDD.

  In the charge pump unit, an N-channel charge transfer transistor MN1 and a P-channel charge transfer transistor MP1 are connected in series, and the other terminal of the second flying capacitor C2 is connected to their gates. Further, an N-channel charge transfer transistor MN2 and a P-channel charge transfer transistor MP2 are connected in series, and the other terminal of the first flying capacitor C1 is connected to the gates thereof. The other terminal of the first flying capacitor C1 is connected to a connection point between the charge transfer transistor MN1 and the charge transfer transistor MP1, and the other terminal of the second flying capacitor C2 is connected to the charge transfer transistor MN2 and the charge transfer. It is connected to a connection point with the transistor MP2.

  A power supply potential PVDD is applied to a common source of the N-channel type charge transfer transistors MN1 and MN2. If the voltage loss due to the transistor is ignored, a positive power supply potential of 2PVDD that is twice PVDD and an output current IVPP are output as the output potential VPP from the common drain of the P-channel type charge transfer transistors MP1 and MP2. A smoothing capacitor C3 is connected to the common drain of the N-channel type charge transfer transistors MP1 and MP2. The charge transfer transistor is formed of a TFT.

  The steady-state operation of this DC-DC converter will be described with reference to the waveform diagram of FIG. When the first drive clock CPCLK is at H level (PVDD), MN1 and MP2 are turned off, MN2 and MP1 are turned on, and the potential V1 of the connection node between MN1 and MP1 is the capacitor cup of the first flying capacitor C1 The voltage is boosted to 2PVDD by the ring, and the level is output through MP1. The potential V2 at the connection node between MN2 and MP2 is charged to PVDD.

  Next, when the first drive clock CPCLK falls to the L level (PVSS), MN1 and MP2 are turned on, MN2 and MP1 are turned off, and the potential V2 is 2PVDD by the capacitor coupling of the second flying capacitor C2. And the level is output through MP2. The potential V1 is charged to PVDD. That is, 2PVDD is alternately output from the left and right series transistor circuits of the DC-DC converter. However, the voltage loss due to the transistor is ignored.

[Sixth Embodiment]
Next, a DC-DC converter that generates a negative power supply potential using the input capacitor Cin will be described. As shown in FIG. 12, in this DC-DC converter, similarly to the circuit of the fifth embodiment, a drive clock synchronized with the common electrode signal VCOM input to the input terminal 133 is obtained, and the same effect is obtained. Play. The driving clock is input to one terminal of the first flying capacitor C11 as the first driving clock CPCLK through the front-stage buffer circuit 131 and the rear-stage buffer circuit 132, and the second driving clock XCPCLK is input to the second flying clock XCPCLK. It is input to one terminal of the capacitor C12.

  In the charge pump unit, the N-channel charge transfer transistor MN11 and the P-channel charge transfer transistor MP11 are connected in series. The fifth point is that the ground potential PVSS is applied to the common source of MP11 and MP12. Unlike the circuit of the embodiment, a potential of -PVDD obtained by multiplying PVDD by -1 is obtained from the common drain of MN11 and MN12. A smoothing capacitor C13 is connected to the common drain of MN11 and MN12.

  The operation of this DC-DC converter will be described with reference to FIG. 13. When the first drive clock CPCLK is at H level (PVDD), MN11 and MP12 are off, MN12 and MP11 are on, and the connection node between MN11 and MP11 Potential V3 is charged to PVSS, the potential V4 of the connection node between MN12 and MP12 drops to the potential of -PVDD, and the potential is output through MN12.

  When the first drive clock CPCLK becomes L level (PVSS), MN11 and MP12 are turned on, MN12 and MP11 are turned off, the potential V3 is lowered to -PVDD, and the level is output through MN11. The potential V4 is charged to PVSS. That is, a potential of −PVDD is alternately output from the left and right series transistor circuits of the negative power supply generation circuit.

  The DC-DC converter is not limited to the circuit of the above embodiment as long as it is a circuit that converts and outputs an input potential using a flying capacitor and a charge transfer element. May be used. Further, the pre-stage buffer circuit 131 and the post-stage buffer circuit 132 of the DC-DC converter are not limited to those of the embodiment, but may be modified or other types of buffer circuits may be used. The buffer circuit may be shared by a DC-DC converter that generates a positive potential and a DC-DC converter that generates a negative potential.

1 is a circuit diagram showing a liquid crystal display device according to a first embodiment of the present invention. It is an operation | movement waveform diagram of the liquid crystal display device by the 1st Embodiment of this invention. 1 is a circuit diagram of a DC-DC converter according to a first embodiment of the present invention. It is an operation | movement waveform diagram of the DC-DC converter by the 1st Embodiment of this invention. It is a circuit diagram of the DC-DC converter by the 2nd Embodiment of this invention. It is a circuit diagram of the DC-DC converter by the 3rd Embodiment of this invention. It is a circuit diagram of the DC-DC converter by the 4th Embodiment of this invention. It is a circuit diagram of the DC-DC converter by the 5th Embodiment of this invention. It is a circuit diagram of the front | former stage buffer circuit of the DC-DC converter by the 5th Embodiment of this invention. It is sectional drawing which shows the structure of an input capacitor. It is a wave form diagram which shows the operation | movement of the DC-DC converter by the 5th Embodiment of this invention. It is a circuit diagram of the DC-DC converter by the 6th Embodiment of this invention. It is a wave form diagram which shows the operation | movement of the DC-DC converter by the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 TFT glass substrate 11 Insulating film 12 Sealing resin 20 Opposite glass substrate 100 Liquid crystal panel 110 Horizontal drive circuit 120 Vertical drive circuit 121 Pixel electrode 122 Common electrode 130 Power supply circuit 131 Pre-stage buffer circuit 132 Post-stage buffer circuit 133 Input terminal 200 Drive IC DL Data line GL Gate line BF Buffer circuit C1, C11 First flying capacitor C2, C12 Second flying capacitor C3, C13 Smoothing capacitor Cin Input capacitor Cout Smoothing capacitor R Load resistance INV Inverter INV1, INV2,. CMOS inverters M1N, M2N N-channel type charge transfer transistors M1P, M2P P-channel type charge transfer transistors MN1, MN2, MN11, MN12 N-channel type Charge transfer transistors MP1, MP2, MP11, MP12 P-channel type charge transfer transistor

Claims (7)

Oriented by a switching element, a pixel electrode to which a video signal is applied through the switching element, a common electrode to which a common electrode signal that repeats a high level and a low level is applied, and an electric field between the common electrode and the pixel electrode A liquid crystal display device including a liquid crystal and a power supply circuit that generates a power supply potential for controlling switching of the switching element,
The power supply circuit is coupled to a connection point of the first and second charge transfer elements connected in series and switching complementarily according to the common electrode signal, and the first and second charge transfer elements. A liquid crystal display device comprising: a first capacitor to which a signal is applied. The power supply circuit is coupled to a connection point of the third and fourth charge transfer elements connected in series and complementarily switching according to the common electrode signal, and the third and fourth charge transfer elements. The liquid crystal display device according to claim 1, further comprising a second capacitor to which an inverted signal of the signal is applied. The liquid crystal display device according to claim 2, wherein the common electrode signal is applied to the first and second capacitors through a buffer circuit. A switching element formed on the first substrate; a pixel electrode formed on the first substrate to which a video signal is applied through the switching element; and a second electrode disposed opposite to the first substrate. A common electrode to which a common electrode signal that repeats a high level and a low level is applied, and a liquid crystal that is aligned by an electric field between the common electrode and the pixel electrode, In a liquid crystal display device comprising a power supply circuit that generates a power supply potential for controlling switching of the switching element,
The power supply circuit includes first and second charge transfer elements formed on the first substrate and connected in series, a first terminal and a second terminal, and the first terminal is the first and second terminals. A capacitor connected to a connection point of a second charge transfer element; a buffer circuit formed on the first substrate, the output of which is applied to a second terminal of the capacitor; and an input terminal of the buffer circuit And an input capacitor formed between the counter electrode and the common electrode facing each other. 5. The liquid crystal display device according to claim 4, wherein the buffer circuit is formed by connecting a plurality of inverters in series, and the input capacitor is formed between an input terminal of a first-stage inverter and the common electrode. . The liquid crystal display device according to claim 5, wherein a capacitance value of the input capacitor is larger than a capacitance value of a parasitic input capacitance of the first-stage inverter. A capacitor having first and second charge transfer elements connected in series, a first terminal and a second terminal, the first terminal being connected to a connection point of the first and second charge transfer elements A buffer circuit whose output is applied to the second terminal of the capacitor, a third terminal and a fourth terminal, and a third terminal is connected to the input terminal of the buffer circuit, A power supply circuit comprising an input capacitor having a clock signal applied to a terminal.

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