JP2002299559A - Booster circuit and display comprising it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a booster circuit having no potential loss in which variation of transistor characteristics causes no variation in the attainable boosted potential. SOLUTION: The booster circuit comprises capacitors CP1 and CP2 having one ends connected, respectively, with nodes ND1 and ND2, n-channel transistors NT1 and NT2, and p-channel transistors PT1 and PT2. Drain terminals D of the PT1 and PT2 are connected commonly and further connected with an output terminal 3. Drain terminals D of the NT1 and NT2 are connected commonly and further connected with a power supply potential terminal. Gate terminals of the NT1 and PT1 are connected common and further connected with the node ND2. Gate terminals of the NT2 and PT2 are connected common and further connected with the node ND1. Clock signals CLK and/CLK having inverted phases are applied to the other terminals of the capacitors CP1 and CP2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a booster circuit and a display device having the booster circuit, and more particularly to a booster circuit using a capacitor and a display device having the booster circuit.

[0002]

2. Description of the Related Art Heretofore, a booster circuit using a capacitor has been known. FIG. 14 is a circuit diagram showing an example of a conventional booster circuit using a capacitor. Referring to FIG. 14, a conventional booster circuit includes a capacitor (pumping capacitor) CP1 and an n-channel MOS (Metal Ox).
Ide Semiconductor) Transistor N
T1 (hereinafter referred to as n-channel transistor NT1)
And an n-channel MOS transistor NT2 (hereinafter, referred to as an n-channel transistor NT2). n
The source terminal S of the channel transistor NT1 is at the node N
The drain terminal D of the n-channel transistor NT1 is connected to the power supply potential VDD. Also,
The drain terminal D of the n-channel transistor NT2 is connected to the node ND1, and the source terminal S of the n-channel transistor NT2 is connected to the output terminal 102. In addition, the capacitor CP1 is connected via the input terminal 101 to:
Clock signal CLK is input.

Next, an outline of a voltage generating operation by the conventional booster circuit shown in FIG. 14 will be described. First, in the initial state, when the clock signal CLK is set to L level (GND), since the gate side and the drain side of the n-channel transistor NT1 are at the power supply potential VDD, the potential of the source-side node ND1 changes from VDD to the n-channel transistor. It becomes a value (VDD-Vtn) obtained by subtracting the threshold voltage Vtn. Further, the boosted potential VPP of the output terminal 102 connected to the source terminal of the n-channel transistor NT2 is VDD-2Vtn since the potential on the gate side and the drain side of the n-channel transistor NT2 is VDD-Vtn.

When the clock signal CLK changes from L level to H level (VDD), the capacitor CP
1, the potential of the node ND1 is raised by an amount corresponding to the H level (VDD) of the clock signal CLK.
As a result, the potential of the node ND1 becomes 2VDD−Vtn.
Becomes

By raising the potential of the node ND1 to 2VDD-Vtn, the potential of the gate and the drain of the n-channel transistor NT2 becomes 2VDD.
−Vtn, the boosted potential VP of the output terminal 102 connected to the source terminal of the n-channel transistor NT2
P reaches 2VDD-2Vtn.

[0006] In this manner, 1 of the clock signal CLK is output.
By repeating the above operation every cycle,
The boosted potential VPP of the output terminal 102 connected to the source terminal of the n-channel transistor NT2 is 2VDD-2V
The voltage is increased to tn.

[0007]

However, in the above-described conventional boosting circuit, the ultimate boosted potential VPP has a potential loss of 2 Vtn (twice the threshold voltage Vtn) since the theoretical value is 2VDD-2Vtn. However, there is a problem that the problem occurs. Further, in the conventional booster circuit, since boosting is performed only during the H level period for each clock signal cycle, there is a problem that the boosting efficiency is poor.

Furthermore, conventionally, the ultimate boosted potential VPP
Is a value correlated with the threshold voltage Vtn of the n-channel transistors NT1 and NT2, and there is a problem that the ultimate boosted potential VPP varies due to variations in the characteristics of the n-channel transistors NT1 and NT2. Therefore, in a booster circuit used for a display device or the like, it is necessary to adopt a circuit configuration capable of obtaining a reached boosted potential VPP having a margin in consideration of variations in transistor characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and an object of the present invention is to eliminate potential loss and to prevent variations in the ultimate boosted potential due to variations in transistor characteristics. It is to provide a booster circuit.

Another object of the present invention is to provide a booster circuit capable of shortening the time required to reach a target output voltage.

Still another object of the present invention is to provide a display device which does not require a margin in consideration of variations in threshold characteristics of transistors.

Another object of the present invention is to make it possible to start up a boosted power supply at an early stage when the power supply is turned on.

[0013]

In order to achieve the above object, a booster circuit according to claim 1 comprises a first node and a second node.
A first node to which one terminal of each is connected to the node
A capacitor and a second capacitor, a first one conductivity type transistor having one of a source terminal and a drain terminal connected to the first node, and the other connected to a power supply potential terminal;
A first other conductivity type transistor having one of a source terminal and a drain terminal connected to the first node and the other connected to a voltage output terminal, and one of a source terminal and a drain terminal connected to a second node and the other being a power supply. The semiconductor device includes a second one conductivity type transistor connected to the potential terminal, and a second other conductivity type transistor having one of the source terminal and the drain terminal connected to the second node and the other connected to the voltage output terminal. The voltage output terminals of the first other conductivity type transistor and the second other conductivity type transistor are commonly connected. In addition, the first one conductivity type transistor and the first
The gate terminals of the other conductivity type transistors are connected together and connected to the second node. The gate terminals of the second one conductivity type transistor and the second other conductivity type transistor are connected together and connected to the first node. It is connected. Further, clock signals whose phases are inverted are applied to the other terminals of the first capacitor and the second capacitor, respectively.

According to the first aspect of the present invention, the first node side of the first capacitor and the second node side of the second capacitor correspond to the H level of the clock signal and the inverted clock signal, respectively. Since the electric charge is accumulated by flowing the electric charge as much as possible, the first
The potentials of the node and the second node are raised by an amount corresponding to the H level of the clock signal and the inverted clock signal. Then, the accumulated charge is pumped to the voltage output terminal side through the first and second other conductivity type transistors having no drop in threshold voltage, so that the voltage drops by the threshold voltage of the transistor. There is no. Thus, it is possible to obtain a booster circuit that has no potential loss and does not vary in ultimate boosted potential due to variations in transistor characteristics. Further, since the pumping operation for generating the target voltage is performed every half cycle by the clock signal and the inverted clock signal, the pumping can be performed more efficiently. As a result, the time required to reach the target output voltage can be reduced.

According to a second aspect of the present invention, in the booster circuit according to the first aspect, the booster circuit has a triple well structure.
The first and second one-conductivity type transistors are formed on a P-type well as field-effect transistors, and a power supply potential terminal is used to obtain the back gate potential. The first and second other conductivity type transistors are formed as field effect transistors on the N-type well, and the voltage output terminal is connected to the N-type well to obtain the back gate potential. The first capacitor and the second capacitor are formed by commonly connecting the source terminal and the drain terminal of the other conductivity type transistor separately formed on the N-type well, and have the gate terminal thereof. Connected to the first node and the second node, respectively. According to the second aspect, with such a configuration, it is possible to easily form a booster circuit having the circuit configuration as in the first aspect. Thus, in the second aspect, the same operation and effect as those of the first aspect can be obtained.

According to a third aspect of the present invention, in the booster circuit according to the first aspect, the booster circuit has a triple well structure.
The first and second one-conductivity type transistors are formed on a P-type well as field-effect transistors, and a power supply potential terminal is used to obtain the back gate potential. The first and second other conductivity type transistors are formed as field effect transistors on the N-type well, and the voltage output terminal is connected to the N-type well to obtain the back gate potential. The first capacitor and the second capacitor are formed by commonly connecting the source terminal and the drain terminal of one conductivity type transistor separately formed on the P-type well, and the gate terminal is connected to the first capacitor and the second capacitor. Connected to the first node and the second node, respectively. According to the third aspect of the present invention, a booster circuit having the circuit configuration as in the first aspect can be easily formed by adopting such a configuration. As a result, according to the third aspect, the same operation and effect as the first aspect can be obtained.

According to a fourth aspect of the present invention, in the booster circuit according to the first aspect, the booster circuit has a double well structure.
The first and second one-conductivity type transistors are formed on a P-type well as field-effect transistors, and a power supply potential terminal is used to obtain the back gate potential. The first and second other conductivity type transistors are formed as field effect transistors on the N-type well, and the voltage output terminal is connected to the N-type well to obtain the back gate potential. The first capacitor and the second capacitor are formed by commonly connecting the source terminal and the drain terminal of one conductivity type transistor separately formed on the P-type well, and the gate terminal is connected to the first capacitor and the second capacitor. Connected to the first node and the second node, respectively. According to a fourth aspect of the present invention, a booster circuit having the circuit configuration as described in the first aspect can be easily formed by such a configuration. As a result, according to the fourth aspect, the same operation and effect as the first aspect can be obtained.

According to a fifth aspect of the present invention, in the booster circuit according to the first aspect, the booster circuit is formed on an insulating film formed on a silicon substrate. The first and second other conductivity type transistors have a semiconductor layer formed on an insulating film as their active layer, and at least one electrode of the first and second capacitors has an n-type electrode formed on the semiconductor layer. It is formed by either the mold region or the p-type region. According to the fifth aspect, by adopting such a configuration, it is possible to easily form a booster circuit having the circuit configuration as in the first aspect. Thereby, in claim 5, the same operation and effect as in claim 1 can be obtained.

According to a sixth aspect of the present invention, in the booster circuit according to the first aspect, the booster circuit is formed on a glass substrate or on an insulating film formed on the glass substrate. The transistor and the first and second other conductivity type transistors are formed using a semiconductor layer formed on a glass substrate or an insulating film as an active layer, and at least one electrode of the first and second capacitors is , And is formed by one of an n-type region and a p-type region formed in the semiconductor layer. According to the sixth aspect, with such a configuration, it is possible to easily form the booster circuit having the circuit configuration as in the first aspect. Thereby, in claim 6, the same operation and effect as in claim 1 can be obtained.

The booster circuit according to claim 7 is the booster circuit according to claim 1
6. The third one-conductivity-type transistor connected to each of the first node and the second node, one of the source terminal and the drain terminal, and the gate terminal being connected to the power supply potential terminal. 4. The semiconductor device further includes a single conductivity type transistor. According to the seventh aspect of the present invention, when the electric charge is accumulated in the first capacitor and the second capacitor, more electric charges can be supplied, and thus the electric charge accumulation time can be further reduced. . Thus, the time required to reach the target output voltage can be further reduced.

The booster circuit according to claim 8 is a booster circuit according to claims 1 to
7, further includes an inverter circuit for generating a clock signal having an inverted phase based on one clock signal. According to the eighth aspect of the present invention, since one clock input signal can be obtained by such a configuration, the configuration of the external circuit can be simplified as compared with the case where two clock input signals are used. .

According to a ninth aspect of the present invention, there is provided a display device provided with a booster circuit, wherein display pixels are arranged in a matrix at intersections of a plurality of scanning lines and a plurality of data lines, and provided for each display pixel. An active switching element for controlling a voltage, a scanning line driving circuit for scanning a plurality of scanning lines and applying a driving voltage for activating the active switching element, and a booster circuit for outputting a voltage to the scanning line driving circuit. It is a display device provided with. And the booster circuit
A first capacitor and a second capacitor each having one terminal connected to the first node and the second node, one of a source terminal and a drain terminal connected to the first node, and the other connected to a power supply potential terminal A first one conductivity type transistor to be connected, a first other conductivity type transistor having one of a source terminal and a drain terminal connected to a first node and the other connected to a voltage output terminal, and a source terminal and a drain connected to a second node. A second one-conductivity-type transistor in which one of the terminals is connected and the other is connected to a power supply potential terminal; and a second transistor in which one of a source terminal and a drain terminal is connected to a second node and the other is connected to a voltage output terminal. And other conductivity type transistors. The voltage output terminals of the first other conductivity type transistor and the second other conductivity type transistor are commonly connected, and the gate terminals of the first one conductivity type transistor and the first other conductivity type transistor are commonly connected, Connected to the second node, the gate terminals of the second one conductivity type transistor and the second other conductivity type transistor are connected in common, and
Connected to the node, clock signals having phases inverted from each other are applied to the other terminals of the first capacitor and the second capacitor, respectively.

According to the ninth aspect, as described above, by providing the display device with the booster circuit, the booster power supply can be used only for a necessary portion of the display device. In the portion where no power supply voltage is provided, the power supply voltage can be reduced. In addition, since the use of the booster circuit having the above structure does not cause a drop in the threshold value of the boosted potential, it is necessary to provide a margin in the display device in consideration of variations in the threshold characteristics of transistors. Absent. Therefore, current consumption of the display device can be reduced. In the booster circuit having the above-described configuration, the pumping operation for generating the target voltage is performed every half cycle by the clock signal and the inverted clock signal, so that the pumping can be performed more efficiently. Thereby, in the display device, the time required to reach the target output voltage can be reduced. As a result, in the display device, it is possible to quickly start up the boosted power supply when the power is turned on.

According to a tenth aspect of the present invention, in the display device having the booster circuit, in the configuration of the ninth aspect, at least the booster circuit is formed on a glass substrate or on an insulating film formed on the glass substrate. The first and second one conductivity type transistors and the first and second other conductivity type transistors have a semiconductor layer formed on a glass substrate or an insulating film as an active layer thereof, and have a first and a second capacitor. Is formed by one of an n-type region and a p-type region formed in the semiconductor layer. According to the tenth aspect, with such a configuration, it is possible to easily form a booster circuit having the circuit configuration as in the ninth aspect. Thereby, Claim 10
Thus, the same function and effect as those of the ninth aspect can be obtained.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a basic configuration of a booster circuit according to a first embodiment of the present invention. FIG. 2 is a timing chart for explaining an operation of generating a boosted voltage by the booster circuit of the first embodiment shown in FIG.

First, the basic configuration of the booster circuit according to the first embodiment will be described with reference to FIG. The booster circuit according to the first embodiment includes two capacitors CP1 and CP2,
Two n-channel transistors NT1 and NT2, 2
And two p-channel transistors PT1 and PT2. In the booster circuit of the first embodiment, nodes ND connected to capacitors CP1 and CP2, respectively,
1 and a predetermined boosted potential VPP via ND2.

The nodes ND1 and ND2
Are examples of the “first node” and the “second node” of the present invention, respectively. Capacitor CP1 and capacitor CP2 are examples of the “first capacitor” and the “second capacitor” of the present invention, respectively. Further, the n-channel transistor NT1 and the n-channel transistor N
T2 is an example of the "first one conductivity type transistor" and the "second one conductivity type transistor" of the present invention, respectively. Further, the p-channel transistor PT1 and the p-channel transistor PT2 are respectively the "first
It is an example of "another conductivity type transistor" and "a second other conductivity type transistor".

The drain terminal D of the n-channel transistor NT1 is connected to the power supply potential VDD, and the source terminal S is connected to the node ND1. The source terminal S of the p-channel transistor PT1 is connected to the node ND1, and the drain terminal D is connected to the output terminal 3. The gate terminals of the n-channel transistor NT1 and the p-channel transistor PT1 are commonly connected and are also connected to a node ND2.

The drain terminal D of the n-channel transistor NT2 is connected to the power supply potential VDD, and the source terminal S is connected to the node ND2. The source terminal S of the p-channel transistor PT2 is connected to the node ND2, and the drain terminal D is connected to the output terminal 3. Further, the n-channel transistor NT2
And the gate terminal of the p-channel transistor PT2
They are connected in common and connected to a node ND1.

The drain terminals D of the n-channel transistors NT1 and NT2 are
Commonly connected. Also, a p-channel transistor P
T1 and the drain terminal D of the p-channel transistor PT2 are commonly connected. Also, the capacitor CP1
And node ND1 and node N of capacitor CP2
Terminals that are not connected to D2 are clock signals CLK and / CLK (“/”) whose phases are inverted from each other, respectively.
Are the clock signal input terminals 1 and 2 to which logic inversion is applied.

Next, the operation of generating a boosted voltage by the booster circuit of the first embodiment having the above configuration will be described with reference to FIG.
This will be described with reference to FIG.

First, at time t1 shown in FIG. 2, when the clock signal CLK starts to change to the H level (VDD), the potential VN1 of the node ND1 changes to the clock signal CLK.
(See FIGS. 2A and 2C). Accordingly, the node ND1
The n-channel transistor NT2 whose gate terminal is connected to the ON state shifts to the ON state, and the p-channel transistor P2 whose gate terminal is connected to the node ND1.
T2 shifts to the off state. Also, the clock signal / CL
When K starts to change to L level (0 V), the node ND2
Of the potential VN2 of FIG. 2 decreases (see FIGS. 2B and 2D). Accordingly, the n-channel transistor NT1 whose gate terminal is connected to the node ND2 shifts to the off state, and the p-channel transistor PT1 whose gate terminal is connected to the node ND2 shifts to the on state.

In this case, the p-channel transistor PT1
Is turned on, the electric charge stored in the capacitor CP1 is extracted to the VPP side via the p-channel transistor PT1. Thereby, the node ND
The potential VN1 of 1 gradually decreases from the H level (see FIG. 2C).

The n-channel transistor NT2
Is turned on, the n-channel transistor NT2
Charge proportional to the capacitance of the capacitor CP2 flows into the node ND2 from the drain terminal D side. This charge is stored in the capacitor CP2 because the p-channel transistor PT2 is off. This allows
The potential VN2 of the node ND2 gradually rises from the L level (see FIG. 2D).

Next, at time t2, the clock signal C
When LK starts to change to L level and clock signal / CLK starts to change to H level, the operation opposite to that at time t1 is performed in each transistor pair. That is, when clock signal / CLK starts to change to H level (VDD) at time t2, the potential VN of node ND2 becomes
2 rises and rises by an amount corresponding to the H level of the clock signal / CLK (see FIGS. 2B and 2D). Accordingly, the n-channel transistor NT1 shifts to the on state, and the p-channel transistor PT1 shifts to the off state. When the clock signal CLK starts to change to the L level (0 V), the potential V of the node ND1 becomes
N1 decreases (see FIGS. 2A and 2C). Accordingly, the n-channel transistor NT2 shifts to the off state, and the p-channel transistor PT2 shifts to the on state.

As the p-channel transistor PT2 is turned on, the charge stored in the capacitor CP2 is drawn to the VPP side, and the potential VN2 of the node ND2 gradually decreases from the H level (FIG. 2 (d)). )reference).

Further, the n-channel transistor NT1
Is turned on, the n-channel transistor NT1
Charge proportional to the capacitance of the capacitor CP1 flows from the drain terminal D side to the node ND1 side. This charge is stored in the capacitor CP1 because the p-channel transistor PT1 is in the off state, and accordingly, the potential VN1 of the node ND1 gradually rises from the L level (see FIG. 2C).

Subsequently, at time t3, when the clock signal CLK starts to change to the H level again, the same operation as that described at time t1 is performed.

By repeating such an operation, p-channel transistors PT1 and PT2 are provided every half cycle of clock signal CLK or clock signal / CLK.
The boosted voltage VPP can be generated by drawing the electric charge to the VPP side via any of the above (FIG. 2)
(E)). That is, in the booster circuit of the first embodiment, the pumping operation for boosting is performed every half cycle of the clock signal, so that pumping can be performed more efficiently. As a result, the time required to reach the target output voltage can be reduced.

Further, in the booster circuit of the first embodiment, since the threshold values of the n-channel transistors NT1 and NT2 and the p-channel transistors PT1 and PT2 do not drop, the final attained boosted voltage has a theoretical value of 2VDD. . As a result, in the booster circuit of the first embodiment, the ultimate boosted voltage does not depend on the variation in the characteristics of the MOS transistors.

FIG. 3 is a circuit diagram of the booster circuit of the first embodiment shown in FIG.
13 is a graph showing a result of simulating a change in the attained potential when the threshold voltage Vtn of T2 and the threshold voltages Vtp of the p-channel transistors PT1 and PT2 are changed. Referring to FIG. 3, the case where the threshold voltage is set to Vtn large and Vtp small, and the case where Vtn is small and Vtp is small
In either case, the arrival time until reaching the final attained boosted potential is different, but the final attained boosted potential is almost the same as the result when the threshold voltage is standard (2).
VDD).

FIG. 4 shows a cross-sectional structure when the booster circuit of the first embodiment is formed on a semiconductor substrate, and FIG. 5 shows an equivalent circuit thereof. In the structure shown in FIG. 4, the booster circuit is formed on a P-type silicon substrate having a triple well structure of a P-type well, an N-type well, and a P-type well (P-well / N-well / P-well). ing. in this case,
The n-channel transistors NT1 and NT2 are formed as MOSFETs (MOS field effect transistors) on the P-type well, and each drain terminal D is connected to the P-type well to obtain a back gate potential.

The p-channel transistors PT1 and PT2 are formed as MOSFETs on the N-type well, and the output terminal 3 is connected to the N-type well in order to obtain the back gate potential.

The capacitors CP1 and CP2 are
The source terminal and the drain terminal of a p-channel transistor separately formed on the N-type well are formed as commonly connected. Gate terminals G of capacitors CP1 and CP2 are connected to corresponding nodes ND1 and ND2, respectively.

The first embodiment can be modified as follows.

FIG. 6 is a sectional view showing a sectional structure of a booster circuit according to a first modification of the first embodiment, and FIG. 7 is an equivalent circuit diagram thereof. In the first embodiment shown in FIG.
The example in which the capacitors CP1 and CP2 are formed by p-channel transistors separately formed on the N-type well has been described. On the other hand, in the first modified example of the first embodiment, as shown in FIG. 6, the capacitors CP1 and CP2 are formed by n-channel transistors separately formed on the P-type well.

FIG. 8 is a sectional view showing a sectional structure of a booster circuit according to a second modification of the first embodiment. In the first embodiment shown in FIG. 4, the booster circuit is formed on a P-type silicon substrate having a triple well structure. In contrast, FIG.
In the second modification of the first embodiment shown in FIG.
An example is shown in which the transistor is formed on an N-type silicon substrate having a double well structure of -well / P-well.

FIG. 9 is a sectional view showing a sectional structure of a booster circuit according to a third modification of the first embodiment. Referring to FIG. 9, a third modification of the first embodiment shows an example in which a booster circuit is formed on an insulating film formed on a silicon substrate. In this case, the n-channel transistor NT1
And NT2 and p-channel transistors PT1 and PT2 are formed in interlayer insulating film 101 formed on the insulating film using a semiconductor layer such as single crystal, polycrystal, or amorphous silicon as an active layer.

The capacitors CP1 and CP2 are also
The lower electrode 103 is formed on an insulating film, and is formed by an n-type region (or a p-type region) formed in a part of the semiconductor layer. The dielectric films 105 of the capacitors CP1 and CP2 include, for example, n-channel transistors NT1 and NT2 and p-channel transistors PT1
And PT2 are formed of the same insulating film (for example, silicon oxide film) as gate oxide film 102.

FIG. 10 is a sectional view showing a sectional structure of a booster circuit according to a fourth modification of the first embodiment. Referring to FIG. 10, in a fourth modification of the first embodiment, a booster circuit is formed on a glass substrate. In this case, the n-channel transistors NT1 and NT2 and the p-channel transistors PT1 and PT2 include a semiconductor layer such as single crystal, polycrystal or amorphous silicon as an active layer in an interlayer insulating film 101 formed on a glass substrate. It is formed. In this case, n-channel transistors NT1 and NT2 and p-channel transistors PT1 and PT
The gate electrode G with T2 is formed of, for example, a chromium (Cr) thin film or a silicide thin film.

The capacitors CP1 and CP2 are also formed on a glass substrate, and the lower electrode 103 is formed by an n-type region (or p-type region) formed in a part of the semiconductor layer. In addition, capacitors CP1 and C
The upper electrode 104 of P2 is formed of, for example, a chromium (Cr) thin film. Dielectric film 105 of capacitors CP1 and CP2 is formed of, for example, the same insulating film (for example, silicon oxide film) as gate oxide film 102 of n-channel transistors NT1 and NT2 and p-channel transistors PT1 and PT2.

Although the booster circuit is formed on the glass substrate in FIG. 10, the booster circuit may be formed on an insulating film formed on the glass substrate. FIG. 10 illustrates an example in which a top-gate transistor is formed; however, a bottom-gate transistor may be used.

(Second Embodiment) FIG. 11 shows a second embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a booster circuit according to the embodiment. FIG.
In the booster circuit according to the second embodiment, in the configuration of the booster circuit according to the first embodiment shown in FIG. 1, the drain terminal and the gate terminal are connected to the power supply potential VDD at the nodes ND1 and ND2, respectively. An example in which connected n-channel transistors NT3 and NT4 are added is shown. The n-channel transistors NT3 and NT4 are examples of the “third one conductivity type transistor” and the “fourth one conductivity type transistor” of the present invention, respectively.

In the second embodiment, as described above, n for supplying the power supply potential to the capacitors CP1 and CP2 is used.
By adding the channel transistors NT3 and NT4, more electric charges can be supplied when electric charges are stored in the capacitors CP1 and CP2, so that the time for storing electric charges can be further reduced.
Thus, the time required to reach the target output voltage can be further reduced.

The other configurations and effects of the second embodiment are the same as those of the first embodiment.

(Third Embodiment) FIG. 12 shows a third embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a booster circuit according to the embodiment. FIG.
With reference to FIG. 3, in the third embodiment, the first embodiment shown in FIG.
In the configuration of the booster circuit of the embodiment, the clock signal / C whose phase is inverted based on one clock signal CLK
An example in which an inverter circuit 4 for generating LK is provided is shown.

In the third embodiment, as described above, 1
Inverter circuit 4 for generating clock signal / CLK having an inverted phase based on two clock signals CLK
Since the number of clock input signals can be reduced to one, the configuration of the external circuit can be simplified as compared with the case where two clock input signals are used.

Note that a pair of clock signals CLK1 and CLK2 may be separately generated and applied to clock signal input terminals 1 and 2, respectively.

Other configurations and effects of the third embodiment are the same as those of the first embodiment.

(Fourth Embodiment) FIG. 13 shows a fourth embodiment of the present invention.
1 is a block diagram illustrating a display device including a booster circuit (boost power supply circuit) according to an embodiment. Referring to FIG. 13, the display device of the fourth embodiment has, for example, the circuit configuration of the booster circuit (boost power supply circuit) of the first embodiment shown in FIG. Fourth Embodiment
It has a cross-sectional structure according to a modification.

In the fourth embodiment, an example is shown in which the present invention is applied to a polysilicon TFT liquid crystal display device as a display device provided with a booster circuit (boost power supply circuit).

As shown in FIG. 13, the display device according to the fourth embodiment includes a display unit 50 formed on a glass substrate, a scanning line driving circuit 60, a data driving circuit 70, and a negative voltage generating circuit 80. , A boost power supply circuit 90. The display unit 50 is provided at each intersection of the plurality of scanning lines (Y1 to Yn) and the plurality of data lines (X1 to Xn), and is provided for each display pixel PX arranged in a matrix. An active switching element ST for controlling a voltage applied to the display pixel PX. The active switching element ST is formed of, for example, a polysilicon thin film transistor (polysilicon TFT). The boost power supply circuit 90 is an example of the “boost circuit” of the present invention.

The scanning line driving circuit 60 scans a plurality of scanning lines (Y1 to Yn) and scans the scanning lines (Y1 to Yn).
1 to Yn), a drive voltage for activating the active switching element ST is applied. The data driving circuit 70 transmits pixel information corresponding to each scanning line (Y1 to Yn) to the data line (X
1 to Xn).

The boosting power supply circuit 90 is used, for example, together with the negative voltage generating circuit 80, and
0 is supplied with a predetermined voltage.

As described above, in the display device of the fourth embodiment, by mounting the booster circuit of the first embodiment as the booster power supply circuit 90, only a necessary portion of the display device can use the booster power supply. In a portion of the display device which does not require the use of the boosted power supply, a lower power supply voltage can be achieved. In addition, by using the booster circuit of the first embodiment, there is no drop in the threshold value of the boosted potential.
In the display device, it is not necessary to take a margin in consideration of the variation in the threshold characteristics of the transistor. Therefore, current consumption of the display device can be reduced. In the booster circuit according to the first embodiment, the pumping operation for generating the target voltage is performed every half cycle by the clock signal and the inverted clock signal, so that the pumping can be performed more efficiently. Thereby, in the display device of the fourth embodiment, the time until the output voltage reaches the target output voltage can be shortened, so that the boosted power supply can be started up quickly when the power supply is turned on.

Further, in the display device of the fourth embodiment, the counter electrode AC drive can be performed at a low power supply voltage by using the boosted power supply circuit 90 together with the negative voltage generation circuit 80. This makes it possible to lower the voltage of the input video signal, and as a result, lower power consumption. Note that the counter electrode AC drive refers to a driving method in which the amplitude of the video data signal is reduced to half by operating the other electrode (counter electrode) different from the one electrode of the display pixel PX to which the video data signal is applied. When the counter electrode AC drive is used, the potential of the video data signal may be negative depending on the potential of the counter electrode and the potential of the video data signal. In this case, when the gate potential of the active switching element ST is a positive potential, the switching transistor is turned on, so that it is necessary to apply a negative voltage to the scanning lines (Y1 to Yn). Therefore, in order to perform counter-electrode AC drive,
A negative voltage generation circuit 80 is required.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

For example, in the fourth embodiment, an example is shown in which the present invention is applied to a polysilicon TFT liquid crystal display device as a liquid crystal display device having a booster circuit. However, the present invention is not limited to this. It may be a device.

Further, in the fourth embodiment, an example in which the present invention is applied to a liquid crystal display device using a booster circuit has been described. However, the present invention is not limited to this, and the present invention is not limited to this.
The present invention is applicable to general display devices including other booster circuits such as display devices.

[0071]

As described above, according to the present invention, a boosted voltage can be generated without dropping by the threshold voltage of a transistor, so that there is no potential loss and
A booster circuit in which the ultimate boosted potential does not vary due to variations in transistor characteristics can be obtained. Also,
By performing the pumping operation for generating the target voltage every half cycle by the clock signal and the inverted clock signal, the time required to reach the target output voltage can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a boosting operation of the booster circuit of the first embodiment shown in FIG. 1;

FIG. 3 is a simulation diagram showing a relationship between time and an attained voltage when a threshold voltage of a transistor of the booster circuit of the first embodiment shown in FIG. 1 is changed.

FIG. 4 is a cross-sectional view showing a cross-sectional structure for achieving the booster circuit of the first embodiment.

5 is an equivalent circuit diagram corresponding to the cross-sectional structure shown in FIG.

FIG. 6 is a sectional view showing a sectional structure of a booster circuit according to a first modification of the first embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram corresponding to the cross-sectional structure of the first modified example shown in FIG.

FIG. 8 is a sectional view showing a sectional structure of a booster circuit according to a second modification of the first embodiment of the present invention.

FIG. 9 is a sectional view showing a sectional structure of a booster circuit according to a third modified example of the first embodiment of the present invention.

FIG. 10 is a sectional view showing a sectional structure of a booster circuit according to a fourth modification of the first embodiment of the present invention.

FIG. 11 is a circuit diagram showing a circuit configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 12 is a circuit diagram showing a circuit configuration of a booster circuit according to a third embodiment of the present invention.

FIG. 13 is a block diagram showing a display device including a booster circuit according to a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing an example of a booster circuit using a conventional capacitor.

[Explanation of symbols]

1, 2 Clock signal input terminal 3 Output terminal 50 Display unit 60 Scan line drive circuit 70 Data drive circuit 80 Negative voltage generation circuit 90 Boost power supply circuit (Boost circuit) CP1 Capacitor (First capacitor) CP2 Capacitor (Second capacitor) ND1 Node (first node) ND2 node (second node) NT1 n-channel transistor (first one conductivity type transistor) NT2 n-channel transistor (second one conductivity type transistor) NT3 n-channel transistor (third one conductivity type transistor) NT4 n-channel transistor (fourth first conductivity type transistor) PT1 p-channel transistor (first other conductivity type transistor) PT2 p-channel transistor (second other conductivity type transistor) PX display pixel ST active switching element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 27/08 321L 5H730 27/08 331 29/78 614 29/786 H02M 3/07 F term (Ref.) FF02 GG02 GG12 GG13 GG15 NN72 5H730 AA04 AA14 AS04 BB02 DD04 FG01 ZZ15

Claims (10)

[Claims] 1. A first capacitor and a second capacitor each having one terminal connected to a first node and a second node, respectively, one of a source terminal and a drain terminal connected to the first node, and the other. A first one conductivity type transistor connected to a power supply potential terminal; a first other conductivity type transistor having one of a source terminal and a drain terminal connected to the first node and the other connected to a voltage output terminal; One of a source terminal and a drain terminal is connected to the second node, and the other is connected to the power supply potential terminal.
A second transistor in which one of a source terminal and a drain terminal is connected to the second node and the other is connected to the voltage output terminal;
A first conductivity type transistor and the second other conductivity type transistor, wherein the voltage output terminals of the first other conductivity type transistor and the second other conductivity type transistor are commonly connected, and the first one conductivity type transistor and the first other conductivity type The gate terminals of the transistors are connected in common,
Connected to the second node, wherein the gate terminals of the second one conductivity type transistor and the second other conductivity type transistor are commonly connected,
A booster circuit connected to the first node, wherein clock signals having inverted phases are applied to the other terminals of the first capacitor and the second capacitor, respectively. 2. The booster circuit is formed on a P-type semiconductor substrate having a triple well structure, and the first and second one conductivity type transistors are formed on a P-type well as a field effect transistor. And the power supply potential terminal is connected to the P-type well to obtain the back gate potential. The first and second other conductivity type transistors are formed on an N-type well by a field effect transistor. And the voltage output terminal is connected to the N-type well in order to obtain the back gate potential. The first capacitor and the second capacitor are separately formed on the N-type well, respectively. The source terminal and the drain terminal of the other conductivity type transistor are connected in common, and the gate terminal is formed by the first node and the first node. The booster circuit according to claim 1, wherein the booster circuit is connected to the first node and the second node. 3. The booster circuit is formed on a P-type semiconductor substrate having a triple well structure, and the first and second one conductivity type transistors are formed on a P-type well as field effect transistors. And the power supply potential terminal is connected to the P-type well to obtain the back gate potential. The first and second other conductivity type transistors are formed on an N-type well by a field effect transistor. And the voltage output terminal is connected to the N-type well to obtain the back gate potential thereof. The first capacitor and the second capacitor are each separately formed on a P-type well. A source terminal and a drain terminal of a transistor of one conductivity type are connected in common, and the gate terminal is connected to the first node and the first node. The booster circuit according to claim 1, wherein the booster circuit is connected to the first node and the second node. 4. The booster circuit is formed on an N-type semiconductor substrate having a double well structure, and the first and second one conductivity type transistors are formed on a P-type well as field effect transistors. And the power supply potential terminal is connected to the P-type well to obtain the back gate potential. The first and second other conductivity type transistors are formed on an N-type well by a field effect transistor. And the voltage output terminal is connected to the N-type well to obtain the back gate potential thereof. The first capacitor and the second capacitor are each separately formed on a P-type well. A source terminal and a drain terminal of a transistor of one conductivity type are connected in common, and the gate terminal is connected to the first node and the first node. The booster circuit according to claim 1, wherein the booster circuit is connected to the first node and the second node. 5. The booster circuit is formed on an insulating film formed on a silicon substrate, wherein the first and second one-conductivity type transistors and the first
And a second other conductivity type transistor, wherein a semiconductor layer formed on the insulating film is formed as an active layer thereof, and at least one electrode of the first and second capacitors is formed on the semiconductor layer. 2. The booster circuit according to claim 1, wherein the booster circuit is formed by one of an n-type region and a p-type region. 6. The booster circuit is formed on a glass substrate or on an insulating film formed on the glass substrate, wherein the first and second one-conductivity type transistors and the first
And a second other conductivity type transistor, wherein a semiconductor layer formed on the glass substrate or the insulating film is formed as an active layer thereof, and at least one electrode of the first and second capacitors is The booster circuit according to claim 1, wherein the booster circuit is formed by one of an n-type region and a p-type region formed in the semiconductor layer. 7. A third one conductivity type transistor connected to each of the first node and the second node, one of a source terminal and a drain terminal, and a gate terminal connected to the power supply potential terminal. The booster circuit according to claim 1, further comprising: a four-conductivity-type transistor. 8. The boosting circuit according to claim 1, further comprising an inverter circuit for generating the clock signal having the inverted phase based on one clock signal. 9. A display pixel arranged in a matrix at an intersection of a plurality of scanning lines and a plurality of data lines, an active switching element provided for each display pixel and controlling an applied voltage of the display pixel, A display device comprising: a scanning line driving circuit that scans the plurality of scanning lines and applies a driving voltage for activating the active switching element; and a booster circuit that outputs a voltage to the scanning line driving circuit. The booster circuit includes: a first capacitor and a second capacitor each having one terminal connected to a first node and a second node; and one of a source terminal and a drain terminal connected to the first node. A first one conductivity type transistor having the other connected to a power supply potential terminal; one of a source terminal and a drain terminal connected to the first node; A first opposite conductivity type transistor connected to the pressure output terminal, one of a source terminal and a drain terminal connected to the second node, the second the other is connected to the power supply potential terminal
A second transistor in which one of a source terminal and a drain terminal is connected to the second node and the other is connected to the voltage output terminal;
A first conductivity type transistor and the second other conductivity type transistor, wherein the voltage output terminals of the first other conductivity type transistor and the second other conductivity type transistor are commonly connected, and the first one conductivity type transistor and the first other conductivity type The gate terminals of the transistors are connected in common,
Connected to the second node, wherein the gate terminals of the second one conductivity type transistor and the second other conductivity type transistor are commonly connected,
A display device, comprising: a booster circuit connected to the first node, wherein clock signals having phases inverted to each other are applied to the other terminals of the first capacitor and the second capacitor, respectively. 10. The at least boosting circuit is formed on a glass substrate or on an insulating film formed on the glass substrate. The first and second one-conductivity type transistors and the first
And a second other conductivity type transistor, wherein a semiconductor layer formed on the glass substrate or the insulating film is formed as an active layer thereof, and at least one electrode of the first and second capacitors is The display device provided with the booster circuit according to claim 9, wherein the display device is formed by one of an n-type region and a p-type region formed in a semiconductor layer.