KR100467709B1 - Heap Pump Circuit using Single Phase Clock and High Voltage Generator using the same - Google Patents

Abstract

The present invention relates to a heap pump circuit for generating a high voltage from a low supply voltage in a nonvolatile memory or the like and a high voltage generator using the same.

The heap pump circuit used in the present invention comprises one or more unit stages and one single phase pumping clock CLK for applying drive signals to the unit stages and output circuits, each unit stage having an input node Vi. ; An output node Vo; A third switch S3 and a pumping capacitor CP sequentially connected in series from an input node to an output node; A first switch S1 disposed between a first connection node N1 and a supply voltage V _DD between the pumping capacitor and an output node; And a second switch connected between the second connection node N2 and the ground GND positioned between the third switch and the pumping capacitor.

By using the hip pump circuit according to the present invention, it is possible not only to provide a high efficiency heap pump circuit having a high efficiency without a threshold voltage drop, but also to use an additional pulse reshaping by using a single phase clock. No reshaping circuit is required, and the clock driver can be easily and compactly implemented.

Description

Heap Pump Circuit using Single Phase Clock and High Voltage Generator using the same}

The present invention relates to a simple pump heap pump circuit, a high voltage generator using the same, and more particularly a heap pump circuit having a threshold voltage drop without using a single phase clock. And a high voltage generator using the same.

A circuit that pumps charge to produce higher voltages from a constant supply voltage is called a charge pump circuit. Such charge pump circuits are used to generate high voltages for programming or writing of data in non-volatile memories such as EPROMs or flash memories that must be driven at low voltages. It can also be used to drive low voltage switch capacitor circuits that require high voltage to drive analog switches, or electrostatic actuators.

This charge pump circuit is the oldest and most widely used Dickson type, which uses two non-overlapping clocks and a capacitor connected to a diode. However, Dixon type charge pump circuits use NMOS instead of diodes in practical implementations.

FIG. 1 shows the configuration of a Dickson charge pump circuit using an NMOS, and has a total of five stages.

The two pumping clocks φ1 and φ2 operate in different phases and have a voltage amplitude of Vφ. Vφ is determined to be the same as VDD, which is mainly a supply voltage, and the two clocks raise the charge voltage through the transistor through the coupling capacitors C ₁ to C ₄ . Ignoring the boundary effect, the voltage variation ΔV at each pumping node will be expressed by Equation 1 below.

Where C is the capacitance of C ₁ to C ₄ , C _S is the parasitic capacitance associated with each pumping node, f is the frequency of the pumping clock and I ₀ is the output current.

When φ ₁ moves from low to high, φ ₂ goes high and then low, the voltage at node 1 is stabilized at V ₁ + ΔV, and the voltage at node ₂ is stabilized at V ₂ . Where V ₁ and V ₂ are defined as steady state low voltages at node 1 and node 2, respectively.

MD1 and MD3 are reverse biased, so charge is pushed from node 1 to node 2 through MD2, and finally the voltage difference between node 1 and node 2 becomes equal to the threshold voltage of MD2. Therefore, the basic condition for charge pumping to work is that ΔV must be greater than the threshold voltage V _tn of the MOSFET.

The voltage pumping gain (Gain) in the second pumping step G _V2 is defined as a voltage difference between V ₂ and V ₁ , and may be expressed as Equation 2 below.

Here, V _tn (V ₂ ) is the threshold voltage of MD2 changed by the body effect due to the source voltage V ₂ .

Therefore, since the output drop by the threshold voltage occurs at each step of the charge pumping circuit, the overall gain is lowered, and too many steps are required to generate the required high voltage. In addition, a reverse charge-sharing phenomenon occurs, and the pumping efficiency drops drastically because the threshold voltage increases due to the trunk effect when a high voltage is generated.

FIG. 2 shows an example of the construction of a charge pump circuit called NCP-2, which has recently been proposed to compensate for this disadvantage.

This NCP-2 charge pump circuit utilizes a charge transition switch (CTS; MSi transistor), each MSi transistor being controlled by a pass transistor MPi. This approach allows the charge transfer switch to be turned off completely to prevent reverse charge flow if necessary, or to turn on and operate more efficiently in the event of a high voltage in the next step.

That is, by controlling the switch to turn on or off during the desired clock phase, the charge can only be pumped in one direction. In each pumping step, the high voltage level at the input is equal to the low voltage level at the output. Therefore, the voltage pumping gain for each step is expressed by Equation 3 below.

In addition, Jang Wingway et al. Published in 2001, "DC-DC charge pump using voltage doubler" (IEEE Transaction on Circuit and System; Vol 48, No. 3, March 2001) Voltage Doubler A charge pump circuit using is disclosed. Using this charge pump circuit, it is described that a voltage increase effect of up to 2 ⁿ times can be achieved in n steps.

Such a charge pump circuit without threshold voltage drop is called a "heap pump". However, using such a heap pump circuit can improve the voltage gain by preventing the threshold voltage from dropping in each pumping step, but there is still a disadvantage in that a clock having at least two different phases must be used.

SUMMARY OF THE INVENTION The present invention addresses these shortcomings and aims to develop a heap pump circuit using a single clock and having sufficient output gain and a high voltage generator using the same.

A summary of the above description is as follows.

As the size of a device such as a flash memory is reduced, the supply voltage V _DD of the nonvolatile memory using the floating gate device can be reduced to 1.5 V or less. Because electron tunneling through thin oxide is required for data storage, the tunneling voltage for programming and erasing operations cannot be reduced by V _DD .

Therefore, the high voltage generator around 1.5V is a very important technology for the development of low voltage flash memory. Basic limitations of the conventional charge pumping circuit include pumping gain-loss due to the drop in threshold voltage V _th and the body effect of the pass transistor.

Recently, a new type of charge pump circuit called heap-pump that does not generate a threshold voltage drop has been introduced into a negative voltage generator. The concept of positive hip pump circuits is also being used for word line boosting circuits. However, heap pumps for positive high voltage generators have not been proposed yet.

The present invention is directed to a heap pump circuit for positive high voltage generators having a single phase clock.

SUMMARY OF THE INVENTION An object of the present invention is to provide a charge pump circuit having a simple structure for use in a flash memory and the like and a high voltage generator using the same.

It is another object of the present invention to provide a high gain positive hip pump circuit and a positive high voltage generator using the same.

It is still another object of the present invention to provide a heap pump circuit in which a threshold voltage drop does not occur even with a single phase clock and a positive high voltage generator using the same.

Fig. 1 shows the configuration of a conventional Dickson charge pump circuit using an NMOS.

2 shows an example of the configuration of the NCP-2 charge pump circuit.

3 is a circuit diagram of a unit stage constituting each stage of the hip pump according to the present invention. FIG. 3A is a detailed circuit diagram of the unit stage, and FIG. 3B is equivalent to FIG. 3A. ) Shows a switch circuit diagram.

4 exemplarily shows a configuration of a hip pump circuit according to the present invention having four unit steps.

FIG. 5 is a graph showing a simulation result of the hip pump circuit according to FIG. 4, and shows the output value Vo4 of the last unit stage and the output value Vpp of the final output node by time (clock).

6 shows the structure of a pumping capacitor introduced for the simulation of a hip pump circuit according to the present invention.

7 and 8 show simulation results for the output voltage of the four-stage hip pump when the pumping capacitors CP are 10pF and 5pF, respectively.

9 shows, by supply voltage, the number of unit steps needed to obtain a final output voltage of 10V or more.

In order to achieve the above object, the hip pump circuit according to the present invention includes one or more unit stages, and one single phase pumping clock (CLK) for applying a drive signal to the unit stage and the output circuit,

Each unit step comprises an input node Vi; An output node Vo; A third switch S3 and a pumping capacitor CP sequentially connected in series from an input node to an output node; A first switch S1 disposed between a first connection node N1 and a supply voltage V _DD between the pumping capacitor and an output node; And a second switch connected between the second connection node N2 and the ground GND positioned between the third switch and the pumping capacitor.

In addition, the hip pump circuit may be further driven by the pumping clock described above, and may further include an output circuit for outputting a stable final output voltage (Vpp) by using the output voltage of the last unit stage as an input.

The first switch S1 is composed of one n-type MOSFET MN1 and two p-type MOSFETs MP1 and MP2, and the second switch S2 is one n-type MOSFET MN2. The third switch S3 may be configured of one p-type MOSFET MP3.

The pumping clock CLK may be applied to the gates of MN1, MN2, MP1, and MP3.

MN1, MP1, and MP2 constituting the first switch S1 are connected in the order of MP2, MP1, and MN1 from a supply voltage V _DD to ground, and the first connection node N1 is a drain of MP2. ) And the source of MP1 are connected.

The high voltage generator according to the present invention includes a hip pump having the above-described configuration, and is used to generate a high voltage required when performing a function of programming a nonvolatile memory, storing data, and the like.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a circuit diagram of a unit stage constituting each stage of the hip pump according to the present invention. FIG. 3A is a detailed circuit diagram of the unit stage, and FIG. 3B is equivalent to FIG. 3A. ) Shows a switch circuit diagram.

As shown in FIG. 3B, the unit steps constituting each step of the hip pump according to the present invention are largely divided into an input node Vi, an output node Vo, and a pumping capacitor CP disposed between the input node and the output node. And a first switch S1 connected between the pumping capacitor and the input node, a first switch S1 disposed between the first connection node N1 and the supply voltage V _DD between the pumping capacitor and the output node. And a second switch connected between the second connection node N2 positioned between the third switch and the pumping capacitor and the ground GND.

Each switch of FIG. 3B preferably comprises one or more MOSFETs. As shown in FIG. 3A, the first switch S1 is composed of one n-type MOSFET MN1 and two p-type MOSFETs MP1 and MP2. The second switch S2 may be configured as one n-type MOSFET MN2 and the third switch S3 may be configured as one p-type MOSFET MP3, but is not limited thereto.

Since MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used as a transistor manufactured by diffusing a source and a drain into a MOS capacitor formed by vertically stacking a metal gate, an oxide film, and a semiconductor, a detailed description thereof is omitted. do.

The pumping clock CLK is applied to the gates of MN1, MN2, MP1, and MP3. The pumping clock CLK may be a pulse having a frequency of several tens of Hz or more according to a required speed. In addition, although the amplitude of the clock causing the voltage rise can be arbitrarily adjusted as necessary, it is generally preferable to use the same voltage as the supply voltage V _DD . The pumping clock used in the present invention is a single clock having only one phase, unlike a conventional hip pump.

MN1, MP1, and MP2 constituting the first switch S1 are connected in the order of MP2, MP1, and MN1 from a supply voltage V _DD to ground, and the first connection node N1 is a drain of MP2. ) And the source of MP1 are connected.

CP is a pumping capacitor, the capacitance is preferably a few pF or more, but is not limited thereto, and may be arbitrarily adjusted as necessary.

The required output high voltage can be obtained by connecting multiple Unit Stages in series.

4 exemplarily shows a configuration of a heap pump circuit composed of four unit stages.

Four unit stages (first unit stage to fourth unit stage) are connected in series, supply voltage is applied to the input node of the first unit stage, and output nodes of the first to third unit stages are It is connected to the input node of the unit level.

In addition, an output circuit for outputting the voltage of the output node Vo4 of the fourth unit stage as the final output voltage Vpp is provided in the last stage.

One pumping clock is simultaneously applied to the first to fourth unit stages and the output circuit to provide an operation control signal for pumping.

Hereinafter, an operation state of the hip pump circuit will be briefly described.

The heap pump circuit as shown in FIG. 4 shows two operating states, one of which is a set-up state and the other of which is a pump-up state.

If the pumping clock CLK is high, MN1 and MN2 are turned on and MP3 and MP1 are turned off, so the heap pump is in the setup state. In the setup state, since the gate voltage of MP2 is zero, the pumping capacitor CP is precharged to the supply voltage V _DD without a threshold voltage drop.

On the contrary, when the pumping clock CLK is low, the heap pump is pumped up because MN1 and MN2 are turned off and MP3 and MP1 are turned on. During the pump-up state, the gate voltage of MP2 becomes equal to the output node voltage of each stage, and the gate voltage of MP3 in each stage becomes zero. Thus, the hip pump does not experience a voltage drop of the threshold voltage magnitude of the series switching transistor.

The output value of the second unit stage is accumulated on the output value of the first unit stage, and the high voltage is obtained at the output node of the last stage through a series of processes in which the output value of the third unit stage is accumulated on the output value of the second unit stage.

In order to obtain the final output voltage Vpp from the output node Vo4 of the last stage (fourth unit stage), one output circuit is needed between the output node Vo4 of the last stage and the final output node Vpp. . That is, due to the operation of the pumping clock, the output voltage in the last stage also has a pulse form that toggles between the high voltage and 0V for each clock period. An output circuit is needed to convert such pulsed high voltage into a stable output voltage.

The output circuit includes four p-type MOSFETs MPo1 to MPo4 and one capacitor Cg, as shown by a dotted line rectangle in FIG. 4.

In the setup state, the gate voltage of MPo3 is charged through MPo4 to the final output voltage (Vpp) level, and in the next pump-up state, the gate voltage of MPo3 moves to near the Vpp-V _DD level so that MPo4 is turned off and MPo3 is turned on. do. Thus, the voltage at node Vo4 is delivered to the final output node.

The nwell voltage of the pMOSFET in the output circuit has the highest potential in the circuit by the cross-connected transistors MPo1 and MPo2.

FIG. 5 is a graph showing a simulation result of the hip pump circuit according to FIG. 4, and shows the output value Vo4 of the last unit stage and the output value Vpp of the final output node by time (clock).

As shown, it can be seen that after about 10 clock cycles have elapsed, the final output voltage Vpp is brought to a steady state of about 11V.

6 shows the structure of a pumping capacitor introduced for the simulation of a hip pump circuit according to the present invention.

As shown, the pumping capacitor Cp was formed in a PIP structure on a field oxide of 4000 kV. The capacitance of the nwell junction was given by Cj of 0.10fF / μm ² and Cjsw of 0.97fF / μm ² , respectively. These capacitors use a floating Nwell structure that can reduce parasitic capacitors.

In addition, the hip pump circuit according to the present embodiment is designed as 0.6μm Hynix MPW.

7 and 8 show simulation results for the output voltage of the four-stage hip pump when the pumping capacitors CP are 10pF and 5pF, respectively.

For the simulation, in the case of the NMOS, the threshold voltage (V _th) of 0.74V, for a PMOS transistor, the model of a 0.6μm CMOS technology having a threshold voltage (V _th) of -0.86V was used, the clock frequency is 10MHz It was set as. The simulation results show that the final output (Vpp) of the hip pump is about 85% of the ideal gain of (N + 1) × V _DD without considering the parasitic field oxide (FOX) capacitance. Where N is the number of steps.

Considering the parasitic field oxide (Fox) capacitance, the pumping efficiencies with and without the floating nwell structure were 73% and 63% of the ideal gain values, respectively.

In the absence of parasitic field oxide (Fox) capacitance, the main factor in which pump efficiency is outlier and the main factor is considered to be the Enwell junction capacitance of MP1, MP2, and MP3 at the unit stage and the voltage loss at the output stage.

In the graph, "□" is an ideal PIP structure, "■" is a floating Nwell structure under a parasitic field oxide (Fox) state, and "○" represents a simulation result when there is no floating enwell.

As can be seen from the waveform of FIG. 5, there is a difference of about 1V between the final output voltage Vpp and the output voltage Vo4 of the last stage. Since Enwell is deflected to the highest potential in the circuit, the threshold voltage of MPo3 while on is about 4V.

Since the device of this example was not optimized to best fit the pump, the voltage loss due to MPo3 was quite large. Thus, optimizing device parameters could further improve voltage losses at the output stage. Considering the voltage gain of the last unit stage Vo4 instead of the output voltage Vpp through the output circuit, it is about 90% of the ideal PIP outlier. The difference between the outliers and about 10% is thought to be due only to the Enwell junction capacitances of MP1, MP2, and MP3. Floating enwell junctions under field oxide can improve pumping efficiency by about 10% compared to structures without floating wells.

9 shows, by supply voltage, the number of unit steps needed to obtain a final output voltage of 10V or more.

As can be seen in FIG. 9, the number of steps for producing a final output voltage Vpp higher than 10V is not constantly inversely proportional to the supply voltage below 1.5V. The simulation results indicate that in operation below 1.5V, the CP cannot be fully charged to V _DD during the setup state of 100 nsec because the On capacitance of the MOSFET is too small.

As described above, when the hip pump circuit according to the present invention is used, it is shown that the efficiency is close to about 90% of the ideal gain value even when the circuit element is not optimized.

In addition, since only one clock of a single phase is used, it is easy to implement and control. That is, the pulse reshaping circuit, which is necessary in the conventional circuit having the two-phase or four-phase control clock, is not necessary, and the clock driver can be made smaller than the conventional one.

As described above, the present invention provides a positive high voltage generator hip pump circuit without a threshold voltage drop.

Since the hip pump according to the present invention is a single phase circuit, an additional pulse reshaping circuit for timing difference between input pulses, which is necessary in the conventional circuit having a two-phase or four-phase control clock. Is not necessary. In addition, since the pulse CLK does not drive the pumping capacitor, the clock driver may be smaller than before.

At the same time, it is possible to provide a hip pump circuit with a good efficiency of approaching the voltage pumping gain to 90% of the outlier.

Claims (12)

One or more unit steps and one single phase pumping clock (CLK) for applying a drive signal to each unit step, Each unit step, (a) Input node (Vi) (b) output node (Vo) (c) a third switch (S3) and a pumping capacitor (CP) connected in series from the input node to the output node. (d) a first switch S1 disposed between a first connection node N1 and a supply voltage V _DD between the pumping capacitor and an output node; (e) a high voltage generation heap using a single phase clock, characterized in that it comprises a second switch connected between the second connection node (N2) and ground (GND) located between the third switch and the pumping capacitor. Pump circuit. The method of claim 1, And an output circuit driven by the pumping clock to output a stable final output voltage Vpp by using the output voltage of the last unit stage as an input. Pump circuit. The method according to claim 1 or 2, The first switch S1 is composed of one n-type MOSFET MN1 and two p-type MOSFETs MP1 and MP2. The second switch S2 is composed of one n-type MOSFET MN2. The third switch (S3) is a high voltage generation heap pump circuit using a single phase clock, characterized in that consisting of one p-type MOSFET (MP3). delete The method of claim 3, wherein And the pumping clock is applied to gates of MN1, MN2, MP1, and MP3. The method of claim 3, wherein MN1, MP1, and MP2 constituting the first switch S1 are connected in the order of MP2, MP1, and MN1 from a supply voltage V _DD to ground. The first connection node (N1) is a high voltage generation heap pump circuit using a single phase clock, characterized in that located in the portion where the drain (Drain) of MP2 and the source (Source) of MP1. To generate a high voltage from a low supply voltage (V _DD ), (1) (a) input node (Vi), (b) output node (Vo), and (c) third switch (S3) and pumping capacitor (CP) sequentially connected in series from input node to output node. And (d) a first switch S1 disposed between the first connection node N1 and the supply voltage V _DD between the pumping capacitor and the output node, and (e) the third switch and the pumping capacitor. At least one unit step comprising a second switch connected between a second connection node (N2) and a ground (GND) interposed therebetween, (2) a high voltage generator using a single phase clock, characterized in that it comprises a hip pump circuit comprising one single phase pumping clock (CLK) for applying a drive signal to each unit step. The method of claim 7, wherein And an output circuit driven by the pumping clock to output a stable final output voltage (Vpp) by using the output voltage of the last unit stage as an input. The method according to claim 7 or 8, The first switch S1 is composed of one n-type MOSFET MN1 and two p-type MOSFETs MP1 and MP2. The second switch S2 is composed of one n-type MOSFET MN2. High voltage generator using a single phase clock, characterized in that the third switch (S3) is composed of one p-type MOSFET (MP3). delete The method of claim 9, The pumping clock is a high voltage generator using a single phase clock, characterized in that applied to the gate of MN1, MN2, MP1 and MP3. The method of claim 9, MN1, MP1, and MP2 constituting the first switch S1 are connected in the order of MP2, MP1, and MN1 from a supply voltage V _DD to ground. The first connection node (N1) is a high voltage generator using a single phase clock, characterized in that located in the portion connected to the drain (Drain) and the source of the MP1 (MP1).