I331838 ' 第95M5950號專利說明書修正本 饮γ - 修正曰期：99.8.9 九、發明說明： 【發明所屬之技術領域】 • 本發明為一種直流電壓轉換器’特別是一種 一 膜電晶體之充電泵積體电路所形成的直流電墨轉換哭― 【先前技術】 在顯示器中，直流電壓轉換器用以降低顯示， 面控制晶片所需之電源電壓’故對於顯示恶沾V ^統介 只不态的效能來說 是一個很重要的部分。以往的設計上會將直流電壓轉 器設計在另外的電路板上，再與顯示面板連接。^在^ 量化與節省成本的考量下’目前在顯示電路整合中，二 流電壓轉換器（DC-DC converter)亦可以整合至顯示面板 中’因而減少控制晶片之製造成本。舉例來說，#由使^ 用薄膜電晶體來形成驅動電路並整合至顯示面板中，_ 示模組的製造成本及出貨時間（time-to-market)將可大大 地減少。然而，薄膜電晶體不佳的特性，例如高臨界電 壓（Vt)及低載子移動率（mobility)，使得薄膜電晶體所構 成之DC-DC轉換器的功率效益會低於金氧半電晶體所構 成之DC-DC轉換器。 一般來5兒’傳統DC-DC轉換态分成切換式穩屋器及 充電泵（charge pump)電路，其中因為切換式穩壞哭通a 係為會產生諧波干擾的RLC電路，因此充電栗吊 电路相較 之下’比較適合與面板進行整合。充電果電路又了^、 為Dickson型’如第la圖與第lb圖中所示，以Ώ 刀 Α及切換電 0773-A32084TWF2(2010〇610) 5 1331838 第95145950號專利說明書修正本 修正曰期：99.8.9 witching capacit0_。然而’由於薄膜電晶體具有較 高的臨界電壓，使得Dickson型充電泵電路會具有很大的 電晶體切換損失，且電容的充放電時間較長，因而降低 它整個的轉換效率。雖亦有人提出改良的以也⑽型充電 泵電路’來改善其功率轉換效益，但該型充電栗電路的 電路複雜度高，增加電路佈局的面積且相當難以驅動。 【發明内容】 本發明的目的為提供一種充電泵直流電壓轉換電 路，可減少功率損耗亦可避免充電泵直流電壓轉換電路 中電容充放電所造成的電壓不穩的問題。 本發明提供一種直流電壓轉換電路，用以將一輸入 電壓轉換成一輸出電壓’包括一第一主要充電泵電路、 一第一次級充電泵電路、一第二主要充電泵電路以及一 第二次級充電泵電路。該第一主要充電泵電路，受控於 恭第時脈仏號，用以將該輸入電壓轉化為一第一提升 包壓。該第一次級充電泵電路，受控於一第二時脈信號， 輕接該第-主要充電泵電路，用以將該第—提升電壓轉 換為該輸出電壓。該第二主要充魏電路，受控於該第 ^時脈信號，用以將該輸入電壓轉化為一第二提升電 壓。該第二次級充電泵電路，受控於該第一時脈信號， 耦接該第一主要充電泵電路，用以將該第二提升電壓轉 換為該輸出電壓。 【實施方式】 〇773-A32084TWF2(20100610) 6 1331838 第95】45950號專利說明書修正本 " 修正日期：99.8.9 第一2a圖係為本發明之直流電壓轉換電路之第一實 施例的示意圖。直流電難換電路2〇包括並聯連接卜 fr主要充電泵電路m級充電泵電路23、-主要充電泵電路22以及―第二次級充電I電路 =將輸入電塵轉Vdd換成一輸出電塵輪出至一 Ϊ二如一液晶顯示器。第-主要充電泵電路2!會將輸 入^堊vDD轉換成一第一提升電壓ν】，並且產生一第一 ;制信號S1輪出至第二主要充電栗電路22。第一次級充 = 一會f第一主要充電泵電路21的輸出電壓V, 至第：二：提升電M %，並產生-第三控制信號S3 =第=、.及充電栗電路24。第二主要充電泵電路22會將 3入、VDD.換成一第二提升電壓並且產生一第 一控制信號S2輸出至第一充電泵電路22。第二次級充電 會，第二主要充電泵電路22的輸出電壓V2轉 」:幼右^提升電壓％並產生一第四控制信號S4至第 一 \級充電泵電路23。 第 主要充電栗電路21、22會根據第-時脈 -裎U CLK2’父替地輸出第一、第 ^升巷壓。第-次級充電泵電路23與第二次級充電泵 ” 24會根據第—時脈㈣c ⑽’交替地輸出第三、第四提升電二 脈信號⑽的㈠脈㈣⑽與第二時 主要充電粟電二-=號S1會禁能第二 之輸出，弟二控制信號S2會禁能第 〇773-A32084TWF2(201〇〇6l〇) 7 第95145950號專利說明書修正本 修正日期：99.8.9 笔，果電路21之輸出’第三控制信號S3會草能 弟一-人級充電泵電路24之銓 能第—次級充以電路2^=弟四控制信號S4會禁 硌23之輸出。於本發明中，第一' 23：24" 壓轉換7方所輪出控制信號所控制，使得直流電 :、不而額外的控制電路。在本實施例中，控制 #號为別^其對應的充電泵電路的輸出電壓。 * 本貝施例中’第—次級充電栗電路23與第二次級 充電栗電路24更可搞接造制 〜㈣㈣I 個第—次級充電泵電路與第 —人、 …路’用以提高輪出電壓的電壓值。在本 :，例：’第-次級充電果電路23可提 2 =，第二次級充電栗電路24可提升π%)的電壓。 t第一次級充電I電路23再輕接—第—次級充電栗電 路’則輸出電壓Vl便可提升為（2V3-V])。同理，若第 二:級充電泵電路24再搞接一第二次級充電泵電路 輸出電壓^便可提升為（2W2)。利用這樣的方式'， 便可使得直流電_換電路的輸出電壓有更多的變化， 且可提供更大的輸出電壓給所需要的電路使用。 第2b圖係為第2a圖的直流電壓轉換電路之控制作 =的示意圖。在第-週期P1中，第二主要充電泵電路^ 輸出第二提升電1 %至第二次級充電泵電路24中，此 時第人、、及充電泵電路23則根據前一週期接收到第一主 要充電泵電路21輸出第—提升電壓A，輸出第三提升· 壓v”在第二週期打中，第一主要充電栗電路21輸= 8 0773-A32084T WF2(2010061 〇) 1331838 第95M5950號專利說明書修正本 修正日期：99.8.9I331838 'Patent No. 95M5950 Revised to Drink γ - Revision Period: 99.8.9 IX. Description of the Invention: [Technical Field of the Invention] The present invention is a DC voltage converter 'in particular, a film transistor charging The DC ink formed by the pump integrated circuit is switched to crying. [Prior Art] In the display, the DC voltage converter is used to reduce the display and control the power supply voltage required for the wafer, so it is only for the display of the evil. Performance is an important part. In the past, the DC voltage converter was designed on another circuit board and connected to the display panel. ^ Under the consideration of quantization and cost saving, 'currently in the display circuit integration, the DC-DC converter can also be integrated into the display panel' thus reducing the manufacturing cost of the control chip. For example, by using a thin film transistor to form a driving circuit and integrating it into a display panel, the manufacturing cost and time-to-market of the module can be greatly reduced. However, the poor characteristics of thin film transistors, such as high threshold voltage (Vt) and low carrier mobility, make the power efficiency of the DC-DC converter composed of thin film transistors lower than that of gold oxide semi-transistors. The DC-DC converter is constructed. Generally, the traditional DC-DC conversion state is divided into a switching type stable house and a charge pump circuit. Among them, because the switching type is stable, the crying is a RLC circuit that generates harmonic interference, so the charging chest hoist The circuit is more suitable for integration with the panel. The charging fruit circuit is again ^, for the Dickson type, as shown in the first and second lb diagrams, the 曰 Α Α and the switching electric 0773-A32084TWF2 (2010 〇 610) 5 1331838 No. 95145950 patent specification to amend this revision period :99.8.9 witching capacit0_. However, due to the higher threshold voltage of the thin film transistor, the Dickson type charge pump circuit has a large transistor switching loss, and the charge and discharge time of the capacitor is long, thereby reducing its overall conversion efficiency. Although an improved (10) type charge pump circuit has been proposed to improve its power conversion efficiency, the circuit of this type of charge pump circuit has a high circuit complexity, increases the area of the circuit layout, and is relatively difficult to drive. SUMMARY OF THE INVENTION An object of the present invention is to provide a DC voltage conversion circuit for a charging pump, which can reduce power loss and avoid voltage instability caused by charging and discharging of a capacitor in a DC voltage conversion circuit of a charging pump. The present invention provides a DC voltage conversion circuit for converting an input voltage into an output voltage 'including a first primary charge pump circuit, a first secondary charge pump circuit, a second primary charge pump circuit, and a second time Level charge pump circuit. The first primary charge pump circuit is controlled by the Christie clock nickname to convert the input voltage into a first boost package voltage. The first secondary charge pump circuit is controlled by a second clock signal, and is connected to the first-primary charge pump circuit for converting the first boost voltage to the output voltage. The second main charging circuit is controlled by the second clock signal for converting the input voltage into a second boosting voltage. The second secondary charging pump circuit is controlled by the first clock signal and coupled to the first primary charging pump circuit for converting the second boosting voltage to the output voltage. [Embodiment] 〇 773-A32084TWF2 (20100610) 6 1331838 95th] 45950 Patent Specification Revisions " Amendment Date: 99.8.9 The first 2a diagram is a schematic diagram of the first embodiment of the DC voltage conversion circuit of the present invention. . The DC refractory circuit 2 〇 includes a parallel connection, a main charge pump circuit, a m-stage charge pump circuit 23, a main charge pump circuit 22, and a second secondary charge I circuit, which converts the input dust to Vdd into an output dust. Take turns to a LCD monitor. The first-main charge pump circuit 2! converts the input 垩vDD into a first boost voltage ν] and generates a first; the signal S1 is rotated to the second main charge circuit 22. The first secondary charging = the output voltage V of the first primary charging pump circuit 21, to the second: boosting power M%, and generating - the third control signal S3 = the first, and the charging circuit 24 . The second primary charge pump circuit 22 converts 3 input, VDD. to a second boost voltage and produces a first control signal S2 for output to the first charge pump circuit 22. The second secondary charging will, the output voltage V2 of the second primary charge pump circuit 22 is turned "up" and the fourth control signal S4 is generated to the first \ -stage charge pump circuit 23. The first main charging circuit 21, 22 outputs the first and second rising lane pressures according to the first-clock-裎U CLK2' parent. The first-secondary charge pump circuit 23 and the second secondary charge pump "24" alternately output the (a) pulse (four) (10) of the third and fourth boosted electric two-pulse signals (10) and the second-time main charge according to the first-time clock (four) c (10)' Su 2 -= S1 will disable the second output, the second control signal S2 will be disabled 〇773-A32084TWF2 (201〇〇6l〇) 7 Patent No. 95145950 revised this amendment date: 99.8.9 pen The output of the fruit circuit 21 'the third control signal S3 will be the grass-powered one - the human-level charge pump circuit 24 can be the first - the secondary charge circuit 2 ^ = the fourth control signal S4 will block the output of 23 . In the present invention, the first '23:24" pressure conversion 7-station rotation control signal is controlled so that the direct current: no additional control circuit. In this embodiment, the control ## is the corresponding charging The output voltage of the pump circuit. * The first-second charge pump circuit 23 and the second secondary charge circuit 24 can be made in the present embodiment. (4) (4) I-secondary charge pump circuit and the first person , ... road 'to increase the voltage value of the wheel voltage. In this:, for example: 'the first-secondary charge 23 can raise 2 =, the second secondary charging circuit 24 can increase the voltage of π%). t The first secondary charging I circuit 23 is lightly connected - the first-second charging circuit can increase the output voltage Vl For the same reason, if the second: level charge pump circuit 24 is connected to a second secondary charge pump circuit output voltage ^, it can be upgraded to (2W2). In this way, The output voltage of the DC-changing circuit is changed more, and a larger output voltage can be provided for the required circuit. Figure 2b is a schematic diagram of the control of the DC voltage conversion circuit of Figure 2a. In the first period P1, the second main charge pump circuit outputs a second boost power of 1% to the second secondary charge pump circuit 24, at which time the first person and the charge pump circuit 23 receive the first according to the previous cycle. A main charge pump circuit 21 outputs a first boost voltage A, and a third boost voltage v is output in the second cycle. The first main charge circuit 21 outputs = 8 0773-A32084T WF2 (2010061 〇) 1331838 95M5950 Patent Specification Amendment Revision Date: 99.8.9
第一提升電愿V V2至第一次級充電泵電路23中 二次級充電泵雷牧” 此野弟 雪$命 路24則根據第一週期P1接收到第二主 壓％ /电路22輸出第二提升電屢V2’輸出苐四提升電 在上述的實施例中，第一充電泵電路21盥 泵電路22分別口鉉垃笙 ^ ^ ^ ，、弟一兄電 刀乃h、耦接第一次級充電泵電路23與第二 級充電泵電路24 电峪Μ，而在貫際應用上，可在 泵電路23與第二次級 * 吸死電泵電路24之後分別耦接複數 夂、'充電泵電路23與第二次級充電泵電路24，如 此輸出電壓Vl提升至更高。在本發明一實施例 中1ΓΓ第—次級充電栗電路23與第二次級充電栗電路 24月匕提升的電壓大小與其耗接電壓源輸出的㈣大小有 關。 第3a圖為本發明之直流電壓轉換電路之第二實施 例的示⑦目直流電壓轉換電路包括第—反相器3卜第 一主要充電泵電路35、第二反相器32、第二主要充電泵 電路％、第二反相器33、第—次級充電泵電路η、第四 反相器34以及第二次級充電泵電路％。 第一主要充電泵電路35中，電晶體丁4具有一第一 源/没極、-第二源/汲極以及__，纟中第—源/没極 躺接電源vDDm軸接端點A1，閘軸接端點 A2。電晶體T3具有一第一源/汲極、一第二祕極以及 一閘極’其中第一源/汲極耦接端點入卜第二源/汲極耦 接第一次級充電泵電路37,閘極耦接端點A2。第一電容 〇773-A32084TWF2(20100610) 9 1331838 第95145950號專利說明書修正本The first boosting power V V2 to the secondary charging pump in the first secondary charging pump circuit 23 is the second stage charging pump. The wilderness snow $24 receives the second main pressure % / circuit 22 output according to the first period P1. The second boosting power is repeated V2' output and the fourth boosting power is in the above embodiment. The first charging pump circuit 21 and the pump circuit 22 respectively 铉 笙 ^ ^ ^ , , , , , , , , , , , , , , , , , , , , A secondary charge pump circuit 23 is electrically coupled to the second stage charge pump circuit 24, and in a continuous application, a plurality of turns can be coupled between the pump circuit 23 and the second secondary*sucker pump circuit 24, respectively. 'Charge pump circuit 23 and second secondary charge pump circuit 24, such that the output voltage V1 is raised to a higher level. In one embodiment of the invention, the first-secondary charge circuit 23 and the second secondary charge circuit are 24 months. The magnitude of the boosted voltage is related to the size of the (fourth) output of the voltage source. Fig. 3a is a diagram showing the second embodiment of the DC voltage conversion circuit of the present invention. The 7th DC voltage conversion circuit includes a first inverter 3 Main charge pump circuit 35, second inverter 32, second main charge pump circuit% a second inverter 33, a second-stage charge pump circuit η, a fourth inverter 34, and a second secondary charge pump circuit %. In the first main charge pump circuit 35, the transistor 4 has a first Source / immersion, - second source / drain and __, the first source / source is connected to the power supply vDDm axis terminal A1, the gate is connected to the end A2. The transistor T3 has a first source / a first source/drain terminal is coupled to the second source/drain to the first secondary charge pump circuit 37, and the gate is coupled to the terminal A2. The first capacitor 〇773-A32084TWF2(20100610) 9 1331838 No. 95145950 patent specification amendment
修正曰期：99.8.9 端轉接第一反相器31的輸出端，另一端輕接端 第 源/没極 主要充電泵電路36中’電晶體丁8具有一第一 /第二源/汲極以及-閘極，Λ巾第—源 源vDD ,第二源/汲極耦接端點Α2，閘極耦接端點 Α卜電晶體Τ7具有—第—源/祕、—第二源續極以及 一，極’其中第一源/没極耗接端‘點A2，第二源/汲極輕 接第二次級充電泵電路％，閘軸接端點A卜第二電容 。的-端耦接第二反相器32的輸出端’另一 點A2。 第一次級充電泵電路37中，電晶體T9具有一第一 源/没極、-第二源/汲極以及—閘極，#中第—源/沒極 福接電晶體Τ3的第二源/㈣’第二源/祕㈣端點χ， 問極輕接端點Υ。第三電容C3 #-端輕接第三反相器33 的輸出端，另一端耦接端點X。電晶體T1〇具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接端點X，第二源/汲極耦接一負载，閘極耦接端點γ。 第二次級充電泵電路38中，電晶體T11具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接電晶體T7的第二源/汲極，第二源/汲極耦接端點γ， 閘極耦接端點X。第四電容C4的一端耦接第四反相器34 的輸出端，另一端耦接端點Y。電晶體τ】2具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接端點Υ，第二源/汲極耦接一負載，閘極耦接端點χ。 〇773-A32084TWF2(20i00610) 10 1331838 • · 第95145950號專利說明書修正本 修正日期：99.8.9 在第3a圖中，第一電容C1與第二電容C2儲存有 電壓VDD，而第一主要充電泵電路35與第二主要充電泵 電路36則根據第一時脈信號CLK1與第二時脈信號 CLK2，交替的輸出2VDD的電壓到第一次級充電泵電路 • 37或第二次級充電泵電路38。第三電容C3與第四電容 C4儲存有電壓2VDD，而第一次級充電泵電路37與第二 次級充電泵電路38則根據第一時脈信號CLK1與第二時 脈信號CLK2，交替的輸出3VDD的電壓到負載。 第3b圖為本發明之直流電壓轉換電路之第三實施 例的示意圖。與第3a圖不同處在於反相器皆以電晶體表 示，其餘相似部分則不再贅述。爲更清楚說明第3b圖的 動作，請參考第3c圖。第3c圖為第3b圖之直流電壓轉 換電路之輸出波形示意圖。 於第一週期P1時，時脈信號CLK1、CLK2分別為 HIGH與LOW。電晶體ΤΙ、T6、T13、T16會截止，而 電晶體T2、T5、T14、T15會導通，使得端點B1與D1 上之電壓為0，節點B2與D2上之電壓為VDD。由於第 一電容C1與第二電容C2儲存有VDD的電壓，故端點 A1上之電壓為VDD，而端點A2上之電壓為2VDD。 由於端點A1的電壓為VDD而端點A2的電壓為 2VDD，所以電晶體T4、T7會導通，而電晶體T3、T8 會截止。由於端點D2上之電壓為VDD，且儲存在電容 C3中的電壓為2VDD，故端點X上之電壓為3VDD之電 壓。另外由於端點D1接地及儲存在電容C4中之電壓 0773-A32084TWF2(20100610) 11 1331838 修正日期：99.8.9 第95145950號專利說明書修正本 (2 VDD)，節點Y上之電壓為2 VDD。因為端點X的電壓 為3VDD而端點Y的電壓為2VDD，所以電晶體T9、T12 會截止，而電晶體Τ10、Τ11會導通，使得第一次級充電 泵電路37輸出3VDD電壓至負載。此時，由於電晶體 Τ12會因為來自第一次級充電泵電路37之輸出電壓而截 止，所以第二次級充電泵電路38之輸出會被禁能 (disable) ° 於第二週期P2時，時脈信號CLK1、CLK2分別為 LOW與HIGH。電晶體T卜T6、T13、T16會導通，而 電晶體T2、T5、T14、T15會截止，使得端點B1與D1 上之電壓為VDD，節點B2與D2上之電壓為0。由於第 一電容C1與第二電容C2儲存有VDD的電壓，故端點 A1上之電壓為2VDD，而端點A2上之電壓為VDD。 由於端點A1的電壓為2VDD而端點A2的電壓為 VDD，所以電晶體T3、T8會導通，而電晶體T4、T7會 截止。由於端點D1上之電壓為VDD，且儲存在電容C4 中的電壓為2 VDD，故端點Y上之電壓為3 VDD之電壓。 另外由於端點D2接地及儲存在電容C3中之電壓 (2VDD)，節點X上之電壓為2 VDD。因為端點X的電壓 為2VDD而端點Y的電壓為3VDD，所以電晶體T10、 T11會截止，而電晶體T9、T12會導通，使得第二次級 充電泵電路38輸出3VDD電壓至負載。此時，由於電晶 體T10會因為來自第二次級充電泵電路38之輸出電壓而 截止，所以第一次級充電泵電路37之輸出會被禁能 0773-A32084TWF2(20100610) 12 1331838 • 第95145950號專利說明書修正本 修正日期：99.8.9 (disable) ° 因此，於直流電壓轉換電路中，第一主要充電泵電 路35與第二主要充電泵電路36會交替地輸出一 2VDD 的電壓作為一提升電壓至第一次級充電泵電路37與第二 " 次級充電泵電路38中，並且第一主要充電泵電路35與 第二主要充電泵電路36會交替地被第一控制信號S1與 第二控制信號S2所禁能，第一次級充電泵電路37與第 二次級充電泵電路38會交替地被第三控制信號S3與第 四控制信號S4所禁能。換句話說，直流電壓轉換電路係 用以將輸出電壓VDD轉換成3VDD之提升電壓（boosted voltage)Vo ° 在上述的實施例中，第一充電泵電路35與第二充電 泵電路36分別只耦接第一次級充電泵電路37與第二次 級充電泵電路38，而在實際應用上，可在第一次級充電 泵電路37與第二次級充電泵電路38之後分別耦接複數 個第一次級充電泵電路37與第二次級充電泵電路38,如 此一來可將輸出電壓V。提升至更高。在本實施例中，第 一次級充電泵電路37與第二次級充電泵電路38皆可將 所接收到的電壓提升VDD的大小（亦即輸入電壓的大 小），因此若串接N個第一次級充電泵電路37與第二次 級充電泵電路38時，輸出電壓V。的大小為（2+N)VDD。 第4a圖為本發明之直流電壓轉換電路之第四實施 例的示意圖。直流電壓轉換電路包括第一反相器41、第 一主要充電泵電路45、第二反相器42、第二主要充電泵 0773-A32084TWF2(20100610) 13 1331838 修正日期：99.8.9 第95145950號專利說明書修正本 電路46、第二反相器43、第一次級充電系電路47、第四 反相器44以及第二次級充電泵電路48。與第3a圖不同 的是原先的電壓源替換為接地，原先的接地替換為電壓 源，原先的PMOS電晶體與NM0S電晶體也分別替換為 NMOS電晶體與pm〇S電晶體。 第一主要充電泵電路45中，電晶體丁4具有一第一 源/沒極、一第二源/沒極以及一閘極，其中第一源/汲極 接地帛—;原/及極_接端點A1，閘極搞接端點Μ。電 晶體Τ3具有-第—源及極、—第二源/汲極以及一間 極，其中第-源/沒極搞接端點八卜第二源/沒極麵接第 一次級充電泵電路47,閘極耦接端點Α2。第一電容q 二一端_一反相器41的輪出端，另-端_點 ,、第一主要充電泵電路46中，電晶體丁8具有一第一 極、-第二源/祕以及1極，其中第—源/没極 接，第-源/沒極輕接端點A2，閉極轉接端點Μ 曰曰0體T7具有一第一源/没極、—第二源/汲極以： 極：其中第-源/汲極轉接端點A2，第二源 二次級充電泵電路48，閘軸接魅a卜第弟 的一端耦接第二反相器42的輪 A2。 銜出碥，另一端耦接端點 第一次級充電泵電路47中，Correction period: 99.8.9 end is switched to the output end of the first inverter 31, and the other end is lightly connected to the first source/no pole main charge pump circuit 36. The transistor D8 has a first/second source/ Bungee and - gate, wiper - source vDD, second source / drain coupled to terminal Α2, gate coupled to the end of the transistor Τ7 has - first source / secret, - second source continued The pole and the first pole, wherein the first source/no pole is connected to the end point A2, the second source/drain is lightly connected to the second secondary charging pump circuit %, and the gate is connected to the terminal A to the second capacitor. The end of the second inverter 32 is coupled to the other end A2. In the first secondary charging pump circuit 37, the transistor T9 has a first source/depolarization, a second source/drain and a gate, and a second source of the first source/sourceless transistor Τ3 Source / (four) 'Second source / secret (four) endpoint χ, ask very lightly connected to the endpoint Υ. The third capacitor C3 is lightly connected to the output end of the third inverter 33, and the other end is coupled to the end point X. The transistor T1 has a first source/drain, a second source/drain, and a gate, wherein the first source/drain is coupled to the terminal X, and the second source/drain is coupled to a load, the gate The pole is coupled to the terminal γ. In the second secondary charging pump circuit 38, the transistor T11 has a first source/drain, a second source/drain, and a gate, wherein the first source/drain is coupled to the second source of the transistor T7. / bungee, the second source/drain is coupled to the terminal γ, and the gate is coupled to the terminal X. One end of the fourth capacitor C4 is coupled to the output end of the fourth inverter 34, and the other end is coupled to the end point Y. The transistor τ 2 has a first source/drain, a second source/drain, and a gate, wherein the first source/drain is coupled to the terminal and the second source/drain is coupled to a load. The gate is coupled to the end point χ. 〇773-A32084TWF2(20i00610) 10 1331838 • · Patent No. 95145950 Revision This revision date: 99.8.9 In Figure 3a, the first capacitor C1 and the second capacitor C2 store the voltage VDD, and the first main charge pump The circuit 35 and the second main charge pump circuit 36 alternately output the voltage of 2VDD to the first secondary charge pump circuit 37 or the second secondary charge pump circuit according to the first clock signal CLK1 and the second clock signal CLK2. 38. The third capacitor C3 and the fourth capacitor C4 store the voltage 2VDD, and the first secondary charging pump circuit 37 and the second secondary charging pump circuit 38 alternate according to the first clock signal CLK1 and the second clock signal CLK2. Output 3VDD voltage to the load. Fig. 3b is a schematic view showing a third embodiment of the DC voltage converting circuit of the present invention. The difference from Fig. 3a is that the inverters are all represented by transistors, and the rest of the similar parts will not be described again. For a clearer explanation of the action of Figure 3b, please refer to Figure 3c. Figure 3c is a schematic diagram of the output waveform of the DC voltage conversion circuit of Figure 3b. During the first period P1, the clock signals CLK1, CLK2 are HIGH and LOW, respectively. The transistors ΤΙ, T6, T13, and T16 are turned off, and the transistors T2, T5, T14, and T15 are turned on, so that the voltages at the terminals B1 and D1 are zero, and the voltages at the nodes B2 and D2 are VDD. Since the first capacitor C1 and the second capacitor C2 store the voltage of VDD, the voltage at the terminal A1 is VDD, and the voltage at the terminal A2 is 2VDD. Since the voltage at the terminal A1 is VDD and the voltage at the terminal A2 is 2 VDD, the transistors T4 and T7 are turned on, and the transistors T3 and T8 are turned off. Since the voltage at terminal D2 is VDD and the voltage stored in capacitor C3 is 2VDD, the voltage at terminal X is a voltage of 3VDD. In addition, since the terminal D1 is grounded and the voltage stored in the capacitor C4 is 0773-A32084TWF2 (20100610) 11 1331838 Revision date: 99.8.9 Amendment No. 95145950 (2 VDD), the voltage on the node Y is 2 VDD. Since the voltage at the terminal X is 3VDD and the voltage at the terminal Y is 2VDD, the transistors T9, T12 are turned off, and the transistors Τ10, Τ11 are turned on, so that the first secondary charging pump circuit 37 outputs the 3VDD voltage to the load. At this time, since the transistor Τ12 is turned off due to the output voltage from the first secondary charge pump circuit 37, the output of the second secondary charge pump circuit 38 is disabled (at the second period P2). The clock signals CLK1 and CLK2 are LOW and HIGH, respectively. The transistor T, T6, T13, and T16 are turned on, and the transistors T2, T5, T14, and T15 are turned off, so that the voltages at the terminals B1 and D1 are VDD, and the voltages at the nodes B2 and D2 are zero. Since the first capacitor C1 and the second capacitor C2 store the voltage of VDD, the voltage at the terminal A1 is 2VDD, and the voltage at the terminal A2 is VDD. Since the voltage at the terminal A1 is 2VDD and the voltage at the terminal A2 is VDD, the transistors T3 and T8 are turned on, and the transistors T4 and T7 are turned off. Since the voltage on terminal D1 is VDD and the voltage stored in capacitor C4 is 2 VDD, the voltage at terminal Y is a voltage of 3 VDD. In addition, since the terminal D2 is grounded and the voltage stored in the capacitor C3 (2VDD), the voltage at the node X is 2 VDD. Since the voltage at terminal X is 2VDD and the voltage at terminal Y is 3VDD, transistors T10, T11 are turned off, and transistors T9, T12 are turned on, causing second secondary charge pump circuit 38 to output a 3VDD voltage to the load. At this time, since the transistor T10 is turned off due to the output voltage from the second secondary charge pump circuit 38, the output of the first secondary charge pump circuit 37 is disabled. 0773-A32084TWF2 (20100610) 12 1331838 • No. 95145950 Patent Specification Revision Date: 99.8.9 (disable) ° Therefore, in the DC voltage conversion circuit, the first main charge pump circuit 35 and the second main charge pump circuit 36 alternately output a voltage of 2VDD as a boost. The voltage is applied to the first secondary charge pump circuit 37 and the second "secondary charge pump circuit 38, and the first primary charge pump circuit 35 and the second primary charge pump circuit 36 are alternately replaced by the first control signal S1 and The second control signal S2 is disabled, and the first secondary charge pump circuit 37 and the second secondary charge pump circuit 38 are alternately disabled by the third control signal S3 and the fourth control signal S4. In other words, the DC voltage conversion circuit is used to convert the output voltage VDD into a boosted voltage of 3 VDD. In the above embodiment, the first charge pump circuit 35 and the second charge pump circuit 36 are respectively coupled. The first secondary charging pump circuit 37 and the second secondary charging pump circuit 38 are connected, and in practical applications, a plurality of first secondary charging pump circuit 37 and second secondary charging pump circuit 38 may be coupled respectively. The first secondary charge pump circuit 37 and the second secondary charge pump circuit 38, as such, can output a voltage V. Upgrade to a higher level. In this embodiment, both the first secondary charging pump circuit 37 and the second secondary charging pump circuit 38 can increase the received voltage by the magnitude of VDD (ie, the magnitude of the input voltage), so if N is connected in series The first secondary charge pump circuit 37 and the second secondary charge pump circuit 38 output a voltage V. The size is (2+N) VDD. Fig. 4a is a schematic view showing a fourth embodiment of the DC voltage converting circuit of the present invention. The DC voltage conversion circuit includes a first inverter 41, a first main charge pump circuit 45, a second inverter 42, and a second main charge pump 0773-A32084TWF2 (20100610) 13 1331838 Revision date: 99.8.9 Patent No. 95145950 The specification corrects the present circuit 46, the second inverter 43, the first secondary charging system 47, the fourth inverter 44, and the second secondary charging pump circuit 48. Different from Figure 3a, the original voltage source is replaced by ground. The original ground is replaced by a voltage source. The original PMOS transistor and NM0S transistor are also replaced by NMOS transistor and pm〇S transistor. In the first main charge pump circuit 45, the transistor 4 has a first source/no pole, a second source/no pole, and a gate, wherein the first source/drain is grounded ;—the original/pole _ Connected to terminal A1, the gate is connected to the endpoint Μ. The transistor Τ3 has a -first source and a pole, a second source/drain and a pole, wherein the first source/no pole is connected to the end point VIII second source/no pole face to the first secondary charge pump Circuit 47, the gate is coupled to terminal Α2. The first capacitor q has two ends, the wheel-out end of the inverter 41, the other end-point, and the first main charge pump circuit 46. The transistor D has a first pole, a second source/secret. And 1 pole, wherein the first source/no pole is connected, the first source/no pole is lightly connected to the end point A2, the closed pole transit end point Μ 曰曰0 body T7 has a first source/no pole, the second source /汲 pole to: pole: wherein the first source/drain transition end A2, the second source secondary charge pump circuit 48, the one end of the brake shaft is coupled to the wheel A2 of the second inverter 42 . The other end is coupled to the end point of the first secondary charge pump circuit 47,
源/及極、一第二源/汲極以=二有-第-輕接電晶體丁3的第二源/；；及極’第” 源/及極 0773-A32084TWF2(201〇〇6]〇) 14 1331838 • · 第95145950號專利說明書修正本 修正日期：99.8.9 閘極耦接端點Y。第三電容C3的一端耦接第三反相器43 的輸出端，另一端耦接端點X。電晶體T10具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接端點X，第二源/汲極耦接一負載，閘極耦接端點Y。 " 第二次級充電泵電路48中，電晶體ΤΙ 1具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接電晶體T7的第二源/汲極，第二源/汲極耦接端點Y， 閘極耦接端點X。第四電容C4的一端耦接第四反相器44 的輸出端，另一端耦接端點Y。電晶體T12具有一第一 源/汲極、一第二源/汲極以及一閘極，其中第一源/汲極 耦接端點Y，第二源/汲極耦接一負載，閘極耦接端點X。 在第4a圖中，第一主要充電泵電路45與第二主要 充電泵電路46則根據第一時脈信號CLK1與第二時脈信 號CLK2，交替的輸出-VDD的電壓到第一次級充電泵電 路47或第二次級充電泵電路48。而第一次級充電泵電路 47與第二次級充電泵電路48則根據第一時脈信號CLK1 與第二時脈信號CLK2，交替的輸出-2VDD的電壓到負 載。 第4b圖為本發明之直流電壓轉換電路之第五實施 例的示意圖。與第4a圖不同處在於反相器皆以電晶體表 示，其餘相似部分則不再贅述。爲更清楚說明第4b圖的 動作，請參考第4c圖。第4c圖為第4b圖之直流電壓轉 換電路之輸出波形示意圖。 於第一週期P1時，時脈信號CLK1、CLK2分別為 0773-A32084TWF2(20100610) 15 1331838 第95145950號專利說明書修正本 修正日期：99.8.9 HIGH與LOW。電晶體Ή、T6、T14、T15會導通，而 電晶體Τ2、Τ5、Τ13、Τ16會截止，使得端點Β1與D1 上之電壓為0，節點Β2與D2上之電壓為VDD。由於第 一電容C1與第二電容C2儲存有-VDD的電壓，故端點 Α1上之電壓為-VDD，而端點Α2上之電壓為0。 由於端點Α1的電壓為-VDD而端點Α2的電壓為0, 所以電晶體Τ4、Τ7會截止，而電晶體Τ3、Τ8會導通。 由於端點D2上之電壓為VDD，且儲存在電容C3中的電 壓為-2VDD，故端點X上之電壓為-VDD之電壓。另外由 於端點D1接地及儲存在電容C4中之電壓（-2VDD)，節 點Υ上之電壓為-2 VDD。因為端點X的電壓為-VDD而 端點Υ的電壓為-2VDD，所以電晶體T9、Τ12會導通， 而電晶體Τ10、Τ11會截止，使得第二次級充電泵電路 48輸出-2VDD電壓至負載。此時，由於電晶體Τ10會因 為來自第二次級充電泵電路48之輸出電壓而截止，所以 第一次級充電泵電路47之輸出會被禁能（disable)。 於第二週期P2時，時脈信號CLK1、CLK2分別為 LOW與HIGH。電晶體ΤΊ、T6、T14、T15會截止，而 電晶體T2、T5、T13、T16會導通，使得端點B1與D1 上之電壓為VDD，節點B2與D2上之電壓為0。由於第 一電容C1與第二電容C2儲存有-VDD的電壓，故端點 A1上之電壓為0，而端點A2上之電壓為-VDD。 由於端點A1的電壓為0而端點A2的電壓為-VDD， 所以電晶體T3、T8會截止，而電晶體T4、T7會導通。 0773-A32084TWF2(2Ol 00610) 16 1331838 1 · 第95145950號專利說明書修正本 修正日期：99.8.9 由於端點D1上之電壓為VDD，且儲存在電容C4中的電 壓為-2VDD，故端點Y上之電壓為-VDD之電壓。另外由 於端點D2接地及儲存在電容C3中之電壓（-2VDD)，節 點X上之電壓為-2 VDD。因為端點X的電壓為-2VDD而 • 端點Y的電壓為-VDD，所以電晶體T10、T11會導通， 而電晶體T9、T12會截止，使得第一次級充電泵電路47 輸出-2VDD電壓至負載。此時，由於電晶體T12會因為 來自第一次級充電泵電路47之輸出電壓而截止，所以第 二次級充電泵電路48之輸出會被禁能（disable)。 因此，於直流電壓轉換電路中，第一主要充電泵電 路45與第二主要充電泵電路46會交替地輸出一 -VDD的 電壓作為一提升電壓至第一次級充電泵電路47與第二次 級充電泵電路48中，並且第一主要充電泵電路45與第 二主要充電泵電路46會交替地被第一控制信號S1與第 二控制信號S2所禁能，第一次級充電泵電路47與第二 次級充電泵電路48會交替地被第三控制信號S3與第四 控制信號S4所禁能。換句話說，直流電壓轉換電路係用 以將輸出電壓VDD轉換成-2 VDD之提升電壓（boosted voltage)Vo ° 在上述的實施例中，第一充電泵電路45與第二充電 泵電路46分別只耦接第一次級充電泵電路47與第二次 级充電泵電路48，而在實際應用上，可在第一次級充電 泵電路47與第二次級充電泵電路48之後分別耦接複數 個第一次級充電泵電路47與第二次級充電泵電路48，如 0773-A32084TWF2(20100610) 17 1331838 修正日期：99.8.9 第95145950號專利說明書修正本 此-來可將輸出電壓V。提升至更高。在本實施例中，第 一次級充電泵電路47與第二次級充電栗電路48皆可將 所接收到的電壓提升·的大小（亦即輸入電壓的大 小），因此若串接N個第一次級充電泵電路47與第二次 級充電泵電路48時，輸出電壓v。的大小為·（Ν+】）ν〇^ 第5圖為應用本發明之直流電壓轉換電路之顯示系 統之-實施例的示意圖。顯示裝置52内建有如前述之直 流電壓轉換電路55 ’接收並轉換電源供應器51提供的電 壓，再傳送至閘極驅動電路56用以驅動像素陣列57。 序控制電路53接收一顯示資料，並控制資料驅動電路μ 以及閘極驅動電路56使得像素陣列57顯示出對應的影 像、。在本貫施例中，時序控制電路53、資料驅動電路^、Source/and pole, a second source/drainage ============================================================================================ 13) 14 1331838 • · Patent No. 95145950 Revision This revision date: 99.8.9 The gate is coupled to the terminal Y. One end of the third capacitor C3 is coupled to the output of the third inverter 43, and the other end is coupled. Point X. The transistor T10 has a first source/drain, a second source/drain, and a gate, wherein the first source/drain is coupled to the terminal X, and the second source/drain is coupled to a load. The gate is coupled to the terminal Y. " In the second secondary charging pump circuit 48, the transistor ΤΙ 1 has a first source/drain, a second source/drain, and a gate, wherein the first source The second capacitor is coupled to the second source/drain of the transistor T7, the second source/drain is coupled to the terminal Y, and the gate is coupled to the terminal X. One end of the fourth capacitor C4 is coupled to the fourth inverter 44. The other end is coupled to the terminal Y. The transistor T12 has a first source/drain, a second source/drain, and a gate, wherein the first source/drain is coupled to the terminal Y, The two source/drain electrodes are coupled to a load and the gate coupling end In Fig. 4a, the first main charge pump circuit 45 and the second main charge pump circuit 46 alternately output the voltage of -VDD to the first time according to the first clock signal CLK1 and the second clock signal CLK2. The stage secondary charge pump circuit 47 or the second secondary charge pump circuit 48. The first secondary charge pump circuit 47 and the second secondary charge pump circuit 48 alternate according to the first clock signal CLK1 and the second clock signal CLK2. The output of -2VDD is applied to the load. Figure 4b is a schematic diagram of a fifth embodiment of the DC voltage conversion circuit of the present invention. The difference from Figure 4a is that the inverters are all represented by transistors, and the remaining similar parts are no longer For a clearer explanation of the action of Figure 4b, please refer to Figure 4c. Figure 4c is a schematic diagram of the output waveform of the DC voltage conversion circuit of Figure 4b. During the first period P1, the clock signals CLK1 and CLK2 are respectively 0773-A32084TWF2(20100610) 15 1331838 Patent Specification No. 95145950 Revision of this amendment date: 99.8.9 HIGH and LOW. The transistor Ή, T6, T14, T15 will be turned on, and the transistors Τ2, Τ5, Τ13, Τ16 will be cut off. Make endpoints Β1 and D1 The voltage is 0, and the voltages on nodes Β2 and D2 are VDD. Since the first capacitor C1 and the second capacitor C2 store the voltage of -VDD, the voltage at the terminal Α1 is -VDD, and the voltage at the terminal Α2 0. Since the voltage at the terminal Α1 is -VDD and the voltage at the terminal Α2 is 0, the transistors Τ4 and Τ7 are turned off, and the transistors Τ3 and Τ8 are turned on. Since the voltage at the terminal D2 is VDD, and The voltage stored in capacitor C3 is -2VDD, so the voltage at terminal X is the voltage of -VDD. In addition, since the terminal D1 is grounded and the voltage (-2VDD) stored in the capacitor C4, the voltage on the node 为 is -2 VDD. Since the voltage at the terminal X is -VDD and the voltage at the terminal Υ is -2VDD, the transistors T9 and Τ12 are turned on, and the transistors Τ10, Τ11 are turned off, so that the second secondary charging pump circuit 48 outputs -2VDD. To the load. At this time, since the transistor Τ10 is turned off due to the output voltage from the second secondary charge pump circuit 48, the output of the first secondary charge pump circuit 47 is disabled. During the second period P2, the clock signals CLK1 and CLK2 are LOW and HIGH, respectively. The transistors ΤΊ, T6, T14, and T15 are turned off, and the transistors T2, T5, T13, and T16 are turned on, so that the voltages at the terminals B1 and D1 are VDD, and the voltages at the nodes B2 and D2 are zero. Since the first capacitor C1 and the second capacitor C2 store a voltage of -VDD, the voltage at the terminal A1 is 0, and the voltage at the terminal A2 is -VDD. Since the voltage at the terminal A1 is 0 and the voltage at the terminal A2 is -VDD, the transistors T3 and T8 are turned off, and the transistors T4 and T7 are turned on. 0773-A32084TWF2(2Ol 00610) 16 1331838 1 · Patent No. 95145950 Revision This revision date: 99.8.9 Since the voltage at terminal D1 is VDD and the voltage stored in capacitor C4 is -2VDD, terminal Y The voltage on it is the voltage of -VDD. In addition, since the terminal D2 is grounded and the voltage stored in the capacitor C3 (-2VDD), the voltage at the node X is -2 VDD. Since the voltage at the terminal X is -2VDD and the voltage at the terminal Y is -VDD, the transistors T10, T11 are turned on, and the transistors T9, T12 are turned off, so that the first secondary charging pump circuit 47 outputs -2VDD. Voltage to load. At this time, since the transistor T12 is turned off due to the output voltage from the first secondary charge pump circuit 47, the output of the second secondary charge pump circuit 48 is disabled. Therefore, in the DC voltage conversion circuit, the first main charge pump circuit 45 and the second main charge pump circuit 46 alternately output a voltage of -VDD as a boost voltage to the first secondary charge pump circuit 47 and the second time. In the stage charge pump circuit 48, and the first main charge pump circuit 45 and the second main charge pump circuit 46 are alternately disabled by the first control signal S1 and the second control signal S2, the first secondary charge pump circuit 47 The third secondary charging pump circuit 48 is alternately disabled by the third control signal S3 and the fourth control signal S4. In other words, the DC voltage conversion circuit is configured to convert the output voltage VDD into a boosted voltage of −2 VDD. In the above embodiment, the first charge pump circuit 45 and the second charge pump circuit 46 respectively. Only the first secondary charging pump circuit 47 and the second secondary charging pump circuit 48 are coupled, and in practical applications, can be coupled after the first secondary charging pump circuit 47 and the second secondary charging pump circuit 48, respectively. A plurality of first secondary charging pump circuits 47 and a second secondary charging pump circuit 48, such as 0773-A32084TWF2 (20100610) 17 1331838. Amendment date: 99.8.9 Patent No. 95,145, 950 to correct this - to output voltage V . Upgrade to a higher level. In this embodiment, both the first secondary charging pump circuit 47 and the second secondary charging circuit 48 can increase the magnitude of the received voltage (that is, the magnitude of the input voltage), so if N is connected in series The first secondary charge pump circuit 47 and the second secondary charge pump circuit 48 output a voltage v. The size is ((+)) ν 〇 ^ Fig. 5 is a schematic view showing an embodiment of a display system to which the DC voltage conversion circuit of the present invention is applied. The display device 52 is internally provided with a DC voltage conversion circuit 55' as described above for receiving and converting the voltage supplied from the power supply 51, and then to the gate drive circuit 56 for driving the pixel array 57. The sequence control circuit 53 receives a display material and controls the data driving circuit μ and the gate driving circuit 56 so that the pixel array 57 displays the corresponding image. In the present embodiment, the timing control circuit 53, the data driving circuit ^,
直流電壓轉換電路55、閘極驅動電路56以及像辛陣列 57皆可整合至面板上。 *轉歹J 第6圖為應用本發明之直流電壓轉換電路之電子裝 實施例的示意圖。電子裝置包括一輸入裝置6i J 二圖：不之顯示裝置。在本發明中’電子裝置可The DC voltage conversion circuit 55, the gate drive circuit 56, and the image sinus array 57 can be integrated onto the panel. *Switch J Fig. 6 is a schematic diagram of an electronic device embodiment to which the DC voltage conversion circuit of the present invention is applied. The electronic device includes an input device 6i J. Figure 2: No display device. In the present invention, the electronic device can
Uda / ，例如手機、數位相機、個人數位助 理(pda)、麵型電腦(_咖从eGmputer)、桌上型 ，視、或可攜式DVD放影機等裳置。再者，本發明 路之直流電壓轉換電路係用以提供輸出電麼供: =以及使用者介面。雖然本發㈣以液晶顯示器= 二鈀：揭路如上，但本發明之直流電壓轉換電路仍可適 於，、他顯示系統，例如電聚顯示元件、有機發光（〇LED) 0773-A32084TWF2(20i 00610) 1331838 • · 第95145950號專利說明書修正本 修正日期：99.8.9 顯示元件、冷陰極管顯示元件或陰極射線管（CRT)顯示元 件等等。 ’ 【圖式簡單說明】 • 第1 a圖係顯示一傳統Dickson充電泵電路。 第lb圖係顯示另一傳統Dickson充電泵電路。 第2a圖為本發明之直流電壓轉換電路之一實施例 的示意圖。 第2b圖係為第2a圖的直流電壓轉換電路之控制信 號的示意圖。 第3a圖為本發明之直流電壓轉換電路之第二實施 例的示意圖。 第3b圖為本發明之直流電壓轉換電路之第三實施 例的示意圖。 第3c圖為第3b圖之直流電壓轉換電路之輸出波形 示意圖。 第4a圖為本發明之直流電壓轉換電路之第四實施 例的示意圖。 第4b圖為本發明之直流電壓轉換電路之第五實施 例的示意圖。 第4c圖為第4b圖之直流電壓轉換電路之輸出波形 示意圖。 第5圖為應用本發明之直流電壓轉換電路之顯示系 統之一實施例的示意圖。 0773-A32084TWF2(20100610) 19 1331838 第95145950號專利說明書修正本 修正日期：99.8.9 第6圖為應用本發明之直流電壓轉換電路之電子裝 置之一實施例的示意圖。 【主要元件符號說明】 21、 35、45〜第一主要充電泵電路 22、 36、46〜第二主要充電泵電路 23、 37、47〜第一次級充電泵電路 32、42〜第二反相器； 34、44〜第四反相器； CLK1〜第一時脈信號； 51〜電源供應益， 5 3〜時序控制電路， 55〜直流電壓轉換電路； 57〜像素陣列； 24、 38、48〜第二次級充電泵電路 31、41〜第一反相器； 33、43〜第三反相器；Uda / , such as mobile phones, digital cameras, personal digital assistants (PDAs), facial computers (_g from eGmputer), desktop, video, or portable DVD players. Furthermore, the DC voltage conversion circuit of the present invention is used to provide output power for: = and user interface. Although the present invention (4) uses a liquid crystal display = two palladium: the above, but the DC voltage conversion circuit of the present invention can still be adapted to, his display system, such as electro-convex display elements, organic light-emitting (〇LED) 0773-A32084TWF2 (20i 00610) 1331838 • · Patent No. 95145950 Revision This revision date: 99.8.9 Display elements, cold cathode tube display elements or cathode ray tube (CRT) display elements, etc. ‘ [Simple description] • Figure 1 a shows a traditional Dickson charge pump circuit. Figure lb shows another conventional Dickson charge pump circuit. Figure 2a is a schematic diagram of one embodiment of a DC voltage conversion circuit of the present invention. Figure 2b is a schematic diagram of the control signal of the DC voltage conversion circuit of Figure 2a. Fig. 3a is a schematic view showing a second embodiment of the DC voltage conversion circuit of the present invention. Fig. 3b is a schematic view showing a third embodiment of the DC voltage converting circuit of the present invention. Figure 3c is a schematic diagram of the output waveform of the DC voltage conversion circuit of Figure 3b. Fig. 4a is a schematic view showing a fourth embodiment of the DC voltage converting circuit of the present invention. Fig. 4b is a schematic view showing a fifth embodiment of the DC voltage converting circuit of the present invention. Figure 4c is a schematic diagram of the output waveform of the DC voltage conversion circuit of Figure 4b. Fig. 5 is a view showing an embodiment of a display system to which the DC voltage conversion circuit of the present invention is applied. 0773-A32084TWF2(20100610) 19 1331838 Revision No. 95145950 Patent Revision Date: 99.8.9 Fig. 6 is a view showing an embodiment of an electronic device to which the DC voltage conversion circuit of the present invention is applied. [Major component symbol description] 21, 35, 45~ first main charge pump circuit 22, 36, 46~ second main charge pump circuit 23, 37, 47~ first secondary charge pump circuit 32, 42~ second reverse Phase comparator; 34, 44 ~ fourth inverter; CLK1 ~ first clock signal; 51 ~ power supply benefit, 5 3 ~ timing control circuit, 55 ~ DC voltage conversion circuit; 57 ~ pixel array; 24, 38, 48~ second secondary charge pump circuit 31, 41 to first inverter; 33, 43 to third inverter;
Cl、C2、C3、C4〜電容； CLK2〜第二時脈信號； 52〜顯示裝置； 54〜資料驅動電路； 56〜閘極驅動電路； 61〜輸入裝置。 0773-A32084TWF2(20100610) 20Cl, C2, C3, C4~capacitor; CLK2~second clock signal; 52~ display device; 54~ data drive circuit; 56~ gate drive circuit; 61~ input device. 0773-A32084TWF2(20100610) 20