CN1770248A - Display drive circuit for liquid crystal on silicon based on large-scale integrated circuit - Google Patents
Display drive circuit for liquid crystal on silicon based on large-scale integrated circuit Download PDFInfo
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- CN1770248A CN1770248A CN 200410067751 CN200410067751A CN1770248A CN 1770248 A CN1770248 A CN 1770248A CN 200410067751 CN200410067751 CN 200410067751 CN 200410067751 A CN200410067751 A CN 200410067751A CN 1770248 A CN1770248 A CN 1770248A
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Abstract
The invention relates to a display driving circuit for reflection liquid crystal projection system (LCOS) based on large scale integrated circuit, which comprises: DVI connector, DVI signal converter, clock circuit, driving board interface, serial data interface, EEPROM memory, SDRAM data memory, safety circuit, power generating circuit, ITO voltage, VP voltage generating circuit, LCOS display chip; also comprises field programmable device for operating frame writing and frame displaying 48 bits data, wherein the frame writing has 48 bits written into SDRAM data memory, frame displaying reads data from SDRAM data memory and outputs display data to LCOS display chip via FPGA device. The invention has the advantages of having high integrated level and being stable.
Description
Technical field
The present invention relates to a kind of high definition digital display technique---LCOS (Liquid CrystalOn Silicon is promptly based on the reflective liquid crystal shadow casting technique on the large scale integrated circuit) relates in particular to the display driver circuit in this shadow casting technique.
Background technology
The high definition LCOS of a new generation microplate display technique is present up-to-date in the world large-screen high-resolution number of degrees word display technique---LCOS; LCOS does packaged liquid crystal cell and integrated circuit (IC) chip together.
Because adopt silicon technology, comparing its cost of products with other technology can be very low; LCOS has the resolution height, the light aperture is big, Pixel Dimensions is little, contrast is high, bright in luster, power consumptive province, pollution-free, in light weight, low cost of manufacture and compatible outstanding advantage such as good, will be one of future world display technique important development direction.LCOS is consistent in the world having an optimistic view of, and most possibly with the product technology that instinct enters the HDTV of ordinary people family that manufactures of its high-quality technical indicator and low price, has very vast market prospect.
How to develop and can accomplish the level of integrated system height, again can adaptive system to the requirement of speed, satisfying the integrality that shows and the display driver circuit of stability requirement is that the needs of pendulum in face of the science and technology personnel are dealt with problems.
Summary of the invention
The technical issues that need to address of the present invention have provided a kind of based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, are intended to address the above problem.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions:
The present invention includes the DVI connector, DVI signal converter, clock circuit, drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, power generation circuit, ITO voltage, VP voltage generation circuit, LCOS display chip; Also comprise on-site programmable device FPGA; Described DVI three chromatic number word video differential signals are delivered to DVI signal converter chip through DVI connector input drive plate by line; Through data conversion, synchronously and decoding handle and produce red, green, Lan Sanse 48bit parallel data signal and clock and ranks synchronizing signal altogether, be input in the field programmable device by connecting line and handle; Field programmable device carries out frame to the 48bits data and writes with the frame display operation and handle: wherein frame writes the 48bits data is write in the SDRAM data-carrier store; Frame shows reading of data from the SDRAM data-carrier store, forms video data, drives the LCOS display chip through field programmable device output; Described ITO voltage, VP voltage generation circuit are accepted the control voltage data code control signal of serial data interface, by the emitter follower and the differential amplifier circuit of A/D converter integrated transporting discharging design, generate display chip liquid crystal back of the body voltage ITO voltage and pixel voltage VP is used for driving the LCOS display chip according to the voltage signal of input voltage signal and feedback; Described power generation circuit passes through linear stabilized power supply with the direct supply of outside input, pass through Filtering Processing, generation 3.3V, 1.5V ,+6V ,-the 6V operating voltage: wherein 3.3V, 1.5V offer IO interface voltage and the core operational voltage of VCCIO, the VCCINT of field programmable device needs; 3.3V and offer DVI signal converter, clock circuit, drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, the required power supply+6V of LCOS display chip ,-6V offers the operating voltage of integrated transporting discharging, to produce ITO voltage and the VP voltage that the LCOS display chip needs; Described safety circuit links to each other with LCOS display chip, ray machine, field programmable device, provides warning and cuts off the ray machine power supply by safety circuit when temperature anomaly, and FPGA is resetted.
Compared with prior art, the invention has the beneficial effects as follows: can accomplish the level of integrated system height, again can adaptive system to the requirement of speed, satisfied the integrality and the stability requirement that show; High-performance, low price is used for three coloured light and learns the driving engine, can produce the height contrast of SXGA (1280 * 1024 pel array) resolution, high brightness, 24 chromatic images.
Description of drawings
Fig. 1 is the block scheme of LCOS light engine;
Fig. 2 is a block scheme of the present invention;
Fig. 3 is the block scheme of FPGA among Fig. 2; (numeral among the figure only is the mark of connecting line)
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:
As seen from Figure 1: vision signal can be the HDTV signal, and normal tv signal also can be DVD, VCD signal or with the computer graphic picture signals.Vision signal through the Flame Image Process pcb board, is delivered to the display driver plate earlier then, sends into the image display chip at last;
The reflective liquid crystal light valve that SXGA MircoLCD image display is made up of 1296 * 1032SRAM array can be supported 1280 * 1024 resolution, and chip size is about 12 * 11cm
2, Pixel Dimensions is about 8 μ m, and greater than 350: 1, the aperture ratio was 95% to contrast (continuously minimum, black in bright), and reflectance is greater than 70%.
As seen from Figure 2: the present invention includes the DVI connector, DVI signal converter, clock circuit, drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, power generation circuit, ITO voltage, VP voltage generation circuit, LCOS display chip; Also comprise on-site programmable device FPGA; Described DVI three chromatic number word video differential signals are delivered to DVI signal converter chip through DVI connector input drive plate by line; Through data conversion, synchronously and decoding handle and produce red, green, Lan Sanse 48bit parallel data signal and clock and ranks synchronizing signal altogether, be input in the field programmable device by connecting line and handle; Field programmable device carries out frame to the 48bits data and writes with the frame display operation and handle: wherein frame writes the 48bits data is write in the SDRAM data-carrier store; Frame shows reading of data from the SDRAM data-carrier store, forms video data, drives the LCOS display chip through field programmable device output; Described ITO voltage, VP voltage generation circuit are accepted the control voltage data code control signal of serial data interface, by the emitter follower and the differential amplifier circuit of A/D converter integrated transporting discharging design, generate display chip liquid crystal back of the body voltage ITO voltage and pixel voltage VP is used for driving the LCOS display chip according to the voltage signal of input voltage signal and feedback; Described power generation circuit passes through linear stabilized power supply with the direct supply of outside input, pass through Filtering Processing, generation 3.3V, 1.5V ,+6V ,-the 6V operating voltage: wherein 3.3V, 1.5V offer IO interface voltage and the core operational voltage of VCCIO, the VCCINT of field programmable device needs; 3.3V and offer DVI signal converter, clock circuit, drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, the required power supply of LCOS display chip; + 6V ,-6V offers the operating voltage of integrated transporting discharging, to produce ITO voltage and the VP voltage that the LCOS display chip needs; Described safety circuit links to each other with LCOS display chip, ray machine, field programmable device, provides warning and cuts off the ray machine power supply by safety circuit when temperature anomaly, and field programmable device is resetted;
Described field programmable device comprises: video input interface, video data storer, LCOS display driver circuit, system interface, system, control circuit, memorizer control circuit, system signal output circuit, I
2The C serial bus interface, the command word storer; Described video input interface receives 48bit parallel data signal and clock and the ranks synchronizing signal that is transmitted by the DVI signal converter, data-signal and clock signal is sent into the video data storer, and the ranks synchronizing signal is sent into memorizer control circuit; Described system interface is accepted alerting signal that reset signal that the clock signal of clock circuit and drive plate interface comes and safety circuit come and these signals is delivered to system, control circuit; The clock signal that described system, control circuit transmits the system interface circuit is delivered to the readout clock of memorizer control circuit as the SDRAM data-carrier store; Clock signal is delivered to the system signal output circuit as the clock of giving the LCOS display chip; System, control circuit is delivered to video input interface, video data storer, memorizer control circuit with the reset signal that the system interface circuit comes, and the command word storer is used as the signal that described circuit reset restarts; Reset signal also outputs to the LCOS display chip from the system signal output circuit and is used for display chip and resets; System, control circuit is delivered to memorizer control circuit with the security alarm signal that the system interface circuit comes, and is used to stop data output, and the security alarm signal is delivered to the system signal output circuit, outputs to the LCOS display chip, is used to stop to show; Described memorizer control circuit output is write the SDRAM data memory addresses to the SDRAM data-carrier store; Described LCOS display driver circuit is accepted memorizer control circuit output and is read the data of SDRAM data memory addresses to the appropriate address of SDRAM data-carrier store, and outputs to the LCOS display chip; Described I
2The C serial bus interface receives from the next command word of eeprom memory; After system interface is received reset signal, the command word memory array is resetted and the data in the eeprom memory are passed through I
2The C serial bus interface is write in the command word feram memory; Described command word storer receives by I
2Command word that the C serial bus interface comes and storage, command word is made up of binary coding, requires chronologically control command is outputed to the LCOS display chip by the system signal output circuit, is used for the required order of LCOS display chip operation;
Described SDRAM data-carrier store comprises by the chip of six 32Mbits memory capacity to be formed, per two data that are used to handle every kind of color;
Described ITO voltage, VP voltage generation circuit comprise A/D converter, high-speed, high precision integrated transporting discharging and stabilivolt;
Described memorizer control circuit comprises the reading, writing address generator; Described reading, writing address generator is made up of 14 binary add 1 counters; Described command word storer is made up of memory array.
Below principle of work of the present invention is described as follows:
The DVI part
DVI three chromatic number word video differential signals are through DVI connector input drive plate, deliver to DVI signal converter chip by line 6, through data conversion, produce red with the decoding processing synchronously, green, Lan Sanse is 48bit parallel data signal and clock and ranks synchronizing signal altogether, by connecting line 7 input LCOS chip for driving.
The FPGA part
Make the LCOS chip for driving with on-site programmable device FPGA, FPGA receives red, green that DVI signal converter chip produces, blue three look 48bits data-signals and clock and ranks synchronizing signal, by system, control circuit, the 48bits data are carried out frame write with the frame display operation and handle.Wherein frame writes the 48bits data is write among the high speed SDRAM; Frame shows reading of data from SDRAM, forms video data, through FPGA output, drives LCOS and shows.System, control circuit, command memory and outside high-speed high capacity SDRAM are finished clock processing, metadata cache storage, produce LCOS video data and control signal.All Data Management Analysis are finished by a BGA packaged FPGA chip, have the level of integrated system height, advantages such as good stability.
The SDRAM part
The data processing of every kind of color needs to be made up of the SDRAM chip of two 32Mbits memory capacity, and system needs six high-speed high capacity SDRAM chips altogether, and storage is write and frame display digit TV signal by the frame that FPGA transmitted.Storage signal during the frame write state, frame read signal when showing.Two SDRAM can finish read-write simultaneously, and alternation has improved the requirement of system to speed, satisfy the integrality and the stability requirement that show.
ITO voltage and VP voltage produce part
Constitute by high-speed, high precision integrated transporting discharging, stabilivolt etc., accept the control voltage data code control signal of serial data interface line 10, emitter follower and differential amplifier circuit by the design of A/D converter integrated transporting discharging, voltage signal generation display chip liquid crystal back of the body voltage ITO voltage and pixel voltage VP according to input voltage signal and feedback send display chip (line 16) to, drive the LCOS display chip.
The power generation circuit part
The direct supply of outside input is passed through linear stabilized power supply, through Filtering Processing, the needed 3.3V of generation circuit system, 1.5V ,+6V ,-the 6V operating voltage, offer each parts of drive plate by line 1, wherein 3.3V, 1.5V offer IO interface voltage and the core operational voltage of VCCIO, the VCCINT of FPGA needs, have low in energy consumption and advantage IO cmos voltage compatibility, 3.3V also offers each parts of drive plate and the required power supply of display chip; + 6V ,-6V offers the operating voltage of integrated transporting discharging, to produce ITO voltage and the VP voltage that LCOS shows to be needed.
The holding circuit part
Temperature detection signal on LCOS display chip and the ray machine is delivered to safety circuit by line 17, provides warning and cuts off the ray machine power supply by safety circuit when temperature anomaly, and FPGA is resetted.Protection system safety.
The FPGA part
The present invention adopts FPGA field-programmable device as chip for driving.By video input interface; Video data storer (SRAM); The LCOS display driver; System interface; System, control circuit; Memorizer control circuit; The system signal output circuit; I
2The C serial bus interface; Command word storer (SRAM) is formed.
Video input interface is made up of the I/O mouth circuit of FPGA, and the 48bit that reception is come by the DVI signal converter (red, green, Lan Sanse) parallel data signal and clock and ranks synchronizing signal (7).Data-signal and clock signal are sent into the video data storer ranks synchronizing signal is sent into memorizer control circuit.
The video data signal that the DVI signal converter comes is made up of 8 bit binary number signals of the gray scale of representing each pixel.Therefore, green with red, blue three chromatic number word signals leave among the SRAM respectively.Under the synchro control of clock signal and memorizer control circuit, output to the SDRAM data-carrier store; When system interface is received reset signal RST, the video data storer is resetted.
System interface is made up of the I/O mouth circuit of FPGA.The clock signal clk (8) of system interface input clock circuit, the reset signal RST (9) that the drive plate interface comes, the alerting signal (12) that safety circuit is come is delivered to system, control circuit with these signals.
System, control circuit is delivered to the readout clock of memorizer control circuit as the SDRAM data-carrier store with the clock signal clk that the system interface circuit comes.CLK delivers to the system signal output circuit as the clock of giving display chip.System, control circuit is delivered to video input interface, video data storer with the RST that resets that the system interface circuit comes, memorizer control circuit, and the command word storer is used as the signal that each circuit reset restarts.Reset signal RST also outputs to display chip from the system signal output circuit and is used for display chip and resets.
System, control circuit is delivered to memorizer control circuit with the security alarm signal alm that the system interface circuit comes, and is used to stop data output.Alm delivers to the system signal output circuit, outputs to display chip and is used to stop to show.
SDRAM reading, writing address generator is arranged in the memorizer control circuit.The read/write address generator adopts 14 binary add 1 counters to form.Memorizer control circuit output is write the SDRAM address to SDRAM.The data of video data storer output are write appropriate address.Whenever write a data write address and add 1 automatically.Every kind of color has 2 SDRAM storeies.When first when writing, second SDRAM storer read.Two read-writes in turn.When reading, read address generator output in the memorizer control circuit and read the address data of SDRAM appropriate address are read in the LCOS display driver circuit of FPGA.Whenever reading data reads the address and adds 1 automatically.It is synchronous that data write and read subject clock signal CLK.When memorizer control circuit is received the RST signal of system, control circuit, with the zero setting of reading, writing address generator counter.
The LCOS display driver circuit is made up of the I/O interface circuit of FPGA.Memorizer control circuit output is read SDRAM address (4) and to the SDRAM data-carrier store data of appropriate address is read into the LCOS display driver circuit, outputs to the LCOS display chip by the LCOS display driver circuit.
I
2The C serial bus interface is made up of the I/O interface circuit of FPGA.The command word that reception comes from eeprom memory.After system interface is received reset signal RST, command word storer SRAM array is resetted and the data among the EEPROM are passed through I
2The C serial bus interface is write among the video data storer SRAM.This command word can be passed through I
2The data of importing in the C universal serial bus are made amendment.
Command word storer SRAM, the command word storer is made up of the SRAM memory array.The command word storer receives by I
2The command word that the C serial bus interface comes also is stored in the SRAM storer.Command word is made up of binary coding.Be used for the required order of LCOS display chip operation.Comprise: the order of display chip data transfer state; Display chip data presentation status command; Data are write display chip SRAM array commands; Data are from the sense command of display chip SRAM array; Data are write the display chip register command, and data are read order from the display chip register.
The command timing that command word storer receiving system control circuit comes requires control command is outputed to the LCOS display chip by the system signal output circuit chronologically.
The system signal output circuit is made up of the I/O mouth circuit of FPGA.The system signal output circuit receives by the next reset signal RST of system, control circuit, clock signal clk, and safety signal alm, the command word signal that the command word storer comes also outputs to LCOS display chip (13).
Claims (5)
1. one kind based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, comprise the DVI connector, DVI signal converter, clock circuit, the drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, power generation circuit, ITO voltage, VP voltage generation circuit, LCOS display chip; It is characterized in that: also comprise on-site programmable device FPGA; Described DVI three chromatic number word video differential signals are delivered to DVI signal converter chip through DVI connector input drive plate by line; Through data conversion, synchronously and decoding handle and produce red, green, Lan Sanse 48bit parallel data signal and clock and ranks synchronizing signal altogether, be input in the field programmable device by connecting line and handle; The field-programmable gate device carries out frame to the 48bits data and writes with the frame display operation and handle: wherein frame writes the 48bits data is write in the SDRAM data-carrier store; Frame shows reading of data from the SDRAM data-carrier store, forms video data, drives the LCOS display chip through the output of field-programmable gate device; Described ITO voltage, VP voltage generation circuit are accepted the control voltage data code control signal of serial data interface, by the emitter follower and the differential amplifier circuit of A/D converter integrated transporting discharging design, generate display chip liquid crystal back of the body voltage ITO voltage and pixel voltage VP is used for driving the LCOS display chip according to the voltage signal of input voltage signal and feedback; Described power generation circuit passes through linear stabilized power supply with the direct supply of outside input, pass through Filtering Processing, generation 3.3V, 1.5V ,+6V ,-the 6V operating voltage: wherein 3.3V, 1.5V offer IO interface voltage and the core operational voltage of VCCIO, the VCCINT of field programmable device needs; 3.3V and offer DVI signal converter, clock circuit, drive plate interface, serial data interface, eeprom memory, SDRAM data-carrier store, safety circuit, the required power supply of LCOS display chip; + 6V ,-6V offers the operating voltage of integrated transporting discharging, to produce ITO voltage and the VP voltage that the LCOS display chip needs; Described safety circuit links to each other with LCOS display chip, ray machine, field programmable device, provides warning and cuts off the ray machine power supply by safety circuit when temperature anomaly, and field programmable device is resetted.
2. according to claim 1 based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, it is characterized in that: described field programmable device comprises: video input interface, the video data storer, the LCOS display driver circuit, system interface, system, control circuit, memorizer control circuit, the system signal output circuit, I
2The C serial bus interface, the command word storer; Described video input interface receives 48bit parallel data signal and clock and the ranks synchronizing signal that is transmitted by the DVI signal converter, data-signal and clock signal is sent into the video data storer, and the ranks synchronizing signal is sent into memorizer control circuit; Described system interface is accepted alerting signal that reset signal that the clock signal of clock circuit and drive plate interface comes and safety circuit come and these signals is delivered to system, control circuit; The clock signal that described system, control circuit transmits the system interface circuit is delivered to the readout clock of memorizer control circuit as the SDRAM data-carrier store; Clock signal is delivered to the system signal output circuit as the clock of giving the LCOS display chip; System, control circuit is delivered to video input interface, video data storer, memorizer control circuit, command word storer with the reset signal that the system interface circuit comes, and is used as the signal that described circuit reset restarts; Reset signal also outputs to the LCOS display chip from the system signal output circuit and is used for display chip and resets; System, control circuit is delivered to memorizer control circuit with the security alarm signal that the system interface circuit comes, and is used to stop data output, and the security alarm signal is delivered to the system signal output circuit, outputs to the LCOS display chip, is used to stop to show; Described memorizer control circuit output is write the SDRAM data memory addresses to the SDRAM data-carrier store; Described LCOS display driver circuit is accepted memorizer control circuit output and is read the data of SDRAM data memory addresses to the appropriate address of SDRAM data-carrier store, and outputs to the LCOS display chip; Described I
2The C serial bus interface receives from the next command word of eeprom memory; After system interface is received reset signal, the command word memory array is resetted and the data in the eeprom memory are passed through I
2The C serial bus interface is write in the command word storer; Described command word storer receives by I
2Command word that the C serial bus interface comes and storage, command word is made up of binary coding, requires chronologically control command is outputed to the LCOS display chip by the system signal output circuit, is used for the required order of LCOS display chip operation.
3. according to claim 1 based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, it is characterized in that: described SDRAM data-carrier store comprises by the chip of six 32Mbits memory capacity to be formed, per two data that are used to handle every kind of color; Described ITO voltage, VP voltage generation circuit comprise A/D converter, high-speed, high precision integrated transporting discharging and stabilivolt.
4. according to claim 2 based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, it is characterized in that: described SDRAM data-carrier store comprises by the chip of six 32Mbits memory capacity to be formed, per two data that are used to handle every kind of color; Described ITO voltage, VP voltage generation circuit comprise A/D converter, high-speed, high precision integrated transporting discharging and stabilivolt.
5. according to claim 2 or 4 described based on display driver circuit in the reflective liquid crystal projection on the large scale integrated circuit, it is characterized in that: described memorizer control circuit comprises the reading, writing address generator; Described reading, writing address generator is made up of 14 binary add 1 counters; Described command word storer is made up of memory array.
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| CN 200410067751 CN1770248A (en) | 2004-11-03 | 2004-11-03 | Display drive circuit for liquid crystal on silicon based on large-scale integrated circuit |
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| CN100463023C (en) * | 2006-12-28 | 2009-02-18 | 上海庆能环保电子科技有限公司 | Hand-held mobile media digital panel display control system |
| CN101916553A (en) * | 2010-07-13 | 2010-12-15 | 深圳市力伟数码技术有限公司 | Color LCOS (Liquid Crystal on Silicon) display chip and drive control method thereof |
| CN101329459B (en) * | 2007-06-20 | 2011-04-06 | 青岛海信电器股份有限公司 | LCD device and apparatus for processing signals |
| CN101241667B (en) * | 2007-02-06 | 2011-07-27 | 瑞萨电子株式会社 | Display driver IC having embedded DRAM |
| CN101577099B (en) * | 2008-05-09 | 2011-07-27 | 联咏科技股份有限公司 | Serial peripheral interface circuit and display device provided with same |
| CN102141695A (en) * | 2011-01-11 | 2011-08-03 | 鞍山亚世光电显示有限公司 | Detection system for intelligent liquid crystal display module |
| CN102194431A (en) * | 2011-05-19 | 2011-09-21 | 华映光电股份有限公司 | Driving system of liquid crystal display |
| CN103794189A (en) * | 2014-02-27 | 2014-05-14 | 刘兴宾 | Liquid crystal display panel sequential control module |
| CN105529007A (en) * | 2016-01-29 | 2016-04-27 | 豪威科技(上海)有限公司 | Drive circuit of ITO electrode in LCOS display structure |
| CN106782356A (en) * | 2016-11-21 | 2017-05-31 | 上海佳显机电科技有限公司 | A kind of drive device of monochromatic high gray liquid crystal display |
| CN107578745A (en) * | 2016-07-04 | 2018-01-12 | 上海和辉光电有限公司 | FPGA device and the AMOLED display circuits using the device |
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| CN101241667B (en) * | 2007-02-06 | 2011-07-27 | 瑞萨电子株式会社 | Display driver IC having embedded DRAM |
| CN101329459B (en) * | 2007-06-20 | 2011-04-06 | 青岛海信电器股份有限公司 | LCD device and apparatus for processing signals |
| CN101577099B (en) * | 2008-05-09 | 2011-07-27 | 联咏科技股份有限公司 | Serial peripheral interface circuit and display device provided with same |
| CN101916553A (en) * | 2010-07-13 | 2010-12-15 | 深圳市力伟数码技术有限公司 | Color LCOS (Liquid Crystal on Silicon) display chip and drive control method thereof |
| CN102141695A (en) * | 2011-01-11 | 2011-08-03 | 鞍山亚世光电显示有限公司 | Detection system for intelligent liquid crystal display module |
| CN102194431A (en) * | 2011-05-19 | 2011-09-21 | 华映光电股份有限公司 | Driving system of liquid crystal display |
| CN102194431B (en) * | 2011-05-19 | 2013-12-25 | 华映光电股份有限公司 | Driving system of liquid crystal display |
| CN103794189A (en) * | 2014-02-27 | 2014-05-14 | 刘兴宾 | Liquid crystal display panel sequential control module |
| CN105529007A (en) * | 2016-01-29 | 2016-04-27 | 豪威科技(上海)有限公司 | Drive circuit of ITO electrode in LCOS display structure |
| CN105529007B (en) * | 2016-01-29 | 2018-01-26 | 豪威科技(上海)有限公司 | LCOS shows the drive circuit of ITO electrode in structure |
| CN107578745A (en) * | 2016-07-04 | 2018-01-12 | 上海和辉光电有限公司 | FPGA device and the AMOLED display circuits using the device |
| CN106782356A (en) * | 2016-11-21 | 2017-05-31 | 上海佳显机电科技有限公司 | A kind of drive device of monochromatic high gray liquid crystal display |
| CN108024149A (en) * | 2017-12-18 | 2018-05-11 | 青岛海信电器股份有限公司 | TCON plates and its method to SoC chip transmission signal, television set |
| CN108024149B (en) * | 2017-12-18 | 2020-09-04 | 海信视像科技股份有限公司 | Method for transmitting signal to SoC chip by TCON board through single connecting line, TCON board and television |
| CN108594698A (en) * | 2018-03-14 | 2018-09-28 | 深圳市火乐科技发展有限公司 | A kind of method for controlling projection and device of adaptation different platform projecting apparatus |
| CN108594698B (en) * | 2018-03-14 | 2021-08-31 | 深圳市火乐科技发展有限公司 | Projection control method and device adaptive to projectors of different platforms |
| CN110191253A (en) * | 2019-04-10 | 2019-08-30 | 电子科技大学 | LCoS micro-display drive control module based on FPGA |
| CN113315960A (en) * | 2021-05-14 | 2021-08-27 | 屏丽科技(深圳)有限公司 | LCOS chip resolution conversion method based on time color mixing |
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