CN211825751U - Flexible circuit board visual detection system based on DSP - Google Patents

Abstract

The utility model relates to a flexible circuit board visual detection system based on DSP, which comprises a detection processor module, an upper computer module and an image processing module; the detection processor with the DSP processor as the core, the image acquisition module with the high-speed linear array CCD as the visual sensor and the upper mechanism as the visual detection system realize the image acquisition data transportation and the rapid cyclic access through the PPI interface and DMA coordinated working mode, and the image segmentation detection function is completed by adopting the rapid local automatic threshold segmentation algorithm. With prior art digital vision detection equipment compares each other, the utility model has the functions of small, the low power dissipation, the image acquisition time quantum, resolution ratio is high.

Description

Flexible circuit board visual detection system based on DSP

[ technical field ] A method for producing a semiconductor device

The utility model relates to a flexible circuit board visual inspection system based on DSP for production line and chip mounter technical field.

[ background of the invention ]

In recent years, with the rapid development of science and technology, human life has entered a high-speed information age. Due to the increasing demand for information quantity, the requirement for information transmission is higher and higher, and new efficient transmission modes are continuously developed. Since a Flexible Printed Circuit (FPC) has advantages of easy folding, light weight, thin thickness, etc., it has been widely used in consumer electronics such as mobile phones, notebook computers, digital video cameras, etc. At present, the flexible circuit board production line and the chip mounting process need to move to acquire pictures, detect product defects and carry out vision correction in the chip mounting process. However, in general, digital visual inspection equipment is adopted to acquire technical defects such as color images, product defects and the like required to move in the production line and the patch process. The digital visual detection equipment is mostly realized by adopting an area array CCD, a general PC, a high-speed image acquisition card and a VC + + based software platform. The digital visual detection equipment system has large volume, high power consumption, high cost, long image acquisition time and insufficient horizontal resolution, so that the production requirement of the flexible circuit board is difficult to meet.

[ Utility model ] content

In view of this, the utility model aims to solve the technical problem that a flexible circuit board visual inspection system based on DSP that has small, the low power dissipation, the image acquisition time quantum, resolution ratio is high is provided.

Therefore, the technical problem is solved, the flexible circuit board vision detection system based on the DSP in the technical scheme of the utility model comprises a detection processor module, an upper computer module and an image processing module; the image processing module is connected with the upper computer module, and the detection processor module is respectively connected with the upper computer module and the image processing module; the detection processor module is a detection chip with a DSP (digital signal processor) as a core and the type of BLACK FIN533, and an SDRAM (synchronous dynamic random access memory) which is expanded by 32M through an external bus interface and is used for storing images and program codes; a memory for 4MB of FLASH for image storage and program code storage through an external bus interface extension 32M; the upper computer module comprises a controller and a first serial bus interface connected to the controller; the image processing module comprises an image acquisition hardware module, a high-speed A/D conversion module connected to the image acquisition hardware module, a second serial bus interface and a CPLD module which are respectively connected to the output end of the high-speed A/D conversion module, a PPI interface and an I/O interface which are respectively connected to the CPLD module, an FIFO memory connected to the CPLD module, an EBIU module connected to the FIFO memory, and a display connected to the CPLD module; the image acquisition hardware module adopts a high-speed linear array CCD as a visual sensor; the visual sensor is an enhanced image-sensitive CCD, is suitable for high-speed and high-resolution image collectors, adopts a single-channel output mode, has the highest driving frequency of 40MHz, and has pixels of 2048 lines.

It is further defined that the image acquisition hardware module includes a VSP converter coupled to the vision sensor, an EPM570 chip, a port1 interface coupled to the VSP converter, a PPI interface coupled to the EPM570 chip, and a blackgin-DSP interface coupled between the port1 interface and the PPI interface.

The utility model has the advantages of: according to the technical scheme, the detection processor with the DSP as the core is adopted, the high-speed linear array CCD is used as the visual sensor to form an image acquisition module, the upper mechanism forms a visual detection system, the PPI interface and the DMA are coordinated to realize image acquisition data transportation and rapid cyclic access, and the rapid local automatic threshold segmentation algorithm is adopted to complete the image segmentation detection function. With prior art digital vision detection equipment compares each other, the utility model has the functions of small, the low power dissipation, the image acquisition time quantum, resolution ratio is high.

The technical solution of the present invention will be described in further detail with reference to the accompanying drawings and embodiments.

[ description of the drawings ]

Fig. 1 is a schematic diagram of a flexible circuit board vision inspection system based on DSP in the present invention;

fig. 2 is a schematic diagram of the middle image capturing hardware module of the present invention.

[ detailed description ] embodiments

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention clearer and more obvious, the following description of the present invention with reference to the accompanying drawings and embodiments is provided for further details. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

Referring to fig. 1 and 2, a DSP-based flexible circuit board visual inspection system is described below with reference to an embodiment, which includes an inspection processor module, an upper computer module and an image processing module; the image processing module is connected with the upper computer module, and the detection processor module is respectively connected with the upper computer module and the image processing module.

The detection processor module is a detection chip with a DSP (digital signal processor) as a core and the type of BLACK FIN533, and an SDRAM (synchronous dynamic random access memory) which is expanded by 32M through an external bus interface and is used for storing images and program codes; and 4MB of FLASH for image storage and program code storage through an external bus interface extension 32M. The upper computer module comprises a controller and a first serial bus interface connected to the controller. The controller is formed by adopting a controller of a chip with the model number of ARM 7. The first serial bus interface is a SPORTO interface. The controller is mainly used for finishing man-machine interaction and sending instructions through a serial SPORTO interface of the detection processor module. The detection processor module mainly completes the functions of image signal acquisition, video decoding, image caching, defect display and the like.

The image processing module comprises an image acquisition hardware module, a high-speed A/D conversion module connected to the image acquisition hardware module, a second serial bus interface and a CPLD module which are respectively connected to the output end of the high-speed A/D conversion module, a PPI interface and an I/O interface which are respectively connected to the CPLD module, a FIFO memory connected to the CPLD module, an EBIU module connected to the FIFO memory, and a display connected to the CPLD module.

The image acquisition hardware module acquires image signals, the image signals are converted into digital signals through the high-speed A/D conversion module and then decoded by the CPLD module, the DSP processor acquires images through 2048 x 40 pixels per frame through the parallel peripheral PPI interface, and sends instructions to the CPLD module through the I/O interface to adjust gain and line frequency. In the running process of the product, the DSP continuously stores image data frames in the SDRAM memory to form a complete FPC image, then the data is transported to a cache memory through the DMA memory, linear stretching, threshold segmentation and morphological filtering are carried out on the image, whether the image has defects or not is detected, finally the defect image is transmitted to the FIFO memory, and the image is input into a display through the VGA interface to be displayed. The system can acquire 1 frame 2048 × 1536 gray-scale map within 50 ms, and the horizontal and vertical detection resolution is 0.05 mm is multiplied by 0.02mm, and the image can be quickly and effectively detected.

The image acquisition hardware module comprises a VSP converter connected with the vision sensor, an EPM570 chip, a SPORT1 interface connected with the VSP converter, a PPI interface connected on the EPM570 chip, and a BLACKFIN-DSP interface connected between the SPORT1 interface and the PPI interface.

The image acquisition hardware module adopts a high-speed linear array CCD as a visual sensor; the visual sensor is an enhanced image-sensitive CCD, is suitable for high-speed and high-resolution image collectors, adopts a single-channel output mode, has the highest driving frequency of 40MHz, and has pixels of 2048 lines.

When the image acquisition hardware module works normally, 5 paths of driving signals are needed, a register reading clock signal CR1 and a register reading clock signal CR2, a transfer signal TCK, a reset signal RST and a register reading tail end signal CRLAST are needed. Therefore, the system adopts a CPLD module to generate a driving time sequence of 40MHz, an image acquisition hardware module outputs analog image signals of 2048 effective pixels by an OS within the light integration time of one TCK, and then the signals are subjected to A/D conversion by a VSP converter.

The VSP converter is a 10-bit single-channel A/D converter specially used for CCD sensor image acquisition, supports a double-sampling technology, and is internally provided with an input clamping circuit and a programmable gain amplifier. The system provides SR signals, SV signals and ADCCLK time sequence signals through the CPLD, and adjusts the double sampling process; meanwhile, the VSP converter provides the serial interfaces SCLK, SDIN and CS time sequence through the SPORT1 port, configures a chip working register, performs gain adjustment, and outputs 8bi image signals to the CPLD module for time sequence logic processing. The CPLD module provides the PPI interface with an 80MHz drive clock (PPICLK), a frame synchronization signal (FRCLK), a line synchronization signal (FS1), and an image data signal.

The DSP processor provides a parallel peripheral PPI interface special for image data transmission, which is a multifunctional parallel synchronous quasi-bidirectional interface capable of being configured to 8-16 bit data width and is suitable for high-speed continuous input and output of large amount of data. The PPI interface adopts a synchronous general input mode and sets the data width of 8 bits. The frame synchronization signal initiates the PPI configuration driven by the external clock PPICLK. After the PPI interface receives the rising edge trigger of the line synchronization signal FS1, the clock period set by the PPIDELAY register is delayed, and the image data in the data line is valid; and acquiring 8-bit data in each clock, acquiring PPICOUN times in each line, and completing 1-frame image acquisition after completing the transmission of PPIFRAME line image data.

According to PPI image acquisition characteristics, destructive writing of image data is prevented, each frame of image processing is independent of other data frames and is accurately carried out in real time, 3 image buffer areas with the storage space of 4MB are opened up in an external buffer SDRAM (synchronous dynamic random access memory) storage by the system, and a 2048 multiplied by 1536 image is respectively stored; each block of memory is subdivided into 40 banks, each bank storing one frame of image and being adapted independently of the processor core.

The mobile controller is used as a data moving channel, so that the bottleneck of data transmission in the image acquisition process can be solved, and the image data moving and the parallel execution of the image algorithm are realized.

In view of the hierarchical storage structure of the DSP processor, the processing speed of the on-chip high-speed cache is synchronous with the core clock, the reading and writing speed is higher than that of an external SDRAM (synchronous dynamic random access memory), if the image data in the off-chip SDRAM is directly read and written, great access delay can be caused, and the real-time performance is poor. Therefore, the system adopts a DMA memory channel to carry the currently required off-chip data to an internal cache region for algorithmic processing. To ensure that image processing and DMA data movement are performed in parallel, the system opens up a set of buffers to prevent corruption of the data.

The cache region is operated in the program, so that the data flow is carried orderly, and the algorithm is quickly and effectively executed, thereby providing an embedded automatic vision detection system which takes the DSP as a processor core and an image acquisition hardware module of the high-speed linear array as a vision sensor. Through the PPI port and DMA (direct memory access) for assisting data handling, the system can rapidly acquire and store high-resolution moving images on the flexible circuit board; and according to the storage framework of the processor, a rapid local automatic threshold segmentation algorithm is adopted to complete the automatic image segmentation detection function. The device is arranged on a production line with the height of 0.3m and the speed of 1.6m/s, and can realize the purpose of image acquisition with the transverse and longitudinal resolution of 0.05 mm multiplied by 0.02 mm.

According to the technical scheme, the detection processor with the DSP as the core is adopted, the high-speed linear array CCD is used as the visual sensor to form an image acquisition module, the upper mechanism forms a visual detection system, the PPI interface and the DMA are coordinated to realize image acquisition data transportation and rapid cyclic access, and the rapid local automatic threshold segmentation algorithm is adopted to complete the image segmentation detection function. With prior art digital visual inspection equipment compares each other, the utility model discloses have small, the low power dissipation, the image acquisition time quantum, the function that resolution ratio is high.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, without thereby limiting the scope of the invention. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the claims of the present invention.

Claims (2)

1. A flexible circuit board visual detection system based on DSP comprises a detection processor module, an upper computer module and an image processing module; the image processing module is connected with the upper computer module, and the detection processor module is respectively connected with the upper computer module and the image processing module; the method is characterized in that: the detection processor module is a detection chip with a DSP (digital signal processor) as a core and the type of BLACK FIN533, and an SDRAM (synchronous dynamic random access memory) which is expanded by 32M through an external bus interface and is used for storing images and program codes; a memory for 4MB of FLASH for image storage and program code storage through an external bus interface extension 32M; the upper computer module comprises a controller and a first serial bus interface connected to the controller; the image processing module comprises an image acquisition hardware module, a high-speed A/D conversion module connected to the image acquisition hardware module, a second serial bus interface and a CPLD module which are respectively connected to the output end of the high-speed A/D conversion module, a PPI interface and an I/O interface which are respectively connected to the CPLD module, an FIFO memory connected to the CPLD module, an EBIU module connected to the FIFO memory, and a display connected to the CPLD module; the image acquisition hardware module adopts a high-speed linear array CCD as a visual sensor; the visual sensor is an enhanced image-sensitive CCD, is suitable for high-speed and high-resolution image collectors, adopts a single-channel output mode, has the highest driving frequency of 40MHz, and has pixels of 2048 lines.

2. The DSP based visual inspection system of flexible circuit board of claim 1, wherein: the image acquisition hardware module comprises a VSP converter connected with the vision sensor, an EPM570 chip, a SPORT1 interface connected with the VSP converter, a PPI interface connected on the EPM570 chip, and a BLACKFIN-DSP interface connected between the SPORT1 interface and the PPI interface.

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