CN1862644A

CN1862644A - Image data storage circuit in LCOS

Info

Publication number: CN1862644A
Application number: CN 200510025738
Authority: CN
Inventors: 郭俊; 曹辉; 印义言
Original assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Current assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Priority date: 2005-05-11
Filing date: 2005-05-11
Publication date: 2006-11-15

Abstract

The present invention relates to an image data storage circuit in LCOS. It is characterized by the image data from DVI signal converter and line and frame synchronous signal can be transferred to control circuit and the reset control signal from system control circuit can be transferred to reset circuit, the clock control signal from system control circuit can be transferred to clock circuit; when the power supply is connected or the system is reset, the reset signal produced by the described reset circuit and the instruction sent by means of control circuit can make first SDRAM memory and second SDRAM memory clear; the clock signal which is produced by the described clock circuit and is required for first SDRAM memory and second SDRAM memory can be transferred to control circuit; the described control circuit makes the received line and frame synchronous signal send writing instruction to first SDRAM memory or second SDRAM memory, at the same time, send reading instruction to second SDRAM memory or first SDRAM memory, and utilize control circuit to transfer said instruction to display drive circuit.

Description

Pictorial data memory circuit among the LCOS

Technical field

The present invention relates to a kind of high definition digital display technique---LCOS (Liquid CrystalOn Silicon is promptly based on the reflective liquid crystal shadow casting technique on the large scale integrated circuit) relates in particular to the pictorial data memory circuit in this shadow casting technique.

Background technology

The high definition LCOS of a new generation microplate display technique is present up-to-date in the world large-screen high-resolution number of degrees word display technique---LCOS; LCOS does packaged liquid crystal cell and integrated circuit (IC) chip together.Because adopt silicon technology, comparing its cost of products with other technology can be very low; LCOS has the resolution height, the light aperture is big, Pixel Dimensions is little, contrast is high, bright in luster, power consumptive province, pollution-free, in light weight, low cost of manufacture and compatible outstanding advantage such as good, will be one of future world display technique important development direction.

LCOS is consistent in the world having an optimistic view of, and most possibly with the product technology that instinct enters the HDTV of ordinary people family that manufactures of its high-quality technical indicator and low price, has very vast market prospect.

The LCOS technology adopts on the large scale integrated chip and makes SRAM (static RAM) array, and liquid crystal cell is encapsulated in forms reflective liquid crystal light valve on the large scale integrated chip (LSI chip); Form 3 coloured light driving engine by the LCOS display module that the chip of 3 band liquid crystal cells is made, can produce 24 colored videos of high-contrast, high brightness that HDTV separates degree of elephant.

And just needing to make the array that 1920*1080=2073600 pixel formed for the Xie Xiangdu of HDTV, the digital signal according to image during work adds ITO voltage on the liquid crystal back electrode, and adds image digital signal voltage VP on each pixel respectively.

As seen from Figure 1: the digital video signal of high definition digital television adopts DVI three chromatic number word video differential signals, deliver to the DVI signal converter through data-switching through the DVI connector, synchronously and decoding, produce red, green, common 48bit parallel data signal of Lan Sanse and row, frame synchronizing signal are delivered to the pictorial data memory circuit, and the pictorial data memory circuit is made up of SDRAM storer and controller.Under system, control circuit control, deliver to display driver circuit after depositing frame image data in.Deliver to the LCOS display chip by display driver circuit.The LCOS display chip adopts the SRAM memory array.Each SRAM storer is formed a group of pixels and is become cell array.And liquid crystal cell is encapsulated in forms reflective liquid crystal light valve on the cell array, be example with XGA form (1024*768 cell array), be a write cycle time with 32bit, in 32 write cycle times, write 1024 data of delegation altogether.Vertically have 768 row, delegation of data delegation is transfused among the whole memory arrays.Each pixel is become by 82 system arrays.Form 2 ⁸Individual gray shade scale.The photoelectric display effect of liquid crystal produces whole 2 ⁸Individual catoptrical gray shade scale.

Present pictorial data memory circuit adopts SDRAM storage and controller, is characterized in adopting sending instruction, receives instruction, such series process is handled in read-write, fast, in the large-capacity data transmission, produce the time of a lot of waits, greatly reduced transmission speed.

Summary of the invention

The technical issues that need to address of the present invention have provided the pictorial data memory circuit among a kind of LCOS, are intended to solve above-mentioned defective.

In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions:

The present invention includes one the one SDRAM storer, a control circuit; Also comprise one the 2nd SDRAM storer; A reset circuit, a clock circuit; Pictorial data from the DVI signal converter and row, frame synchronizing signal are sent into control circuit and are sent into reset circuit by the reseting controling signal that system, control circuit comes, and send into clock circuit by the clock control signal that system, control circuit comes; When power connection or system reset, the reset signal that described reset circuit produces is also sent instruction by control circuit and is made a SDRAM storer, the 2nd SDRAM storer zero clearing; A SDRAM storer and the required clock signal of the 2nd SDRAM storer that described clock circuit produces are delivered to control circuit; The row that described control circuit will be received, frame synchronizing signal are sent write command to a SDRAM storer or the 2nd SDRAM storer, send simultaneously and read instruction, and send display driver circuit by control circuit to the 2nd SDRAM storer or a SDRAM storer.

Compared with prior art, the invention has the beneficial effects as follows: the SDRAM that can drive two high-speed high capacities simultaneously finishes the buffer memory of view data, has improved data-handling capacity; Owing to adopt parallel mode to handle external command, greatly reduce the stand-by period between the instruction execution, improved transmission speed.

Description of drawings

Fig. 1 is the block scheme of LCOS pictorial data passage;

Fig. 2 is a block scheme of the present invention;

Fig. 3 is the serial transmission synoptic diagram of prior art;

Fig. 4 is a parallel transmission synoptic diagram of the present invention;

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:

As seen from Figure 2: the present invention includes one the one SDRAM storer, a control circuit; Also comprise one the 2nd SDRAM storer; A reset circuit, a clock circuit; Pictorial data from the DVI signal converter and row, frame synchronizing signal are sent into control circuit and are sent into reset circuit by the reseting controling signal that system, control circuit comes, and send into clock circuit by the clock control signal that system, control circuit comes; When power connection or system reset, the reset signal that described reset circuit produces is also sent instruction by control circuit and is made a SDRAM storer, the 2nd SDRAM storer zero clearing; A SDRAM storer and the required clock signal of the 2nd SDRAM storer that described clock circuit produces are delivered to control circuit; The row that described control circuit will be received, frame synchronizing signal are sent write command to a SDRAM storer or the 2nd SDRAM storer, send simultaneously and read instruction, and send display driver circuit by control circuit to the 2nd SDRAM storer or a SDRAM storer;

The processing of a described SDRAM storer or the 2nd SDRAM memory write or the processing of reading are by parallel processing.

When system power supply connection or system reset, produce reseting controling signal from system, control circuit and deliver to reset circuit generation RST reset signal.Send instruction by control circuit and make a SDRAM, the 2nd SDRAM zero clearing.System, control circuit produces clock control signal to the clock circuit, clock circuit produces the required clock signal of reading and writing SDRAM and delivers to control circuit, control circuit receives row, beginning is sent 48bit pictorial data that write command comes the DVI signaling conversion circuit to a SDRAM and write a SDRAM since the start address of a SDRAM after the frame synchronizing signal, and whenever writing 48bit pictorial data the one SDRAM address increases automatically.All write a SDRAM until frame data.Control circuit sent to the 2nd SDRAM and reads instruction when the one SDRAM began to write data, and the former frame data that will deposit in since the 2nd SDRAM are read from the start address of the 2nd SDRAM, and send display driver circuit by control circuit.Whenever the address increases automatically after reading the 48bit data, read next 48bit data.Next frame data in the 2nd SDRAM are all read.After frame data read-write was finished, control circuit began to send write command to the 2nd SDRAM after receiving next frame synchronizing signal, begins to deposit the next frame pictorial data in the 2nd SDRAM.Control circuit sends and reads instruction simultaneously, and the previous frame data that begin to have deposited among the SDRAM begin to read and deliver to display driver circuit by control circuit from start address.Two SDRAM like this read and write in turn.Make the rapid access of data.Guarantee needed access speed.

When carrying out the operation of SDRAM, need carry out necessary several operations to SDRAM, carry out read or write subsequently.As shown in Figure 3, processing instruction is represented the operation that SDRAM reads or writes; Next bar instruction must be waited for after a last instruction is carried out and could receive, form the more instruction process stand-by period.Sdram controller has then been avoided the problems referred to above among the present invention, as seen from Figure 4: in a last execution process instruction, the transmission that has started next bar instruction receives, and before a last order fulfillment, be ready to the data or the address of next bar instruction, in case a last order fulfillment carries out the processing of next bar instruction at once.The instruction process stand-by period is 0, has greatly improved data rate.And provide very big performance boost space for the LCOS display system.

Claims

1. the pictorial data memory circuit among the LCOS comprises one the one SDRAM storer, a control circuit; It is characterized in that: also comprise one the 2nd SDRAM storer; A reset circuit, a clock circuit; Pictorial data from the DVI signal converter and row, frame synchronizing signal are sent into control circuit and are sent into reset circuit by the reseting controling signal that system, control circuit comes, and send into clock circuit by the clock control signal that system, control circuit comes; When power connection or system reset, the reset signal that described reset circuit produces is also sent instruction by control circuit and is made a SDRAM storer, the 2nd SDRAM storer zero clearing; A SDRAM storer and the required clock signal of the 2nd SDRAM storer that described clock circuit produces are delivered to control circuit; The row that described control circuit will be received, frame synchronizing signal are sent write command to a SDRAM storer or the 2nd SDRAM storer, send simultaneously and read instruction, and send display driver circuit by control circuit to the 2nd SDRAM storer or a SDRAM storer.

2. the pictorial data memory circuit among the LCOS according to claim 1 is characterized in that: the processing of a described SDRAM storer or the 2nd SDRAM memory write or the processing of reading are by parallel processing.

3. the pictorial data memory circuit among the LCOS according to claim 1 and 2, it is characterized in that: to be 48bit pictorial data that the DVI signaling conversion circuit is come write a SDRAM since the start address of a SDRAM to described write command, whenever writing 48bit pictorial data the one SDRAM address increases automatically, all writes a SDRAM until frame data; Described reading instruction is that the former frame data that will deposit in since the 2nd SDRAM are read from the start address of the 2nd SDRAM, and send display driver circuit by control circuit; Whenever the address increases automatically after reading the 48bit data, read next 48bit data, and the next frame data in the 2nd SDRAM are all read.

4. the pictorial data memory circuit among the LCOS according to claim 3, it is characterized in that: after frame data read-write is finished, control circuit begins to send write command to the 2nd SDRAM after receiving next frame synchronizing signal, begins to deposit the next frame pictorial data in the 2nd SDRAM; Control circuit sends and reads instruction simultaneously, and the previous frame data that begin to have deposited among the SDRAM begin to read and deliver to display driver circuit by control circuit from start address.