CN105450049A - Auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints - Google Patents
Auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints Download PDFInfo
- Publication number
- CN105450049A CN105450049A CN201610047419.1A CN201610047419A CN105450049A CN 105450049 A CN105450049 A CN 105450049A CN 201610047419 A CN201610047419 A CN 201610047419A CN 105450049 A CN105450049 A CN 105450049A
- Authority
- CN
- China
- Prior art keywords
- phase
- submodule
- brachium pontis
- module
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
The invention provides an auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints. In the half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology, a half-bridge/full-bridge parallel-serial MMC model is electrically connected with a self-voltage-sharing auxiliary loop through auxiliary switches in the auxiliary loop; the auxiliary switches are switched on, and the half-bridge/full-bridge parallel-serial MMC model and the self-voltage-sharing auxiliary loop form the auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on the inequality constraints; the auxiliary switches are switched off, and the topology is equivalent to the half-bridge/full-bridge parallel-serial MMC topology. Under the condition of not emphasizing the differences between the two topologies, 6K mechanical switches in the auxiliary switches can be omitted. By means of the half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology, the DC failure clamping capacity is achieved without depending on special voltage-sharing control; the capacitances and voltages of sub-modules can be balanced spontaneously on the basis of completing DC and AC energy conversion; meanwhile, the triggering frequencies and capacitance values of the sub-modules can be correspondingly reduced, and base-frequency modulation of MMC is achieved.
Description
Technical field
The present invention relates to flexible transmission field, being specifically related to the centralized half-bridge of a kind of auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC from all pressing topology.
Background technology
Modularization multi-level converter MMC is the developing direction of following HVDC Transmission Technology, MMC adopts submodule (Sub-module, SM) mode of cascade constructs converter valve, avoid the direct series connection of large metering device, reduce the conforming requirement of device, be convenient to dilatation and redundant configuration simultaneously.Along with the rising of level number, output waveform, close to sinusoidal, effectively can avoid the defect of low level VSC-HVDC.
Half-bridge/full-bridge series-parallel connection MMC is combined by half-bridge and full-bridge submodule, and half-bridge sub modular structure is simple, and cost is low, and running wastage is little, and full-bridge submodule has DC Line Fault clamping ability.
Different from two level, three level VSC, the DC voltage of MMC is not supported by a bulky capacitor, but is supported by a series of separate suspension submodule capacitances in series.In order to ensure the waveform quality that AC voltage exports and ensure that in module, each power semiconductor bears identical stress, also in order to better support direct voltage, reduce alternate circulation, must ensure that submodule capacitor voltage is in the state of dynamic stability in the periodicity flowing of brachium pontis power.
Sequence based on capacitance voltage sequence all presses algorithm to be the main flow thinking solving MMC Neutron module capacitance voltage equalization problem at present, but also constantly to expose its some inherent shortcomings.First, the realization of ranking function must rely on the Millisecond sampling of capacitance voltage, needs a large amount of transducers and optical-fibre channel to be coordinated; Secondly, when group number of modules increases, the operand of capacitance voltage sequence increases rapidly, for the hardware designs of controller brings huge challenge; In addition, sequence all presses the cut-off frequency of the realization of algorithm to submodule to have very high requirement, cut-offs frequency and all presses effect to be closely related, in practice process, may because all press the restriction of effect, the trigger rate of raising submodule of having to, and then bring the increase of converter loss.
Document " ADC-LinkVoltageSelf-BalanceMethodforaDiode-ClampedModula rMultilevelConverterWithMinimumNumberofVoltageSensors ", proposes a kind of clamp diode and transformer of relying on to realize the thinking of MMC submodule capacitor voltage equilibrium.But the program to a certain degree destroys the modular nature of submodule in design, submodule capacitive energy interchange channel is also confined to mutually, the existing structure of MMC could not be made full use of, while being introduced in of three transformers makes control strategy complicated, also can bring larger improvement cost.
Summary of the invention
For the problems referred to above, the object of the invention is to propose a kind of economy, modular, do not rely on and all press algorithm, simultaneously can corresponding reduction submodule trigger rate and capacitor's capacity and the half-bridge/full-bridge series-parallel connection MMC with DC Line Fault clamping ability from all pressing topology.
The concrete constituted mode of the present invention is as follows.
The centralized half-bridge of auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC is from all pressing topology, comprise the half-bridge MMC model be made up of A, B, C three-phase, each brachium pontis of A, B, C three-phase is in series by K half-bridge submodule, a N-K full-bridge submodule and 1 brachium pontis reactor respectively; Comprise by 6N auxiliary switch (6K mechanical switch, 6N-6K IGBT module), 6N+7 clamp diode, 4 auxiliary capacitors, 2 auxiliary IGBT module compositions from all pressing subsidiary loop.
The centralized half-bridge of the above-mentioned auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC is from all pressing topology, 1st submodule of brachium pontis in A phase, its submodule electric capacity negative pole is connected with the 2nd sub-module I GBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is upwards connected with DC bus positive pole; I-th submodule of brachium pontis in A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity negative pole is connected with the i-th+1 sub-module I GBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is upwards connected with the i-th-1 sub-module capacitance negative pole of brachium pontis in A phase; K half-bridge submodule of brachium pontis in A phase, its submodule electric capacity negative pole is connected with K+1 submodule IGBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is upwards connected with K-1 sub-module capacitance negative pole of brachium pontis in A phase; A jth submodule of brachium pontis in A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in A phase downwards, and another IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in A phase; The N number of submodule of brachium pontis in A phase, its submodule IGBT module mid point is downwards through two brachium pontis reactor L
0be connected with the 1st sub-module I GBT module mid point of the lower brachium pontis of A phase, another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis in A phase; I-th submodule of the lower brachium pontis of A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity negative pole downwards brachium pontis the i-th+1 sub-module I GBT module mid point lower to A phase is connected, and its IGBT module mid point upwards brachium pontis the i-th-1 sub-module capacitance negative pole lower to A phase is connected; K submodule of the lower brachium pontis of A phase, its submodule electric capacity negative pole downwards brachium pontis K+1 submodule IGBT module mid point lower to A phase is connected, and its submodule IGBT module mid point upwards brachium pontis K-1 sub-module capacitance negative pole lower to A phase is connected; The lower brachium pontis jth submodule of A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point downwards brachium pontis jth+1 submodule IGBT module mid point lower to A phase is connected, and another IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to A phase is connected; The lower brachium pontis N number of submodule IGBT module mid point of A phase is connected with DC bus negative pole downwards, and another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis under A phase.1st submodule of brachium pontis in B phase, its submodule capacitance cathode is upwards connected with DC bus positive pole, and its submodule IGBT module mid point is connected with the 2nd sub-module capacitance positive pole of brachium pontis in B phase downwards; I-th submodule of brachium pontis in B phase, wherein the value of i is 2 ~ K-1, its submodule capacitance cathode is upwards connected with the i-th-1 sub-module I GBT module mid point of brachium pontis in B phase, and its submodule IGBT module mid point is connected with the i-th+1 sub-module capacitance positive pole of brachium pontis in B phase downwards; K submodule of brachium pontis in B phase, its submodule capacitance cathode is upwards connected with K-1 sub-module I GBT module mid point of brachium pontis in B phase, and its submodule IGBT module mid point is connected with brachium pontis K+1 submodule IGBT module mid point in B phase downwards; A jth submodule of brachium pontis in B phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in B phase downwards; The N number of submodule of brachium pontis in B phase, its submodule IGBT module mid point is upwards connected with brachium pontis N-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is downwards through two brachium pontis reactor L
0be connected with the 1st sub-module capacitance positive pole of the lower brachium pontis of B phase; I-th submodule of the lower brachium pontis of B phase, wherein the value of i is 2 ~ K-1, its submodule capacitance cathode is upwards connected with the i-th-1 sub-module I GBT module mid point of brachium pontis under B phase, and its submodule IGBT module mid point is connected with the i-th+1 sub-module capacitance positive pole of brachium pontis under B phase downwards; K submodule of the lower brachium pontis of B phase, its submodule capacitance cathode upwards brachium pontis K-1 sub-module I GBT module mid point lower to B phase is connected, and its submodule IGBT module mid point downwards brachium pontis K+1 submodule IGBT module mid point lower to B phase is connected; The lower brachium pontis jth submodule of B phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point downwards brachium pontis jth+1 submodule IGBT module mid point lower to B phase is connected; The lower N number of submodule of brachium pontis of B phase, its submodule IGBT module mid point upwards brachium pontis N-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point is connected with DC bus negative pole downwards.The connected mode of C phase upper and lower bridge arm submodule is consistent with A phase or B.
From all pressing in subsidiary loop, first auxiliary capacitor is in parallel by clamp diode with second auxiliary capacitor, and second auxiliary capacitor positive pole connects auxiliary IGBT module first auxiliary capacitor negative pole connection clamp diode and be incorporated to DC bus positive pole; 3rd auxiliary capacitor is in parallel by clamp diode with the 4th auxiliary capacitor, and the 3rd auxiliary capacitor negative pole connects auxiliary IGBT module the 4th auxiliary capacitor positive pole connection clamp diode and be incorporated to DC bus negative pole.Clamp diode, by the 1st sub-module capacitance and first auxiliary capacitor positive pole in brachium pontis in auxiliary switch connection A phase; By i-th sub-module capacitance and the i-th+1 sub-module capacitance positive pole in brachium pontis in auxiliary switch connection A phase, wherein the value of i is 1 ~ N-1; By N number of submodule electric capacity and lower brachium pontis the 1st the sub-module capacitance positive pole of A phase in brachium pontis in auxiliary switch connection A phase; Connect i-th sub-module capacitance brachium pontis the i-th+1 sub-module capacitance positive pole lower to A phase in the lower brachium pontis of A phase by auxiliary switch, wherein the value of i is 1 ~ N-1; N number of submodule electric capacity and the 3rd auxiliary capacitor positive pole in the lower brachium pontis of A phase is connected by auxiliary switch.Clamp diode, connects the negative pole of the 1st sub-module capacitance and second auxiliary capacitor in brachium pontis in B phase by auxiliary switch; Connected the negative pole of i-th sub-module capacitance and the i-th+1 sub-module capacitance in brachium pontis in B phase by auxiliary switch, wherein the value of i is 1 ~ N-1; By the negative pole of N number of submodule electric capacity in brachium pontis in auxiliary switch connection B phase with lower brachium pontis the 1st the sub-module capacitance of B phase; To be connected in the lower brachium pontis of B phase the negative pole of i-th sub-module capacitance and the sub-module capacitance of brachium pontis the i-th+1 under B phase by auxiliary switch, wherein the value of i is 1 ~ N-1; The negative pole of N number of submodule electric capacity and the 4th auxiliary capacitor in the lower brachium pontis of B phase is connected by auxiliary switch.The annexation of C phase clamp diode is corresponding with the annexation of its submodule.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1 is the structural representation of half-bridge submodule;
Fig. 2 is the structural representation of full-bridge submodule;
Fig. 3 is from all pressing topology based on the centralized half-bridge of the auxiliary capacitor/full-bridge series-parallel connection MMC of inequality constraints.
Embodiment
For setting forth performance of the present invention and operation principle further, below in conjunction with accompanying drawing, the constituted mode of invention and operation principle are specifically described.But be not limited to Fig. 3 based on the half-bridge/full-bridge series-parallel connection MMC of this principle from all pressing topology.
With reference to figure 3, the centralized half-bridge of auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC is from all pressing topology, comprise the half-bridge/full-bridge series-parallel connection MMC model be made up of A, B, C three-phase, each brachium pontis of A, B, C three-phase is in series by K half-bridge submodule, a N-K full-bridge submodule and 1 brachium pontis reactor respectively; Comprise by 6N auxiliary switch (6K mechanical switch, 6N-6K IGBT module), 6N+7 clamp diode, 4 auxiliary capacitors, 2 auxiliary IGBT module compositions from all pressing subsidiary loop.
In half-bridge/full-bridge series-parallel connection MMC model, the 1st submodule of brachium pontis in A phase, its submodule electric capacity C-
au-_1negative pole is connected with the 2nd sub-module I GBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is upwards connected with DC bus positive pole; I-th submodule of brachium pontis in A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
au-_inegative pole is connected with the i-th+1 sub-module I GBT module mid point of brachium pontis in A phase downwards, its submodule IGBT module mid point upwards with the i-th-1 sub-module capacitance C of brachium pontis in A phase
-au-_i-1negative pole is connected; K half-bridge submodule of brachium pontis in A phase, its submodule electric capacity C
-au-_Knegative pole is connected with K+1 submodule IGBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is sub-module capacitance C-individual with the K-1 of brachium pontis in A phase upwards
au-_K-1negative pole is connected; A jth submodule of brachium pontis in A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in A phase downwards, and another IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in A phase; The N number of submodule of brachium pontis in A phase, its submodule IGBT module mid point is downwards through two brachium pontis reactor L
0be connected with the 1st sub-module I GBT module mid point of the lower brachium pontis of A phase, another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis in A phase; I-th submodule of the lower brachium pontis of A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
al-_inegative pole downwards brachium pontis the i-th+1 sub-module I GBT module mid point lower to A phase is connected, and its IGBT module mid point is the lower sub-module capacitance C-of brachium pontis the i-th-1 with A phase upwards
al-_i-1negative pole is connected; K submodule of the lower brachium pontis of A phase, its submodule electric capacity C
-al_Knegative pole downwards brachium pontis K+1 submodule IGBT module mid point lower to A phase is connected, and its submodule IGBT module mid point is lower brachium pontis K-1 the sub-module capacitance C-with A phase upwards
al-_K-1negative pole is connected; The lower brachium pontis jth submodule of A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point downwards brachium pontis jth+1 submodule IGBT module mid point lower to A phase is connected, and another IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to A phase is connected; The lower brachium pontis N number of submodule IGBT module mid point of A phase is connected with DC bus negative pole downwards, and another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis under A phase.1st submodule of brachium pontis in B phase, its submodule electric capacity C
-bu-_1positive pole is upwards connected with DC bus positive pole, its submodule IGBT module mid point downwards with the 2nd sub-module capacitance C of brachium pontis in B phase
-bu-_2positive pole is connected; I-th submodule of brachium pontis in B phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
bu-_ipositive pole is upwards connected with the i-th-1 sub-module I GBT module mid point of brachium pontis in B phase, its submodule IGBT module mid point downwards with the i-th+1 sub-module capacitance C-of brachium pontis in B phase
bu-_i+1positive pole is connected; K submodule of brachium pontis in B phase, its submodule electric capacity C-
bu-_Kpositive pole is upwards connected with K-1 sub-module I GBT module mid point of brachium pontis in B phase, and its submodule IGBT module mid point is connected with brachium pontis K+1 submodule IGBT module mid point in B phase downwards; A jth submodule of brachium pontis in B phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in B phase downwards; The N number of submodule of brachium pontis in B phase, an one IGBT module mid point is upwards connected with brachium pontis N-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is downwards through two brachium pontis reactor L
0with the 1st sub-module capacitance C of the lower brachium pontis of B phase
-bl-_1positive pole is connected; I-th submodule of the lower brachium pontis of B phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C
-bl_ipositive pole upwards descends the i-th-1 sub-module I GBT module mid point of brachium pontis to be connected with B phase, and its submodule IGBT module mid point descends the i-th+1 sub-module capacitance C-of brachium pontis with B phase downwards
bl-_i+1positive pole is connected; K submodule of the lower brachium pontis of B phase, its submodule electric capacity C
-bl_Kpositive pole upwards brachium pontis K-1 sub-module I GBT module mid point lower to B phase is connected, and its submodule IGBT module mid point downwards brachium pontis K+1 submodule IGBT module mid point lower to B phase is connected; The lower brachium pontis jth submodule of B phase, wherein the value of j is K+2 ~ N-1, an one IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point downwards brachium pontis jth+1 sub-module I GBT IGBT module mid point lower to B phase is connected; The lower N number of submodule of brachium pontis of B phase, its submodule IGBT module mid point upwards brachium pontis N-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point is connected with DC bus negative pole downwards.The connected mode of C phase upper and lower bridge arm submodule is consistent with A.
From all pressing in subsidiary loop, auxiliary capacitor C
1with auxiliary capacitor C
2in parallel by clamp diode, auxiliary capacitor C
2positive pole connects auxiliary IGBT module T
1, auxiliary capacitor C
1negative pole connects clamp diode and is incorporated to DC bus positive pole; Auxiliary capacitor C
3with auxiliary capacitor C
4in parallel by clamp diode, auxiliary capacitor C
3negative pole connects auxiliary IGBT module T
2, auxiliary capacitor C
4positive pole connects clamp diode and is incorporated to DC bus negative pole.Clamp diode, by auxiliary switch K
au_121st sub-module capacitance C in brachium pontis in connection A phase
-au-_1with auxiliary capacitor C
1positive pole; By auxiliary switch K
au_i2, K
au_(i+1) 2i-th sub-module capacitance C in brachium pontis in connection A phase
-au-_iwith the i-th+1 sub-module capacitance C
-au-_i+1positive pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
au_K2, T
au_K+1k sub-module capacitance C in brachium pontis in connection A phase
-au-_Kwith K+1 sub-module capacitance C-
au_K+1positive pole; By auxiliary switch T
au_j, T
au_j+1a jth sub-module capacitance C in brachium pontis in connection A phase
-au-_jmodule capacitance C with jth+1
-au-_j+1positive pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
au_N, K
al_12n number of submodule electric capacity C-in brachium pontis in connection A phase
au_Nbrachium pontis 1st sub-module capacitance C lower to A phase
-al-_1positive pole; By auxiliary switch K
al_i2, K
al_(i+1) 2connect i-th sub-module capacitance C in the lower brachium pontis of A phase
-al-_iwith the i-th+1 sub-module capacitance C
-al-_i+1positive pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
al_K2, T
al_K+1connect K sub-module capacitance C-in the lower brachium pontis of A phase
al-_Kwith K+1 sub-module capacitance C-
al-_K+1positive pole; By auxiliary switch T
al_j, T
al_j+1connect a jth sub-module capacitance C in the lower brachium pontis of A phase
-al_jmodule capacitance C with jth+1
-al-_j+1positive pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
al_Nconnect N number of submodule electric capacity C in the lower brachium pontis of A phase
-al_Nwith auxiliary capacitor C
3positive pole.Clamp diode, by auxiliary switch K
bu_121st sub-module capacitance C in brachium pontis in connection B phase
-bu-_1with auxiliary capacitor C
2negative pole; By auxiliary switch K
bu_i2, K
bu_(i+1) 2i-th sub-module capacitance C-in brachium pontis in connection B phase
bu-_iwith the i-th+1 sub-module capacitance C-
bu-_i+1negative pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
bu_K2, T
bu_K+1k sub-module capacitance C-in brachium pontis in connection B phase
bu-_Kwith K+1 sub-module capacitance C-
bu-_K+1negative pole; By auxiliary switch T
bu_j, T
bu_j+1a jth sub-module capacitance C-in brachium pontis in connection B phase
bu-_jmodule capacitance C-with jth+1
bu-_j+1negative pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
bu_N, K
bl_12n number of submodule electric capacity C-in brachium pontis in connection B phase
bu-_Nwith the 1st sub-module capacitance C-in the lower brachium pontis of B phase
bl_1negative pole; By auxiliary switch K
bl_i2, K
bl_(i+1) 2connect i-th sub-module capacitance C-in the lower brachium pontis of B phase
bl-_iwith the i-th+1 sub-module capacitance C-
bl-_i+1negative pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
bl_K2, T
bl_K+1connect K sub-module capacitance C-in the lower brachium pontis of B phase
bl_Kwith K+1 sub-module capacitance C-
bl-_K+1negative pole; By auxiliary switch T
bl_j, T
bl_j+1connect a jth sub-module capacitance C-in the lower brachium pontis of B phase
bl-_jmodule capacitance C-with jth+1
bl_j+1negative pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
bl_Nconnect N number of submodule electric capacity C in the lower brachium pontis of B phase
-bl-_Nwith auxiliary capacitor C
4negative pole.The annexation of C phase clamp diode is consistent with A.
Under normal circumstances, from all pressing 6N auxiliary switch K in subsidiary loop
au_i2, K
al_i2, K
bu_i2, K
bl_i2, K
cu_i2, K
cl_i2, T
au_j, T
al_j, T
bu_j, T
bl_j, T
cu_j, T
cl_jnormally closed, wherein the value of i is the value of 1 ~ K, j is brachium pontis first sub-module capacitance C-in K+1 ~ N, A phase
au-_1during bypass, now auxiliary IGBT module T
1disconnect, submodule electric capacity C
-au-_1with auxiliary capacitor C
1in parallel by clamp diode; Brachium pontis i-th sub-module capacitance C-in A phase
au-_iduring bypass, wherein the value of i is 2 ~ N, submodule electric capacity C-
au-_iwith submodule electric capacity C-
au-_i-1in parallel by clamp diode; Lower brachium pontis first the sub-module capacitance C-of A phase
al_1during bypass, submodule electric capacity C-
al-_1by clamp diode, two brachium pontis reactor L
0with submodule electric capacity C-
au-_Nin parallel; Lower brachium pontis i-th the sub-module capacitance C-of A phase
al_iduring bypass, wherein the value of i is 2 ~ N, submodule electric capacity C-
al-_iwith submodule electric capacity C-
al_i-1in parallel by clamp diode; Auxiliary IGBT module T
2time closed, auxiliary capacitor C
3by clamp diode and submodule electric capacity C-
al_Nin parallel.
Under normal circumstances, from all pressing 6N auxiliary switch K in subsidiary loop
au_i2, K
al_i2, K
bu_i2, K
bl_i2, K
cu_i2, K
cl_i2, T
au_j, T
al_j, T
bu_j, T
bl_j, T
cu_j, T
cl_jnormally closed, wherein the value of i is the value of 1 ~ K, j is K+1 ~ N, auxiliary IGBT module T
1time closed, auxiliary capacitor C
2with submodule electric capacity C-
bu-_1in parallel by clamp diode; Brachium pontis i-th sub-module capacitance C-in B phase
bu-_iduring bypass, wherein the value of i is 1 ~ N-1, submodule electric capacity C-
bu-_iwith submodule electric capacity C-
bu-_i+1in parallel by clamp diode; The N number of submodule electric capacity C-of brachium pontis in B phase
bu_Nduring bypass, submodule electric capacity C
-bu-_Nby clamp diode, two brachium pontis reactor L
0with submodule electric capacity C-
bl-_1in parallel; Lower brachium pontis i-th the sub-module capacitance C-of B phase
bl_iduring bypass, wherein the value of i is 1 ~ N-1, submodule electric capacity C
-bl-_iwith submodule electric capacity C-
bl_i+1in parallel by clamp diode; The lower N number of submodule electric capacity C-of brachium pontis of B phase
bl_Nduring bypass, submodule electric capacity C-
bl-_Nwith auxiliary capacitor C-
4in parallel by clamp diode.Above-mentioned auxiliary IGBT module T
1triggering signal consistent with " the logic sum " of brachium pontis first submodule triggering signal in A, C phase; Auxiliary IGBT module T
2the triggering signal of the lower N number of submodule of brachium pontis of triggering signal and B phase consistent.
In the process of orthogonal stream energy conversion, each submodule alternately drops into, bypass, auxiliary IGBT module T
1, T
2be alternately closed, turn off, between A, B phase upper and lower bridge arm, capacitance voltage is under the effect of clamp diode, meets lower column constraint:
Auxiliary capacitor C
1, C
2between voltage, auxiliary capacitor C
3, C
4inequality constraints condition is there is between voltage:
It can thus be appreciated that, at half-bridge/full-bridge series-parallel connection MMC in the dynamic process completing the conversion of orthogonal stream energy, meet constraints below:
The constraints that between C, B phase upper and lower bridge arm, the constraints of capacitance voltage is alternate with A, B is consistent.
Illustrated from above-mentioned, this half-bridge/full-bridge series-parallel connection MMC topology possesses submodule capacitor voltage from the ability of equalization.
Finally should be noted that: described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the application's protection.
Claims (6)
1. the centralized half-bridge of the auxiliary capacitor/full-bridge series-parallel connection MMC based on inequality constraints all presses topology certainly, it is characterized in that: comprise the half-bridge/full-bridge series-parallel connection MMC model be made up of A, B, C three-phase, each brachium pontis of A, B, C three-phase is in series by K half-bridge submodule, a N-K full-bridge submodule and 1 brachium pontis reactor respectively; Comprise by 6N auxiliary switch (6K mechanical switch, 6N-6K IGBT module), 6N+7 clamp diode, 4 auxiliary capacitor C
1, C
2, C
3, C
4, 2 auxiliary IGBT module T
1, T
2what form all presses subsidiary loop certainly.
2. the centralized half-bridge/full-bridge series-parallel connection MMC of the auxiliary capacitor based on inequality constraints according to right 1, from all pressing topology, is characterized in that: the 1st submodule of brachium pontis in A phase, its submodule electric capacity C-
au-_1negative pole is connected with the 2nd sub-module I GBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is upwards connected with DC bus positive pole; I-th submodule of brachium pontis in A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
au-_inegative pole is connected with the i-th+1 sub-module I GBT module mid point of brachium pontis in A phase downwards, its submodule IGBT module mid point upwards with the i-th-1 sub-module capacitance C of brachium pontis in A phase
-au-_i-1negative pole is connected; K half-bridge submodule of brachium pontis in A phase, its submodule electric capacity C
-au-_Knegative pole is connected with K+1 submodule IGBT module mid point of brachium pontis in A phase downwards, and its submodule IGBT module mid point is sub-module capacitance C-individual with the K-1 of brachium pontis in A phase upwards
au-_K-1negative pole is connected; A jth submodule of brachium pontis in A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in A phase downwards, and another IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in A phase; The N number of submodule of brachium pontis in A phase, its submodule IGBT module mid point is downwards through two brachium pontis reactor L
0be connected with the 1st sub-module I GBT module mid point of the lower brachium pontis of A phase, another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis in A phase; I-th submodule of the lower brachium pontis of A phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
al-_inegative pole downwards brachium pontis the i-th+1 sub-module I GBT module mid point lower to A phase is connected, and its IGBT module mid point is the lower sub-module capacitance C-of brachium pontis the i-th-1 with A phase upwards
al-_i-1negative pole is connected; K submodule of the lower brachium pontis of A phase, its submodule electric capacity C
-al_Knegative pole downwards brachium pontis K+1 submodule IGBT module mid point lower to A phase is connected, and its submodule IGBT module mid point is lower brachium pontis K-1 the sub-module capacitance C-with A phase upwards
al-_K-1negative pole is connected; The lower brachium pontis jth submodule of A phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point downwards brachium pontis jth+1 submodule IGBT module mid point lower to A phase is connected, and another IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to A phase is connected; The lower brachium pontis N number of submodule IGBT module mid point of A phase is connected with DC bus negative pole downwards, and another IGBT module mid point is upwards connected with N-1 submodule IGBT module mid point of brachium pontis under A phase; 1st submodule of brachium pontis in B phase, its submodule electric capacity C
-bu-_1positive pole is upwards connected with DC bus positive pole, its submodule IGBT module mid point downwards with the 2nd sub-module capacitance C of brachium pontis in B phase
-bu-_2positive pole is connected; I-th submodule of brachium pontis in B phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C-
bu-_ipositive pole is upwards connected with the i-th-1 sub-module I GBT module mid point of brachium pontis in B phase, its submodule IGBT module mid point downwards with the i-th+1 sub-module capacitance C-of brachium pontis in B phase
bu-_i+1positive pole is connected; K submodule of brachium pontis in B phase, its submodule electric capacity C-
bu-_Kpositive pole is upwards connected with K-1 sub-module I GBT module mid point of brachium pontis in B phase, and its submodule IGBT module mid point is connected with brachium pontis K+1 submodule IGBT module mid point in B phase downwards; A jth submodule of brachium pontis in B phase, wherein the value of j is K+2 ~ N-1, its submodule IGBT module mid point is upwards connected with brachium pontis jth-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is connected with brachium pontis jth+1 submodule IGBT module mid point in B phase downwards; The N number of submodule of brachium pontis in B phase, an one IGBT module mid point is upwards connected with brachium pontis N-1 submodule IGBT module mid point in B phase, and another IGBT module mid point is downwards through two brachium pontis reactor L
0with the 1st sub-module capacitance C of the lower brachium pontis of B phase
-bl-_1positive pole is connected; I-th submodule of the lower brachium pontis of B phase, wherein the value of i is 2 ~ K-1, its submodule electric capacity C
-bl_ipositive pole upwards descends the i-th-1 sub-module I GBT module mid point of brachium pontis to be connected with B phase, and its submodule IGBT module mid point descends the i-th+1 sub-module capacitance C-of brachium pontis with B phase downwards
bl-_i+1positive pole is connected; K submodule of the lower brachium pontis of B phase, its submodule electric capacity C
-bl_Kpositive pole upwards brachium pontis K-1 sub-module I GBT module mid point lower to B phase is connected, and its submodule IGBT module mid point downwards brachium pontis K+1 submodule IGBT module mid point lower to B phase is connected; The lower brachium pontis jth submodule of B phase, wherein the value of j is K+2 ~ N-1, an one IGBT module mid point upwards brachium pontis jth-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point downwards brachium pontis jth+1 sub-module I GBT IGBT module mid point lower to B phase is connected; The lower N number of submodule of brachium pontis of B phase, its submodule IGBT module mid point upwards brachium pontis N-1 submodule IGBT module mid point lower to B phase is connected, and another IGBT module mid point is connected with DC bus negative pole downwards; The connected mode of C phase upper and lower bridge arm submodule can be consistent with A, also can be consistent with B; Due to the existence of full-bridge submodule, unnecessary configuration thyristor between the upper and lower output line of half-bridge submodule; Therefore A, B, C phase upper and lower bridge arm submodule be parallel with mechanical switch K between output line up and down
au_i1, K
al_i1, K
bu_i1, K
bl_i1, K
cu_i1, K
cl_i1, K
au_j, K
al_j, K
bu_j, K
bl_j, K
cu_j, K
cl_j, wherein the value of i is the value of 1 ~ K, j is K+1 ~ N; A, B, C three-phase status that above-mentioned annexation is formed is consistent, and other topologys after three-phase symmetrized in turn are in interest field.
3. the centralized half-bridge/full-bridge series-parallel connection MMC of the auxiliary capacitor based on inequality constraints according to right 1, from all pressing topology, is characterized in that: from all pressing in subsidiary loop, auxiliary capacitor C
1with auxiliary capacitor C
2in parallel by clamp diode, auxiliary capacitor C
2positive pole connects auxiliary IGBT module T
1, auxiliary capacitor C
1negative pole connects clamp diode and is incorporated to DC bus positive pole; Auxiliary capacitor C
3with auxiliary capacitor C
4in parallel by clamp diode, auxiliary capacitor C
3negative pole connects auxiliary IGBT module T
2, auxiliary capacitor C
4positive pole connects clamp diode and is incorporated to DC bus negative pole; Clamp diode, by auxiliary switch K
au_121st sub-module capacitance C in brachium pontis in connection A phase
-au-_1with auxiliary capacitor C
1positive pole; By auxiliary switch K
au_i2, K
au_(i+1) 2i-th sub-module capacitance C in brachium pontis in connection A phase
-au-_iwith the i-th+1 sub-module capacitance C
-au-_i+1positive pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
au_K2, T
au_K+1k sub-module capacitance C in brachium pontis in connection A phase
-au-_Kwith K+1 sub-module capacitance C-
au_K+1positive pole; By auxiliary switch T
au_j, T
au_j+1a jth sub-module capacitance C in brachium pontis in connection A phase
-au-_jmodule capacitance C with jth+1
-au-_j+1positive pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
au_N, K
al_12n number of submodule electric capacity C-in brachium pontis in connection A phase
au_Nbrachium pontis 1st sub-module capacitance C lower to A phase
-al-_1positive pole; By auxiliary switch K
al_i2, K
al_(i+1) 2connect i-th sub-module capacitance C in the lower brachium pontis of A phase
-al-_iwith the i-th+1 sub-module capacitance C
-al-_i+1positive pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
al_K2, T
al_K+1connect K sub-module capacitance C-in the lower brachium pontis of A phase
al-_Kwith K+1 sub-module capacitance C-
al-_K+1positive pole; By auxiliary switch T
al_j, T
al_j+1connect a jth sub-module capacitance C in the lower brachium pontis of A phase
-al_jmodule capacitance C with jth+1
-al-_j+1positive pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
al_Nconnect N number of submodule electric capacity C in the lower brachium pontis of A phase
-al_Nwith auxiliary capacitor C
3positive pole; Clamp diode, by auxiliary switch K
bu_121st sub-module capacitance C in brachium pontis in connection B phase
-bu-_1with auxiliary capacitor C
2negative pole; By auxiliary switch K
bu_i2, K
bu_(i+1) 2i-th sub-module capacitance C-in brachium pontis in connection B phase
bu-_iwith the i-th+1 sub-module capacitance C-
bu-_i+1negative pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
bu_K2, T
bu_K+1k sub-module capacitance C-in brachium pontis in connection B phase
bu-_Kwith K+1 sub-module capacitance C-
bu-_K+1negative pole; By auxiliary switch T
bu_j, T
bu_j+1a jth sub-module capacitance C-in brachium pontis in connection B phase
bu-_jmodule capacitance C-with jth+1
bu-_j+1negative pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
bu_N, K
bl_12n number of submodule electric capacity C-in brachium pontis in connection B phase
bu-_Nwith the 1st sub-module capacitance C-in the lower brachium pontis of B phase
bl_1negative pole; By auxiliary switch K
bl_i2, K
bl_(i+1) 2connect i-th sub-module capacitance C-in the lower brachium pontis of B phase
bl-_iwith the i-th+1 sub-module capacitance C-
bl-_i+1negative pole, wherein the value of i is 1 ~ K-1; By auxiliary switch K
bl_K2, T
bl_K+1connect K sub-module capacitance C-in the lower brachium pontis of B phase
bl_Kwith K+1 sub-module capacitance C-
bl-_K+1negative pole; By auxiliary switch T
bl_j, T
bl_j+1connect a jth sub-module capacitance C-in the lower brachium pontis of B phase
bl-_jmodule capacitance C-with jth+1
bl_j+1negative pole, wherein the value of j is K+1 ~ N-1; By auxiliary switch T
bl_Nconnect N number of submodule electric capacity C in the lower brachium pontis of B phase
-bl-_Nwith auxiliary capacitor C
4negative pole; The annexation of C phase clamp diode is corresponding with the annexation of its submodule; 6N auxiliary switch K in above-mentioned A, B, C three-phase
au_i2, K
al_i2, K
bu_i2, K
bl_i2, K
cu_i2, K
cl_i2, T
au_j, T
al_j, T
bu_j, T
bl_j, T
cu_j, T
cl_j, wherein the value of i is the value of 1 ~ K, j is K+1 ~ N, 6N+7 clamp diode, 4 auxiliary capacitor C
1, C
2, C
3, C
4and 2 auxiliary IGBT module T
1, T
2, common formation is from all pressing subsidiary loop.
4. the centralized half-bridge/full-bridge series-parallel connection MMC of the auxiliary capacitor based on inequality constraints according to right 1, from all pressing topology, is characterized in that: during normal condition, from all pressing 6N auxiliary switch K in subsidiary loop
au_i2, K
al_i2, K
bu_i2, K
bl_i2, K
cu_i2, K
cl_i2, T
au_j, T
al_j, T
bu_j, T
bl_j, T
cu_j, T
cl_jnormally closed, wherein the value of i is the value of 1 ~ K, j is K+1 ~ N; During failure condition, 6N-6K auxiliary switch T
au_j, T
al_j, T
bu_j, T
bl_j, T
cu_j, T
cl_jdisconnect, wherein the value of j is K+1 ~ N; Under normal circumstances, brachium pontis first sub-module capacitance C-in A phase
au-_1during bypass, now auxiliary IGBT module T
1disconnect, submodule electric capacity C
-au-_1with auxiliary capacitor C
1in parallel by clamp diode; Brachium pontis i-th sub-module capacitance C-in A phase
au-_iduring bypass, wherein the value of i is 2 ~ N, submodule electric capacity C-
au-_iwith submodule electric capacity C-
au-_i-1in parallel by clamp diode; Lower brachium pontis first the sub-module capacitance C-of A phase
al_1during bypass, submodule electric capacity C-
al-_1by clamp diode, two brachium pontis reactor L
0with submodule electric capacity C-
au-_Nin parallel; Lower brachium pontis i-th the sub-module capacitance C-of A phase
al_iduring bypass, wherein the value of i is 2 ~ N, submodule electric capacity C-
al-_iwith submodule electric capacity C-
al_i-1in parallel by clamp diode; Auxiliary IGBT module T
2time closed, auxiliary capacitor C
3by clamp diode and submodule electric capacity C-
al_Nin parallel; Auxiliary IGBT module T
1time closed, auxiliary capacitor C
2with submodule electric capacity C-
bu-_1in parallel by clamp diode; Brachium pontis i-th sub-module capacitance C-in B phase
bu-_iduring bypass, wherein the value of i is 1 ~ N-1, submodule electric capacity C-
bu-_iwith submodule electric capacity C-
bu-_i+1in parallel by clamp diode; The N number of submodule electric capacity C-of brachium pontis in B phase
bu_Nduring bypass, submodule electric capacity C
-bu-_Nby clamp diode, two brachium pontis reactor L
0with submodule electric capacity C-
bl-_1in parallel; Lower brachium pontis i-th the sub-module capacitance C-of B phase
bl_iduring bypass, wherein the value of i is 1 ~ N-1, submodule electric capacity C
-bl-_iwith submodule electric capacity C-
bl_i+1in parallel by clamp diode; The lower N number of submodule electric capacity C-of brachium pontis of B phase
bl_Nduring bypass, submodule electric capacity C-
bl-_Nwith auxiliary capacitor C-
4in parallel by clamp diode; Wherein auxiliary IGBT module T
1triggering signal consistent with " the logic sum " of brachium pontis first submodule triggering signal in A, C phase; Auxiliary IGBT module T
2the triggering signal of the lower N number of submodule of brachium pontis of triggering signal and B phase consistent; In the process of orthogonal stream energy conversion, each submodule alternately drops into, bypass, auxiliary IGBT module T
1, T
2be alternately closed, turn off, A phase upper and lower bridge arm submodule capacitor voltage, under the effect of clamp diode, meets lower column constraint, U
c1>=U
c-au_1>=U
c-au_2>=U
c-au_N>=U
c-al_1>=U
c-al_2>=U
c-al_N>=U
c3; B phase upper and lower bridge arm submodule capacitor voltage, under the effect of clamp diode, meets lower column constraint, U
c2≤ U
c-bu_1≤ U
c-bu_2≤ U
c-bu_N≤ U
c-bl_1≤ U
c-bl_2≤ U
c-bl_N≤ U
c4; Against auxiliary capacitor C
1, C
2between voltage, auxiliary capacitor C
3, C
4two inequality constraintss between voltage, U
c1≤ U
c2, U
c3>=U
c4, 4N sub-module capacitance in A, B phase upper and lower bridge arm, C
au_i, C
al_i, C
bu_i, C
bl_i, wherein i value is 1 ~ N, and auxiliary capacitor C
1, C
2, C
3, C
4, voltage be in self-balancing state, topological A, B are alternate possesses submodule capacitor voltage from the ability of equalization; If the form of the composition of C phase is consistent with A in topology, then the constraints of C, B capacitive coupling voltage is consistent with capacitance voltage constraints between A, B; If the form of the composition of C phase is consistent with B in topology, then the constraints of A, C capacitive coupling voltage is consistent with capacitance voltage constraints between A, B, and topology possesses submodule capacitor voltage from the ability of equalization; Realize on the basis of the single-phase flowing of capacitive energy between adjacent submodule mutually utilizing clamp diode; rely on the inequality constraints between auxiliary capacitor; the alternate flowing realizing capacitive energy forms the peripheral passage of capacitive energy; and then keep alternate submodule capacitor voltage to stablize, be the protection content of this right.
5. the centralized half-bridge/full-bridge series-parallel connection MMC of the auxiliary capacitor based on inequality constraints according to right 1, from all pressing topology, is characterized in that: auxiliary capacitor C
1, C
2, C
3, C
4both as the passage of A, B capacitive coupling energy exchange, again as the passage of B, C capacitive coupling energy exchange; Function focus utilization in topology of auxiliary capacitor all presses the device consumption in subsidiary loop certainly with minimizing; Auxiliary capacitor C
1, C
2function concentrate, auxiliary capacitor C
3, C
4function do not concentrate; Auxiliary capacitor C
1, C
2function do not concentrate, auxiliary capacitor C
3, C
4function concentrate topology in interest field.
6. the centralized half-bridge/full-bridge series-parallel connection MMC of the auxiliary capacitor based on inequality constraints according to right 1 is from all pressing topology, it is characterized in that: the centralized half-bridge of the auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC is from all pressing topology, flexible direct-current transmission field can not only be directly applied to as multi-level voltage source current converter, also by forming STATCOM (STATCOM), Research on Unified Power Quality Conditioner (UPQC), the application of installations such as THE UPFC (UPFC) are in flexible AC transmission field; Other application scenarios of this invention topology of indirect utilization and thought are in interest field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610047419.1A CN105450049A (en) | 2016-01-25 | 2016-01-25 | Auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610047419.1A CN105450049A (en) | 2016-01-25 | 2016-01-25 | Auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105450049A true CN105450049A (en) | 2016-03-30 |
Family
ID=55559929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610047419.1A Pending CN105450049A (en) | 2016-01-25 | 2016-01-25 | Auxiliary capacitance concentrated type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105450049A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253675A (en) * | 2005-08-30 | 2008-08-27 | 西门子公司 | Converter circuit comprising distributed energy stores |
| CN102223080A (en) * | 2011-06-10 | 2011-10-19 | 浙江大学 | Mixed clamping back-to-back multi-level AC-DC-AC switching circuit |
| CN102832841A (en) * | 2012-08-27 | 2012-12-19 | 清华大学 | Modularized multi-level converter with auxiliary diode |
| CN203608108U (en) * | 2013-12-17 | 2014-05-21 | 山东大学 | Capacitance voltage self-balancing circuit of modular multilevel converter |
| CN205960964U (en) * | 2016-01-25 | 2017-02-15 | 华北电力大学 | Supplementary centralized half -bridge of electric capacity / full -bridge series -parallel connection MMC is from voltage -sharing topology based on inequality constraint |
-
2016
- 2016-01-25 CN CN201610047419.1A patent/CN105450049A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253675A (en) * | 2005-08-30 | 2008-08-27 | 西门子公司 | Converter circuit comprising distributed energy stores |
| CN102223080A (en) * | 2011-06-10 | 2011-10-19 | 浙江大学 | Mixed clamping back-to-back multi-level AC-DC-AC switching circuit |
| CN102832841A (en) * | 2012-08-27 | 2012-12-19 | 清华大学 | Modularized multi-level converter with auxiliary diode |
| CN203608108U (en) * | 2013-12-17 | 2014-05-21 | 山东大学 | Capacitance voltage self-balancing circuit of modular multilevel converter |
| CN205960964U (en) * | 2016-01-25 | 2017-02-15 | 华北电力大学 | Supplementary centralized half -bridge of electric capacity / full -bridge series -parallel connection MMC is from voltage -sharing topology based on inequality constraint |
Non-Patent Citations (2)
| Title |
|---|
| CONGZHE GAO 等: "A DC-Link Voltage Self-Balance Method for a Diode-Clamped Modular Multilevel Converter With Minimum Number of Voltage Sensors", 《IEEE TRANSACTIONS ON POWER ELECTRONICS》 * |
| XIN ZHAO 等: "Research on submodule capacitance voltage balancing of MMC based on carrier phase shifted SPWM technique", 《CHINA INTERNATIONAL CONFERENCE ON ELECTRICITY DISTRIBUTION》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205960964U (en) | Supplementary centralized half -bridge of electric capacity / full -bridge series -parallel connection MMC is from voltage -sharing topology based on inequality constraint | |
| CN205754047U (en) | The half-bridge MMC of formula without auxiliary capacitor based on inequality constraints is from all pressing topology | |
| CN205754041U (en) | The centralized single clamp MMC of auxiliary capacitor based on equality constraint is from all pressing topology | |
| CN105450070A (en) | Non-auxiliary-capacitance type half-bridge/full-bridge parallel-serial MMC self-voltage-sharing topology based on inequality constraints | |
| CN105471259A (en) | Auxiliary capacitor centralized half-bridge/single-clamping series-parallel MMC automatic voltage-equalizing topology based on equality constraint | |
| CN205657607U (en) | Supplementary electric capacity distributing type half -bridge / single clamp series -parallel connection MMC is from voltage -sharing topology based on inequality constraint | |
| CN105471302A (en) | Auxiliary capacitor centralized half-bridge MMC automatic voltage-equalizing topology based on equality constraint | |
| CN105515427A (en) | Auxiliary-capacitor-free full-bridge MMC self-voltage-sharing topology based on inequality constraints | |
| CN105515428A (en) | Auxiliary-capacitor-free half-bridge MMC self-voltage-sharing topology based on inequality constraints | |
| CN105429491A (en) | Inequality constraints-based auxiliary capacitor concentrated single clamping MMC self voltage-sharing topology | |
| CN205754044U (en) | The centralized half-bridge of auxiliary capacitor based on equality constraint/full-bridge series-parallel connection MMC is from all pressing topology | |
| CN205754042U (en) | The centralized half-bridge MMC of auxiliary capacitor based on inequality constraints is from all pressing topology | |
| CN205754045U (en) | The centralized half-bridge MMC of auxiliary capacitor based on equality constraint is from all pressing topology | |
| CN205754046U (en) | The distributed half-bridge of auxiliary capacitor based on equality constraint/full-bridge series-parallel connection MMC is from all pressing topology | |
| CN105450048A (en) | Auxiliary capacitance distributed type half-bridge/single-clamping parallel-serial MMC self-voltage-sharing topology based on equality constraints | |
| CN205657605U (en) | Single clamp MMC is from voltage -sharing topology for supplementary electric capacity distributing type based on equality constraint | |
| CN105515425A (en) | Auxiliary capacitor distributed half-bridge and full-bridge series-parallel MMC self-voltage-sharing topology based on inequality constraints | |
| CN205754043U (en) | The distributed half-bridge MMC of auxiliary capacitor based on inequality constraints is from all pressing topology | |
| CN105450069A (en) | Auxiliary capacitance concentrated type full-bridge MMC self-voltage-sharing topology based on equality constraints | |
| CN105471305A (en) | Auxiliary capacitor centralized half-bridge MMC automatic voltage-equalizing topology based on inequality constraint | |
| CN105471307A (en) | Auxiliary capacitor distributed type half-bridge/single-clamping series-parallel MMC automatic voltage-equalizing topology based on inequality constraint | |
| CN205754029U (en) | The centralized single clamp MMC of auxiliary capacitor based on inequality constraints is from all pressing topology | |
| CN205754049U (en) | The distributed half-bridge of auxiliary capacitor based on inequality constraints/full-bridge series-parallel connection MMC is from all pressing topology | |
| CN205657606U (en) | Single clamp MMC is from voltage -sharing topology for supplementary electric capacity distributing type based on inequality constraint | |
| CN105515426A (en) | Auxiliary capacitor concentrated type single-clamping MMC self-voltage-balancing topology based on equality constraints |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160330 |