CN105448859A - 一种芯片上加有玻璃盖板的封装件及其制造方法 - Google Patents

一种芯片上加有玻璃盖板的封装件及其制造方法 Download PDF

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CN105448859A
CN105448859A CN201510923439.6A CN201510923439A CN105448859A CN 105448859 A CN105448859 A CN 105448859A CN 201510923439 A CN201510923439 A CN 201510923439A CN 105448859 A CN105448859 A CN 105448859A
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chip
glass cover
plate
substrate
glue
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王小龙
刘宇环
张锐
谢建友
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种芯片上加有玻璃盖板的封装件及其制造方法，封装件包括有芯片和玻璃盖板，玻璃盖板为凹型，芯片上直接加镀有增透膜的凹型玻璃盖板，不用塑封，简化封装工序，芯片感应区域外露，感应区域玻璃保护盖板直接在封装过程中添加，大大减少再加工造成的风险，有效降低封装难点，提高封装良率。

Description

一种芯片上加有玻璃盖板的封装件及其制造方法
技术领域
本发明属于集成电路领域，具体是一种芯片上加有玻璃盖板的封装件及其制造方法。
背景技术
现有封装件封装时，需要塑封来对芯片保护，造成工艺复杂化，产品良率低下。
发明内容
针对上述现有技术存在的问题，本发明提供了一种芯片上加有玻璃盖板的封装件及其制造方法，该方法有效降低了封装难点，提高了封装良率。
一种芯片上加有玻璃盖板的封装件，主要由玻璃盖板、增透膜、粘合胶、基板、粘片胶、芯片、金手指、键合线、填充胶组成；所述玻璃盖板为凹型，凹型底部有增透膜，所述基板上通过粘片胶固定有芯片，所述键合线将芯片与基板上的金手指互连，所述粘合胶将玻璃盖板贴装在基板对应的粘合区域，所述芯片位于玻璃盖板的凹型区域，所述填充胶填充玻璃盖板与基板、芯片间的空隙部分，包裹键合线和芯片。
一种芯片上加有玻璃盖板的封装件的制造方法，具体按照以下步骤进行：
步骤一：准备玻璃盖板，玻璃盖板为凹型，凹型底部镀有增透膜；
步骤二：在基板表面贴装芯片，芯片为指纹识别芯片，芯片通过粘片胶固定在基板之上；
步骤三：引线键合工艺，通过键合线使芯片与基板上的金手指形成电性连接；
步骤四：通过粘合胶将玻璃盖板贴装在基板对应的粘合区域；
步骤五：用填充胶填充玻璃盖板与基板、芯片间的空隙部分，包裹键合线和芯片，填充胶为Underfill填充胶。
本发明通过在指纹传感芯片上面直接加镀有增透膜的凹型玻璃盖板，可以不用进行塑封，简化封装工序，指纹识别芯片感应区域外露，感应区域玻璃保护盖板直接在封装过程中添加，大大减少再加工造成的风险，有效降低封装难点，提高封装良率。
附图说明
图1玻璃盖板示意图；
图2基板贴装指纹传感芯片&压焊示意图；
图3芯片直接加玻璃盖板的结构示意图。
其中：1为玻璃盖板；2为增透膜；3为粘合胶；4为基板；5为粘片胶；6为芯片；7为金手指；8为键合线；9为填充胶。
具体实施方式
如图3所示，一种芯片上加有玻璃盖板的封装件，主要由玻璃盖板1、增透膜2、粘合胶3、基板4、粘片胶5、芯片6、金手指7、键合线8、填充胶9组成；所述玻璃盖板1为凹型，凹型底部有增透膜2，所述基板4上通过粘片胶5固定有芯片6，所述键合线8将芯片6与基板4上的金手指7互连，所述粘合胶3将玻璃盖板1贴装在基板4对应的粘合区域，所述芯片6位于玻璃盖板1的凹型区域，所述填充胶9填充玻璃盖板1与基板4、芯片6间的空隙部分，包裹键合线8和芯片6。
一种芯片上加有玻璃盖板的封装件的制造方法，具体按照以下步骤进行：
步骤一：准备玻璃盖板1，玻璃盖板1为凹型，凹型底部镀有增透膜2，如图1所示；
步骤二：在基板4表面贴装芯片6，芯片6为指纹识别芯片，芯片6通过粘片胶5固定在基板4之上，如图2所示；
步骤三：引线键合工艺，通过键合线8使芯片6与基板4上的金手指7形成电性连接；
步骤四：通过粘合胶3将玻璃盖板1贴装在基板4对应的粘合区域，如图3所示；
步骤五：用填充胶9填充玻璃盖板1与基板4、芯片6间的空隙部分，包裹键合线8和芯片6，填充胶9为Underfill填充胶，如图3所示。

Claims (4)

1.一种芯片上加有玻璃盖板的封装件，其特征在于：所述封装件主要由玻璃盖板(1)、增透膜(2)、粘合胶(3)、基板(4)、粘片胶(5)、芯片(6)、金手指(7)、键合线(8)、填充胶(9)组成；所述玻璃盖板(1)为凹型，凹型底部有增透膜(2)，所述基板(4)上通过粘片胶(5)固定有芯片(6)，所述键合线(8)将芯片(6)与基板(4)上的金手指(7)互连，所述粘合胶(3)将玻璃盖板(1)贴装在基板(4)对应的粘合区域，所述芯片(6)位于玻璃盖板(1)的凹型区域，所述填充胶(9)填充玻璃盖板(1)与基板(4)、芯片(6)间的空隙部分，包裹键合线(8)和芯片(6)。
2.根据权利要求1所述的一种芯片上加有玻璃盖板的封装件，其特征在于：所述芯片(6)为指纹识别芯片。
3.根据权利要求1所述的一种芯片上加有玻璃盖板的封装件，其特征在于：所述填充胶(9)为Underfill填充胶。
4.一种芯片上加有玻璃盖板的封装件的制造方法，其特征在于：具体按照以下步骤进行：
步骤一：准备玻璃盖板(1)，玻璃盖板(1)为凹型，凹型底部镀有增透膜(2)；
步骤二：在基板(4)表面贴装芯片(6)，芯片(6)为指纹识别芯片，芯片(6)通过粘片胶(5)固定在基板(4)之上；
步骤三：引线键合工艺，通过键合线(8)使芯片(6)与基板(4)上的金手指(7)形成电性连接；
步骤四：通过粘合胶(3)将玻璃盖板(1)贴装在基板(4)对应的粘合区域；
步骤五：用填充胶(9)填充玻璃盖板(1)与基板(4)、芯片(6)间的空隙部分，包裹键合线(8)和芯片(6)，填充胶(9)为Underfill填充胶。
CN201510923439.6A 2015-12-11 2015-12-11 一种芯片上加有玻璃盖板的封装件及其制造方法 Pending CN105448859A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113101A1 (zh) * 2016-12-23 2018-06-28 创智能科技股份有限公司 生物辨识装置

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CN104182738A (zh) * 2014-08-26 2014-12-03 南昌欧菲生物识别技术有限公司 指纹识别模组及其制造方法
CN205303444U (zh) * 2015-12-11 2016-06-08 华天科技（西安）有限公司 一种芯片上加有玻璃盖板的封装件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120126386A1 (en) * 2003-09-16 2012-05-24 Micron Technology, Inc. Electronic devices
CN1921125A (zh) * 2005-08-25 2007-02-28 矽格股份有限公司 光感测组件封装结构及其制造方法
CN104078479A (zh) * 2014-07-21 2014-10-01 格科微电子（上海）有限公司 图像传感器的晶圆级封装方法和图像传感器封装结构
CN104182738A (zh) * 2014-08-26 2014-12-03 南昌欧菲生物识别技术有限公司 指纹识别模组及其制造方法
CN205303444U (zh) * 2015-12-11 2016-06-08 华天科技（西安）有限公司 一种芯片上加有玻璃盖板的封装件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113101A1 (zh) * 2016-12-23 2018-06-28 创智能科技股份有限公司 生物辨识装置

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Application publication date: 20160330