CN105428422B - 薄膜晶体管、阵列基板、显示面板及显示装置 - Google Patents

薄膜晶体管、阵列基板、显示面板及显示装置 Download PDF

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CN105428422B
CN105428422B CN201610005838.9A CN201610005838A CN105428422B CN 105428422 B CN105428422 B CN 105428422B CN 201610005838 A CN201610005838 A CN 201610005838A CN 105428422 B CN105428422 B CN 105428422B
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extension
drain electrode
tft
thin film
film transistor
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CN105428422A (zh
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吕振华
包智颖
王世君
张勇
肖文俊
许静波
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种薄膜晶体管、阵列基板、显示面板及显示装置,用以保证通电后形成的沟道的宽和长的比值不变,提高显示装置的显示效果。其中薄膜晶体管包括:栅极层,位于栅极层上的源极和漏极,以及位于源极和漏极上的有源层,有源层与源极和漏极电连接,有源层包括:两个平行设置的侧边,且每个侧边与源极朝向漏极的一面所成的锐角为45度。本发明提供的薄膜晶体管,通过将有源层的形状改变:有源层包括:两个平行设置的侧边,且每个侧边与源极朝向漏极的一面所成的锐角为45度,可以使得有源层与源极和/或漏极存在对位偏差时,薄膜晶体管通电后,有源层与源极和漏极之间形成的沟道的宽和长的比不变,可以提高显示装置的显示效果。

Description

薄膜晶体管、阵列基板、显示面板及显示装置
技术领域
本发明涉及显示器技术领域,特别涉及一种薄膜晶体管、阵列基板、显示面板及显示装置。
背景技术
在制作薄膜晶体管时,需要保证多层膜材之间的对位精度。如图1所示,图1为现有技术中的薄膜晶体管的结构示意图,现有技术中的薄膜晶体管主要包括:栅极层01,位于栅极层01上的源极02和漏极03以及位于源极02和漏极03上的有源层04,在制备时需要保证栅极层01、源极02、漏极03和有源层04之间的对位精度,以保通电时形成的沟道的宽W与长的比值不变。
但现有技术中薄膜晶体管在制备时,很难保证栅极层,源、漏极和有源层之间的对位精度,当源、漏极和有源层之间产生对位偏差时,沟道的宽与长的比值将发生变化,会影响显示装置的显示画面效果。
发明内容
本发明提供了一种薄膜晶体管、阵列基板、显示面板及显示装置,用以保证通电后形成的沟道的宽和长的比值不变,提高显示装置的显示效果。
为达到上述目的,本发明提供以下技术方案:
本发明提供了一种薄膜晶体管,包括:栅极层,位于所述栅极层上的源极和漏极,以及位于所述源极和漏极上的有源层,所述有源层与所述源极和漏极电连接,所述有源层包括:两个平行设置的侧边,且每个所述侧边与所述源极朝向所述漏极的一面所成的锐角为45度。
本发明提供的薄膜晶体管,通过将有源层的形状改变:有源层包括:两个平行设置的侧边,且每个所述侧边与所述源极朝向所述漏极的一面所成的锐角为45度,可以使得有源层与源极和/或漏极存在对位偏差时,薄膜晶体管通电后,有源层与源极和漏极之间形成的沟道的宽和长的比不变,可以提高显示装置的显示效果。
在一些可选的实施方式中,所述源极包括:主体部、从所述主体部向所述漏极延伸的第一延伸部、从所述第一延伸部向背离所述漏极方向延伸的第二延伸部,从所述主体部向远离所述漏极方向延伸的第三延伸部,所述第一延伸部与所述第二延伸部和第三延伸部的延伸方向垂直。第一延伸部、第二延伸部和第三延伸部的设置,可以使得有源层与源极和/或漏极存在对位偏差时,栅极和源极交叠处的电容不变,减少显示装置的显示画面出现闪烁。
在一些可选的实施方式中,所述漏极包括:与所述第二延伸部平行设置的第一本体、从所述第一本体向所述源极方向延伸的第二本体,所述第二本体与所述第一本体相互垂直,所述第一延伸部和所述第二延伸部相对所述第一延伸部和所述第二延伸部连接处的夹角的角平分线对称,所述第一本体和所述第二本体相对所述角平分线对称。
在一些可选的实施方式中,所述有源层还包括:连接所述两个平行设置的侧边的第一连接边和第二连接边,所述第二连接边与所述两个平行设置的侧边的连接处形成避让倒角。第二连接边与两个平行设置的侧边的连接处的避让倒角的设置可以避免有源层和源极、漏极存在对位偏差时,有源层延伸出漏极的现象的发生。
在一些可选的实施方式中,所述第一连接边与所述两个平行设置的侧边的连接处形成避让倒角。当有源层和源极和漏极存在对位偏差时,可以避免有源层延伸出源极的现象的发生。
在一些可选的实施方式中,所述第一连接边与所述第一延伸部和所述第二延伸部的连接处相对应的部分设有向所述第二连接边凸起的避让口。
在一些可选的实施方式中,所述源极和所述漏极同层设置。
本发明还提供了一种阵列基板,包括上述任一项所述的薄膜晶体管。由于上述薄膜晶体管可以保证通电后形成的沟道的宽和长的比值不变,提高显示装置的显示效果,故本发明提供的阵列基板可以提高显示装置的显示效果。
本发明还提供一种显示面板,包括上述阵列基板。由于上述阵列基板可以提高显示装置的显示效果,故本发明提高的显示面板具有较好的显示效果。
本发明还提供了一种显示装置,包括上述显示面板。具有较好的显示效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解,构成本发明的一部分,本发明的示意性实施例及其说明用于解释本发明,并不构成对本发明的不当限定。在附图中:
图1为现有技术中的薄膜晶体管的结构示意图;
图2为本发明实施例提供的薄膜晶体管的结构示意图;
图3a~图3d为本发明实施例提供的薄膜晶体管中的有源层相对源极和漏极存在偏移的结构示意图;
图4a~图4d为本发明实施例提供的薄膜晶体管中的源极和漏极相对栅极存在偏移的结构示意图。
图中:
01-栅极层 02-源极
03-漏极 04-有源层
1-栅极层 2-源极
21-第一延伸部 22-第二延伸部
23-第三延伸部 24-主体部
3-漏极 31-第一本体
32-第二本体 4-有源层
41-避让倒角 42-避让口
5-角平分线
a、a1、b、b1、s、e、h、f代表长度,c代表角度
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。
如图1所示,图1为现有技术中的薄膜晶体管的结构示意图;本发明提供了一种薄膜晶体管,包括:栅极层1,位于栅极层1上的源极2和漏极3,以及位于源极2和漏极3上的有源层4,有源层4与源极2和漏极3电连接,有源层4包括:两个平行设置的侧边,且每个侧边与源极2朝向漏极3的一面所成的锐角为45度。
本发明提供的薄膜晶体管,通过将有源层4的形状改变:有源层4包括:两个平行设置的侧边,且每个侧边与源极2朝向漏极3的一面所成的锐角为45度,可以使得有源层4与源极2和/或漏极3存在对位偏差时,薄膜晶体管通电后,有源层4与源极2和漏极3之间形成的沟道的宽和长的比不变,可以提高显示装置的显示效果。
如图3a~图3d所示,图3a~图3d为本发明实施例提供的薄膜晶体管中的有源层4相对源极2和漏极3存在偏移的结构示意图;当有源层4相对源极2和漏极3有偏移时,以图3a为例,对本发明提供的方案进行具体解释说明,这里定义薄膜晶体管通电后形成的沟道的长度为源极2和漏极3正对距离,其中黑色实线代表有源层4的正确对位位置,点划线代表偏移的有源层4,从图3a可以看出,有源层4相对正确位置向右偏移距离为S,当有源层4未偏移时,沟道的宽度为a+b,当有源层4偏移时,a将减少a1,b增大b1,沟道的宽度变为a-a1+b+b1,图中:h/s=sinc=sin45,则h=s×sinc=s×sin45 (1);
a1=h/sinc=h/sin45 (2);
从式(1)和式(2)可以得到a1=s;
e/s=cosc=cos45,则e=s×cosc=s×cos45 (3);
b1=e/sinc=e/sin45 (4);
从式(3)和式(4)可以得到可知a1=b1;也就是说有源层4偏移和未偏移前,沟道的宽度不变,由于其长度也不变,故沟道的宽和长的比值不变。
图3b表示的是有源层相对正确对位位置向左偏移,图3c表示的是有源层相对正确对位位置向下偏移,图3d表示的是有源层相对正确对位位置向上偏移,图3b~图3c中沟道的宽和长的比值不变的具体推到过程如图3a,这里就不再一一赘述。
如图4a~图4d所示,图4a~图4d为本发明实施例提供的薄膜晶体管中的源极和漏极相对栅极存在偏移的结构示意图。当源极2和漏极3相对栅极层1有偏移时,以图4a为例,对本发明提供的方案进行具体解释说明,这里定义薄膜晶体管通电后形成的沟道的长度为源极2和漏极3正对距离,其中黑色实线代表源极2和漏极3的正确对位位置,点划线代表偏移的源极2和漏极3,从图4a可以看出,源极2和漏极3相对正确位置向左偏移距离为f,当源极2和漏极3未偏移时,沟道的宽度为a+b,当源极2和漏极3偏移时,a将减少a1,b增大b1,沟道的宽度变为a-a1+b+b1,图中:a1=f(5);
b1=f×tan45=f (6);
从式(5)和式(6)可知a1=b1;也就是说源极2和漏极3偏移和未偏移前,沟道的宽度不变,由于其长度也不变,故沟道的宽和长的比值不变。
图4b表示的是源极和漏极相对正确对位位置向右偏移,图4c表示的是源极和漏极相对正确对位位置向上偏移,图3d表示的是源极和漏极相对正确对位位置向下偏移,图4b~图4c中沟道的宽和长的比值不变的具体推到过程如图4a,这里就不再一一赘述。
如图2所示,进一步的,源极2包括:主体部24、从主体部24向漏极3延伸的第一延伸部21、从第一延伸部21向背离漏极3方向延伸的第二延伸部22,从主体部24向远离漏极3方向延伸的第三延伸部23,第一延伸部21与第二延伸部22和第三延伸部23的延伸方向垂直。第一延伸部21、第二延伸部22和第三延伸部23的设置,可以使得有源层4与源极2和/或漏极3存在对位偏差时,栅极和源极2交叠处的电容不变,减少显示装置的显示画面出现闪烁。
进一步的,漏极3包括:与第二延伸部22平行设置的第一本体31、从第一本体31向源极2方向延伸的第二本体32,第二本体32与第一本体31相互垂直,第一延伸部21和第二延伸部22相对第一延伸部21和第二延伸部22连接处的夹角的角平分线5对称,第一本体31和第二本体32相对角平分线5对称。
一种具体实施方式中,有源层4还包括:连接两个平行设置的侧边的第一连接边和第二连接边,第二连接边与两个平行设置的侧边的连接处形成避让倒角41。第二连接边与两个平行设置的侧边的连接处的避让倒角41的设置可以避免有源层4和源极2和漏极3存在对位偏差时,有源层4延伸出漏极3的现象的发生。
进一步的,第一连接边与两个平行设置的侧边的连接处形成避让倒角41。当有源层4和源极2和漏极3存在对位偏差时,可以避免有源层4延伸出源极2的现象的发生。
更进一步的,第一连接边与第一延伸部21和第二延伸部22的连接处相对应的部分设有向第二连接边凸起的避让口42。
可选的,上述源极2和漏极3同层设置。当然源极2和漏极3也可以不同层设置。
本发明还提供了一种阵列基板,包括上述任一项所述的薄膜晶体管。由于上述薄膜晶体管可以保证通电后形成的沟道的宽和长的比值不变,提高显示装置的显示效果,故本发明提供的阵列基板可以提高显示装置的显示效果。
本发明还提供一种显示面板,包括上述阵列基板。由于上述阵列基板可以提高显示装置的显示效果,故本发明提高的显示面板具有较好的显示效果。
本发明还提供了一种显示装置,包括上述显示面板。具有较好的显示效果。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。

Claims (9)

1.一种薄膜晶体管,包括:栅极层,位于所述栅极层上的源极和漏极,以及位于所述源极和漏极上的有源层,所述有源层与所述源极和漏极电连接,其特征在于,所述有源层包括:两个平行设置的侧边,且每个所述侧边与所述源极朝向所述漏极的一面所成的锐角为45度;
所述有源层还包括:连接所述两个平行设置的侧边的第一连接边和第二连接边,所述第二连接边与所述两个平行设置的侧边的连接处形成避让倒角。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述源极包括:主体部、从所述主体部向所述漏极延伸的第一延伸部、从所述第一延伸部向背离所述漏极方向延伸的第二延伸部,从所述主体部向远离所述漏极方向延伸的第三延伸部,所述第一延伸部与所述第二延伸部和第三延伸部的延伸方向垂直。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述漏极包括:与所述第二延伸部平行设置的第一本体、从所述第一本体向所述源极方向延伸的第二本体,所述第二本体与所述第一本体相互垂直,所述第一延伸部和所述第二延伸部相对所述第一延伸部和所述第二延伸部连接处的夹角的角平分线对称,所述第一本体和所述第二本体相对所述角平分线对称。
4.根据权利要求3所述的薄膜晶体管,其特征在于,所述第一连接边与所述两个平行设置的侧边的连接处形成避让倒角。
5.根据权利要求4所述的薄膜晶体管,其特征在于,所述第一连接边与所述第一延伸部和所述第二延伸部的连接处相对应的部分设有向所述第二连接边凸起的避让口。
6.根据权利要求1~5任一项所述的薄膜晶体管,其特征在于,所述源极和所述漏极同层设置。
7.一种阵列基板,其特征在于,包括如权利要求1~6任一项所述的薄膜晶体管。
8.一种显示面板,其特征在于,包括如权利要求7所述的阵列基板。
9.一种显示装置,其特征在于,包括如权利要求8所述的显示面板。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877512A (en) * 1995-07-28 1999-03-02 Samsung Electronics Co., Ltd. Liquid crystal display device having uniform parasitic capacitance between pixels
US6274884B1 (en) * 1996-07-26 2001-08-14 Samsung Electronics Co., Ltd. Thin film transistors for liquid crystal displays
CN104465673A (zh) * 2014-12-30 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制造方法、以及显示装置

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* Cited by examiner, † Cited by third party
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US6274684B1 (en) 1999-10-22 2001-08-14 Univation Technologies, Llc Catalyst composition, method of polymerization, and polymer therefrom
KR102481378B1 (ko) * 2015-12-10 2022-12-27 삼성디스플레이 주식회사 박막 트랜지스터 기판, 및 표시 장치

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877512A (en) * 1995-07-28 1999-03-02 Samsung Electronics Co., Ltd. Liquid crystal display device having uniform parasitic capacitance between pixels
US6274884B1 (en) * 1996-07-26 2001-08-14 Samsung Electronics Co., Ltd. Thin film transistors for liquid crystal displays
CN104465673A (zh) * 2014-12-30 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制造方法、以及显示装置

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