CN105405806A - 等离子蚀刻和隐形切片激光工艺 - Google Patents
等离子蚀刻和隐形切片激光工艺 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 230000008569 process Effects 0.000 title description 18
- 238000001020 plasma etching Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 4
- 238000003698 laser cutting Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000003331 infrared imaging Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 abstract description 7
- 238000012986 modification Methods 0.000 abstract description 7
- 239000011888 foil Substances 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 38
- 239000007789 gas Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000008859 change Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000003333 near-infrared imaging Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241001050985 Disco Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000540 analysis of variance Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000013401 experimental design Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- KFZUDNZQQCWGKF-UHFFFAOYSA-M sodium;4-methylbenzenesulfinate Chemical compound [Na+].CC1=CC=C(S([O-])=O)C=C1 KFZUDNZQQCWGKF-UHFFFAOYSA-M 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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Abstract
与示例实施例一致,一种用于从具有正面和背面的晶圆衬底制备集成电路(IC)器件管芯的方法,其中,所述正面具有有源器件所述方法包括:将晶圆的正面安装在保护膜上。以第一聚焦深度将激光施加到晶圆的背面的锯道区域以限定改性区;所述改性区被限定在有源器件边界内预定深度处,并且所述有源器件具有由锯道限定的边界。拉伸保护膜以将IC器件管芯彼此分离并暴露出有源器件侧壁。对有源器件侧壁进行干法蚀刻,使得改性区被基本移除。
Description
技术领域
本公开的实施例涉及制备具有有源器件管芯的半导体晶圆以增加这些器件管芯(尤其是封装在射频识别装置(RFID)标签中的器件管芯)在被封装时的产量。具体地说,本公开涉及用于减少器件管芯上发生的侧壁龟裂的蚀刻工艺。
背景技术
通常通过在半导体衬底(诸如硅)上形成多个集成电路(IC)来产生IC。IC包括形成在衬底上的一个或多个层(例如,半导体层、绝缘层和金属化层)。单个IC被锯道(lane)分离。在晶圆上完成的IC随后例如通过沿锯道锯晶圆而被分离为单个IC。将晶圆分离为单个IC可被称为切片。可使用各种机械切割和激光切割方法来锯晶圆。机械切割工具容易在衬底的背面或正面引起破片。激光切割容易不均匀地切割完全或部分地覆盖衬底的锯道的金属化层。
在隐形激光切片工艺期间,激光聚焦于材料中并融化非晶硅。材料重新结晶为多晶硅,由于多晶结构的体积更大,导致在材料中诱发应力。这种应力产生用于管芯分离的龟裂(crack)。
针对一种特定类型的产品,即射频识别装置(RFID)标签,管芯分离特征已经成为RFID标签生产工艺的后期阶段的挑战。一旦器件管芯被胶合嵌入在RFID标签中,弯曲力可从管芯侧传递到(在所嵌入的管芯的侧壁上的)激光改性区(lasermodificationzone),导致管芯边缘的龟裂。
因此需要在组装RFID装置时消除该缺陷。
发明内容
已经发现本发明有利于封装可被嵌入RFID标签等中的半导体器件。RFID标签和其它智能卡装置在其寿命期间遭受机械应力。例如,将能够使用RFID的卡放进某人的口袋中可能会将应力施加到封装结构上。随着时间的流逝,累积的弯曲和破裂应力会损坏封装,并且到RFID的一个或多个电/机械连接会损坏;装备有RFID的装置将不再工作。
在组装工艺期间,侧壁应力在组装的装置管芯中累积。这些应力归因于晶圆锯开/分离。在示例实施例中,使用激光来切开晶圆衬底上的有源器件的锯道。激光能够在器件之间提供窄锯道。例如,与利用机械刀片的80μm的锯道相比,利用激光的锯道可以为大约15μm。然而,激光在切割区域中引入多晶硅的改性区,其中,它们之前是半导体器件的单晶结构的一部分。这些改性区易受应力影响;应力可在这些改性区中造成龟裂并扩散到半导体器件的有源区域中。干法蚀刻工艺移除这些改性区,使得侧壁基本上不具有多晶硅,从而减少侧壁应力并降低龟裂的可能性。
在示例实施例中,提供一种用于从具有正面和背面的晶圆衬底制备集成电路(IC)器件管芯的方法,其中,所述正面具有有源器件,所述有源器件具有由锯道限定的边界。所述方法包括:将晶圆的正面安装在保护膜上。以第一聚焦深度将激光施加到晶圆的背面的锯道区域以限定改性区,所述改性区被限定在有源器件边界内预定深度处。拉伸保护膜以将IC器件管芯彼此分离并暴露出有源器件侧壁。对有源器件侧壁进行干法蚀刻,使得改性区被基本移除。
在另一示例实施例中,一种集成电路(IC)器件管芯包括:在正表面上的有源器件以及与正表面相对的下表面,其中,所述有源器件被锯道划界。在锯道附近存在多个竖直侧壁,其中,所述多个竖直侧壁在其中限定了多晶硅的改性区。改性区暴露在等离子蚀刻剂中,使得基本上所有的多晶硅都被移除。
在示例实施例中,提供一种用于从晶圆衬底制备具有减小的侧壁应力的激光切割器件管芯的方法。所述方法包括:使用激光沿锯道切割晶圆衬底,所述锯道限定器件边界以得到单个器件管芯。使用蚀刻来移除针对单个器件管芯的侧壁的激光诱发应力。
本发明的以上内容不意图表示本发明的每个公开的实施例或每个方面。在下面的附图和详细描述中提供其它方面和示例实施例。
附图说明
通过下面结合附图考虑本发明的多个实施例的详细描述,可以更全面地理解本发明,其中:
图1示出组装在RFID封装中的IC器件中的应力的源;
图2A至图2B示出由于图1所示的应力而导致的器件管芯边缘龟裂;
图3是根据示例性实施例的用于制备晶圆的工艺的流程图;
图4A至图4B描绘示例激光切片工艺;
图5A至图5B是通过晶圆衬底背面的红外光成像来定位有源器件的示例;
图6A至图6D示出蚀刻硅改性层的示例实施例;
图7A至图7B示出硅改性层及其蚀刻的示例;
图8描绘针对两个示例工艺气体的移除程度相对于断裂应力的块图。
本发明可被修改为各种变形和备选形式,并且在附图中通过示例的方式示出其特定细节并将对其进行详细描述。然而,应该理解,本发明不将本发明限制为描述的特定实施例。相反,本发明覆盖落入由所附权利要求限定的本发明的精神和范围内的所有变形、等同物和备选。
具体实施方式
已经发现公开的实施例有助于防止对被制备用于封装在RFID标签等中的有源器件管芯的损坏。在一个示例中,工艺,“隐形切片”工艺可用于将这种晶圆分离为单个IC。隐形激光切片能够将锯道宽度间隔从大约60μm至80μm的正常宽度减少至大约15μm的最小宽度。利用该减少的锯道宽度,每片晶圆的潜在良好管芯(PGDW)量可显著增加。在该隐形激光切片工艺期间,改性区被实施在已经变薄的晶圆的硅层中。该改性区导致龟裂,该龟裂稍后可用于通过扩张处理将管芯彼此分离。
沿着各个锯道(IC沿这些锯道被分离)在晶圆的正面上的一个或多个金属化层中形成沟道。这些(分离)锯道位于IC之间并在晶圆的金属化层的正面和晶圆的硅衬底的背面之间延伸。在形成沟道之后,硅衬底的背面变薄,并且激光脉冲经由硅衬底的背面被施加以沿着锯道改变硅衬底的结晶结构。硅结构的这种改变弱化锯道中的硅。硅衬底中的改变部分(即,“改性区”)和沟道有助于在晶圆的扩展期间硅衬底中的龟裂沿着锯道扩散,同时减少龟裂向锯道外扩散。利用这种方法,可以实现晶圆分离,并同时减少可能由于龟裂的形成而出现的问题。
然而,利用“隐形切片”工艺,在器件管芯被封装到RFID标签中之后可能存在过大的管芯应力。管芯可能沿由于激光而改性的区域龟裂,导致RFID标签的可靠性因素彻底失败。参照图1,RFID标签35中的组装器件管芯25受到刀片15和滚子17施加的应力,该应力不像是用户标签在被放置在用户裤子后口袋中时会受到的力。区域10示出应力5明显的放大区域。参照图2A至图2B,示例器件管芯50(侧视图)示出沿着边缘的龟裂20。相同的示例器件管芯50(顶视图)示出沿着一些边缘的龟裂30。
可以在SaschaMoeller和MartinLapke于2012年11月28日提交的名为“WaferSeparation”的美国专利申请(No.13/687,110)中找到关于“隐形切片”的更多细节,并且该专利申请通过引用被全部合并于此。
可以在日本东京DISCO公司的名为“LaserApplication”的产品手册中找到关于“隐形切片”和“激光消融”的进一步信息。
此外,可以在GuidoAlbermann等人的名为“CombinationGrindingafterLaser(GAL)andLaserOn-OffFunctiontoIncreaseDieStrength”的美国专利申请(于2014年3月11日提交的S/N14/204,858)中找到用于增加RFID标签的器件管芯产量的工艺,该专利申请通过引用被全部合并于此。
然而,在本公开中,已经发现由于改性层的尺寸所直接导致的器件管芯龟裂的可能性增加。通过利用合适蚀刻剂(诸如氙-二氟气体(XeF2))的干法蚀刻处理来移除改性区不仅增强了器件管芯的侧壁强度,还增强了整个器件管芯结构的强度,从而减少在组装期间的器件管芯龟裂,并允许隐形切片使用15μm锯道。除了XeF2之外,其它气体蚀刻剂可包括溴三氟(BrF3)、氯三氟(ClF3)和氟气(F2)。
在一个示例工艺中,可利用以下配方移除改性区。使用的蚀刻设备是由加利福尼亚的圣何塞SPTS制造的XeF2释放蚀刻系统。
在示例实施例中,利用在大约5sccm至大约50sccm(标准每分钟立方厘米)的范围中的XeF2流速、大约120秒至大约180秒的周期时间来进行对改性区的蚀刻。在该示例实施例中使用的压力为大约21mTorr。
参照图3。在示例工艺中,在步骤110,对在正面具有有源器件管芯的晶圆衬底进行背面预研磨。例如,8英寸晶圆(200mm)的预研磨厚度大约为725μm,对于6英寸的晶圆(150mm)而言大约为675μm。应注意,该技术可应用于任何尺寸的晶圆衬底,并可用于12英寸(300mm)的衬底。在示例工艺中,晶圆被研磨至大约200μm的厚度。期望实现最小的晶圆厚度;然而,其受到使用200μm凸块(bump)将晶圆变薄的技术能力的限制。在示例工艺中,厚度可以在大约150μm至大约250μm的范围中。之后在步骤120,背景晶圆衬底的正面安装到保护膜上。之后在步骤130,调整目前受保护的晶圆衬底的朝向,使得背表面暴露在切片激光下。在步骤140,以第一聚焦深度将激光施加到晶圆的背面,以限定改性区。通过红外光或其它成像技术,在切割之前确定切割锯道(即,锯道)的位置。在步骤150,拉伸载体膜以在激光划分的器件的侧壁之间创建等距间隙。在步骤160,利用合适的蚀刻剂对器件侧壁进行干法蚀刻,以移除改性区。在示例实施例中,使用氙二氟(XeF2)。在步骤170,将晶圆的朝向重新调整为正面朝上,使得支撑带可以被移除。在步骤180,扩展晶圆以分离出将被嵌入到RFID标签180中的IC。在蚀刻期间,在单晶硅或多晶硅之间不存在明显的蚀刻选择性差异。此外,为了蚀刻至预定深度,在单晶硅和多晶硅之间不存在明显的时间差异。同时,取决于晶体方位(例如,{100}、{110}和{111})的蚀刻速率也不存在差异。
在另一示例实施例中,可以利用合适的湿蚀刻剂来移除改性区。然而,需要保护有源器件区域不受到湿蚀刻剂的蚀刻。
参照图4A至图4B。在示例实施例中,具有(利用透镜230)在规定深度聚焦的激光220的设备在晶圆衬底210的锯道215上执行隐形激光切片。示出长度大约为300μm且深度大约为50μm的激光扫描235a的改性区235b;激光扫描240a的(在一点处的)改性区240b的深度大约为50μm且长度为小于大约5μm。
参照图5A至图5B。在示例实施例中,经由在瞄准视场305中示出的红外光扫描具有器件管芯310的晶圆衬底300。锯道320是可见的。红外光成像允许激光对锯道320执行切片,从而产生改性区330。
参照图6A至图6D。对具有器件管芯410的晶圆衬底400的锯道420进行激光切片。拉伸载体膜430,使得在器件管芯410之间获得等距间隔。拉伸的晶圆400被置于蚀刻设备中。在一个示例实施例中,导入氙二氟(XeF2)55。对激光诱发的改性区415(在单晶层425之间)进行蚀刻,使得多晶硅基本被蚀刻掉,只留下最少的多晶硅435。
参照图7A至图7B。在示例实施例中,在蚀刻了器件管芯之后,用户可观察到在器件管芯500上,多晶硅520的改性区被夹在单晶层510之间。有源器件530在表面上。图7B的面板P1至P4示出改性层510的等离子蚀刻的示例,其中,P1的蚀刻的量最少,而P4的蚀刻的量最大。P2比参考P1具有更多的蚀刻,而比P3具有更少的蚀刻;P3比P4具有更少的蚀刻。
在将蚀刻应用于改性区时,改性区的尺寸不可被直接测量;然而,通过断裂强度值的分布的转移来确定蚀刻的适当量。可以通过进行实验设计(DoE)并确定达到管芯强度的目标改善的点来确定将被蚀刻掉的材料的量。可以看到,对于改性区只在光学上与之前稍有不同的情况下(蚀刻没有改变拓扑结构而仅移除了应力),已经达到了目标。
参照表1,基于有限数量的样本被处理的研究,可以推断,在侧壁处理的群组与参考之间存在明显差异。然而,统计数据还示出(当前还未被分析或模型的)其它参数的明显影响(差的R2值)。
在一个实施例中,这些因素由非最优化的针对使用的工艺的器件设计以及切口的窄开口(蚀刻剂不均匀渗透到切口中)而造成。正被蚀刻的密封环(sealring)区域和前端结构的部分正在引入新类型的弱点和新的断裂机制。为了利用工艺的所有潜能,需要提高器件设计(刻画锯道宽度、钝化结构)的适应性,以防止形成大的凸起并同时允许大量的移除。
图8示出通过使用两种不同工艺和蚀刻剂的管芯强度改善。第一气体是SF6,第二气体是XeF2。利用SF6的工艺示出两个块图,一个工艺820的气体较少(即,以较低的压力或和/或流速分配气体),而一个工艺810的气体较多(即,以较大的压力或和/或流速分配气体)。类似地,利用XeF2的工艺示出两个块图,一个的气体较少(830),而一个的气体较多(840)。
使用的采样来自于代表性RFID标签产品,其刻画锯道与工艺控制结构和其它金属结构无关。可以从ANOVA表中看到,在平均情况改善的同时,断裂强度相比于参考的变化增加。可以将增加的变化归因于切口宽度的不均匀性以及由于隐形切片切口位置的变化(即,曲折)而导致的正被蚀刻的不同的量。
RFID/标签环境自身不能被完全指明,这是因为其基于产品以及各个生产工艺步骤而不同。通过先前工艺步骤(诸如研磨或切片)的多个因素来确定管芯强度。然而,例如,传统断裂强度是600MPa。改善大约20%(即大于700MPa)将改善后续生产步骤的性能。
发现通过移除改性区来改善管芯强度的比率为针对(在0-1μm范围内)大约0.1μm的移除是大约200MPa。然而,当蚀刻总共超过1μm时,观察到管芯强度的降低,这可能与蚀刻到前端结构之下有关。
将受到所提出的工艺的器件设计需要被优化以实现最好的结果。总体而言,可以说,在可以消除负侧影响的情况下,较高的移除量将增加断裂强度。为此,管芯的密封环之间的距离需要足够大,以确保材料的移除不会进入到密封环之下。此外,意图蚀刻的区域应该不具有钝化材料等。在示例工艺中,可以将竖直蚀刻停止引入器件设计(例如,改性的密封环结构)中。精确的设计取决于对使用气体、器件厚度、器件之间的距离、工艺速度和使用的切片带的选择。
在示例测试中,蚀刻已经完全移除了改性区,因此在SEM分析中可以光学地看到该改性区已被移除(见图7B)。在极端图片P4上的与很长的蚀刻的重叠为大约8μm。改性区会比其更小(基于文字上的TEM分析)。
在示例工艺中,通过使用的激光引擎确定脉冲频率。通过切片速度(通常为300mm/s)和脉冲频率确定改性点的距离。对于一个实施例,SDE03为大约3μm。点的大小取决于使用的激光功率,该激光功率可以在大约0.8瓦至大约1.4W的范围(取决于厚度和衬底类型)内。
表2用于隐形激光切片的示例工艺
参照特定示意性示例描述了各个示例性实施例。选择示意性示例以帮助本领域普通技术人员形成对各个实施例的清楚理解并实施各个实施例。然而,可被构件为具有一个或多个实施例的器件、结构和系统的范围、以及可根据一个或多个实施例实施的方法的范围不应被限制为呈现的特定示意性示例。相反,本领域普通技术人员将容易地认识到,基于本描述,根据各个实施例的许多其它配置、布置和方法可被实施。
对于在描述本公开时使用的诸如顶、底、上、下的位置指定,将理解,参照相应附图给出这些指定,并且如果在生产或操作期间装置的方位改变,则可应用其它位置关系。如上所述,为了清楚而非限制描述这些位置关系。
已经针对特定实施例并参照特定附图描述了本公开,然而本发明不受限于此,而是仅在权利要求中被阐述。描述的附图仅仅是示意性的而非限制。在附图中,为了示意性目的,各个元件的大小可被夸大,并且不需要按特定比例绘制。意图本公开包含相关容差和组件属性以及操作模式的不重要的变化。意图覆盖本发明的不完美的实现。
在术语“包括”被用在本描述和权利要求中的情况下,其不排除其它元素或步骤。在指示名词单数形式时使用定冠词或不定冠词的情况下,除非另外清楚地说明,否则其包括名词复数形式。因此,术语“包括”不应被解释为限制为在其后所列的项目;其不排除其它元素或步骤,并且因此表述“装置包括项目A和B”的范围不应被限制为仅包括组件A和B的装置。该表述指明针对本公开,装置中的相关的组件仅为A和B。
在不脱离在所附权利要求中限定的本发明的精神和范围的情况下,本领域技术人员将清楚本发明的许多其它实施例。
Claims (15)
1.一种用于从具有正面和背面的晶圆衬底制备集成电路(IC)器件管芯的方法,其中,所述正面具有有源器件,所述有源器件具有由锯道限定的边界,所述方法包括:
将晶圆的正面安装在保护膜上;
以第一聚焦深度将激光施加到晶圆背面的锯道区域,以限定改性区,所述改性区被限定在有源器件边界内预定深度处;
拉伸保护膜,以将IC器件管芯彼此分离并暴露出有源器件侧壁;
对有源器件侧壁进行干法蚀刻,使得改性区被基本移除。
2.如权利要求1所述的方法,还包括:在将晶圆的正表面安装到保护膜上之前,预研磨晶圆衬底的背面。
3.如权利要求2所述的方法,其中,利用通过晶圆衬底的背面进行的红外成像来限定改性区,其中,所述改性区位于由锯道区域限定的边界内。
4.如权利要求1所述的方法,其中,于法蚀刻使用从以下各项之一选择的蚀刻剂:SF6、XeF2、BrF3、ClF3和F2。
5.如权利要求4所述的方法,其中,干法蚀刻包括:
将经过拉伸和分离的IC器件管芯置于蚀刻室中;以及
利用流速在大约5sccm至大约50sccm范围内的XeF2,在大约21mTorr的基底压力下,蚀刻经过分离的IC器件管芯,并且周期时间在大约25秒至大约900秒的范围内。
6.如权利要求5所述的方法,其中,周期时间在大约12秒至大约180秒的范围内。
7.如权利要求1所述的方法,其中,改性区被蚀刻至大约0.1μm至大约1μm的深度。
8.如权利要求6所述的方法,其中,改性区被蚀刻至大约0.1μm至大约1μm的深度。
9.一种集成电路(IC)器件管芯,包括:
有源器件,位于正表面上,所述有源器件被锯道划界;
下表面,与正表面相对;
多个竖直侧壁,位于锯道附近,其中,所述多个竖直侧壁在其中限定了多晶硅的改性区,
其中,改性区被暴露于等离子蚀刻剂中,使得基本上所有的多晶硅都被移除。
10.如权利要求9所述的IC器件,其中,等离子蚀刻剂是XeF2。
11.如权利要求10所述的IC器件,其中,锯道的宽度为大约15μm至大约80μm。
12.如权利要求11所述的IC器件,其中,锯道的宽度为大约15μm。
13.一种用于从晶圆衬底制备具有减小的侧壁应力的激光切割器件管芯的方法,所述方法包括:
使用激光沿锯道切割晶圆衬底,所述锯道限定器件边界以得到单个器件管芯;
使用蚀刻来移除针对单个器件管芯的侧壁的激光诱发应力。
14.如权利要求13所述的方法,其中,激光诱发应力是由激光形成的多晶硅改性区。
15.如权利要求13所述的方法,其中,蚀刻是干法蚀刻。
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Cited By (5)
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CN111451646A (zh) * | 2020-04-24 | 2020-07-28 | 苏州镭明激光科技有限公司 | 一种晶圆激光隐形切割的加工工艺 |
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US12131924B2 (en) | 2020-12-11 | 2024-10-29 | Yangtze Memory Technologies Co., Ltd. | Method for processing semiconductor wafers |
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US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
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US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
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US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11538711B2 (en) | 2018-07-23 | 2022-12-27 | Micron Technology, Inc. | Methods for edge trimming of semiconductor wafers and related apparatus |
US11217550B2 (en) | 2018-07-24 | 2022-01-04 | Xilinx, Inc. | Chip package assembly with enhanced interconnects and method for fabricating the same |
US20200075533A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
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US11701739B2 (en) * | 2019-04-12 | 2023-07-18 | Skyworks Solutions, Inc. | Method of optimizing laser cutting of wafers for producing integrated circuit dies |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US11011424B2 (en) * | 2019-08-06 | 2021-05-18 | Applied Materials, Inc. | Hybrid wafer dicing approach using a spatially multi-focused laser beam laser scribing process and plasma etch process |
US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US20230411169A1 (en) * | 2022-06-15 | 2023-12-21 | Western Digital Technologies, Inc. | Semiconductor wafer thinned by horizontal stealth lasing |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020127824A1 (en) * | 1998-10-23 | 2002-09-12 | Shelton Bryan S. | Semiconductor wafer protection and cleaning for device separation using laser ablation |
US20050045276A1 (en) * | 2001-05-22 | 2005-03-03 | Patel Satyadev R. | Method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants |
CN101106103A (zh) * | 2006-07-14 | 2008-01-16 | 优迪那半导体有限公司 | 发光元件的制造方法 |
CN101297394A (zh) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | 半导体器件的制造方法以及半导体器件 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
ATE362653T1 (de) * | 2002-03-12 | 2007-06-15 | Hamamatsu Photonics Kk | Methode zur trennung von substraten |
GB2420443B (en) | 2004-11-01 | 2009-09-16 | Xsil Technology Ltd | Increasing die strength by etching during or after dicing |
JP5128575B2 (ja) * | 2009-12-04 | 2013-01-23 | リンテック株式会社 | ステルスダイシング用粘着シート及び半導体装置の製造方法 |
US8666530B2 (en) | 2010-12-16 | 2014-03-04 | Electro Scientific Industries, Inc. | Silicon etching control method and system |
US8673741B2 (en) | 2011-06-24 | 2014-03-18 | Electro Scientific Industries, Inc | Etching a laser-cut semiconductor before dicing a die attach film (DAF) or other material layer |
US20140145294A1 (en) | 2012-11-28 | 2014-05-29 | Nxp B.V. | Wafer separation |
US9034734B2 (en) * | 2013-02-04 | 2015-05-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Systems and methods for plasma etching compound semiconductor (CS) dies and passively aligning the dies |
US9812361B2 (en) | 2013-09-11 | 2017-11-07 | Nxp B.V. | Combination grinding after laser (GAL) and laser on-off function to increase die strength |
US8975163B1 (en) * | 2014-04-10 | 2015-03-10 | Applied Materials, Inc. | Laser-dominated laser scribing and plasma etch hybrid wafer dicing |
-
2014
- 2014-09-09 US US14/481,051 patent/US9601437B2/en active Active
-
2015
- 2015-08-27 CN CN201510535505.2A patent/CN105405806B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020127824A1 (en) * | 1998-10-23 | 2002-09-12 | Shelton Bryan S. | Semiconductor wafer protection and cleaning for device separation using laser ablation |
US20050045276A1 (en) * | 2001-05-22 | 2005-03-03 | Patel Satyadev R. | Method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants |
CN101297394A (zh) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | 半导体器件的制造方法以及半导体器件 |
CN101106103A (zh) * | 2006-07-14 | 2008-01-16 | 优迪那半导体有限公司 | 发光元件的制造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108996470A (zh) * | 2018-08-09 | 2018-12-14 | 烟台睿创微纳技术股份有限公司 | 一种mems晶圆切割方法 |
CN111451646A (zh) * | 2020-04-24 | 2020-07-28 | 苏州镭明激光科技有限公司 | 一种晶圆激光隐形切割的加工工艺 |
CN112585725A (zh) * | 2020-11-19 | 2021-03-30 | 长江存储科技有限责任公司 | 处理半导体晶圆的方法 |
CN112585725B (zh) * | 2020-11-19 | 2024-06-07 | 长江存储科技有限责任公司 | 处理半导体晶圆的方法 |
US12131924B2 (en) | 2020-12-11 | 2024-10-29 | Yangtze Memory Technologies Co., Ltd. | Method for processing semiconductor wafers |
CN117066978A (zh) * | 2023-10-16 | 2023-11-17 | 天通控股股份有限公司 | 一种钽酸锂键合晶片的减薄方法 |
CN117066978B (zh) * | 2023-10-16 | 2024-01-05 | 天通控股股份有限公司 | 一种钽酸锂键合晶片的减薄方法 |
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US9601437B2 (en) | 2017-03-21 |
US20160071770A1 (en) | 2016-03-10 |
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