CN105378847B - Dram子阵列级自动刷新存储器控制器优化 - Google Patents

Dram子阵列级自动刷新存储器控制器优化 Download PDF

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Publication number
CN105378847B
CN105378847B CN201480039303.2A CN201480039303A CN105378847B CN 105378847 B CN105378847 B CN 105378847B CN 201480039303 A CN201480039303 A CN 201480039303A CN 105378847 B CN105378847 B CN 105378847B
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China
Prior art keywords
refresh
row
dram
subarray
command
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Expired - Fee Related
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CN201480039303.2A
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English (en)
Chinese (zh)
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CN105378847A (zh
Inventor
D·V·斯里拉玛吉利
J·徐
X·董
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Qualcomm Inc
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Qualcomm Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618Refresh operations over multiple banks or interleaving
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
CN201480039303.2A 2013-07-12 2014-05-20 Dram子阵列级自动刷新存储器控制器优化 Expired - Fee Related CN105378847B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361845818P 2013-07-12 2013-07-12
US61/845,818 2013-07-12
US14/148,515 2014-01-06
US14/148,515 US9524771B2 (en) 2013-07-12 2014-01-06 DRAM sub-array level autonomic refresh memory controller optimization
PCT/US2014/038845 WO2015005975A1 (en) 2013-07-12 2014-05-20 Dram sub-array level autonomic refresh memory controller optimization

Publications (2)

Publication Number Publication Date
CN105378847A CN105378847A (zh) 2016-03-02
CN105378847B true CN105378847B (zh) 2018-06-12

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Country Link
US (1) US9524771B2 (https=)
EP (1) EP3020046A1 (https=)
JP (1) JP6211186B2 (https=)
KR (1) KR101763312B1 (https=)
CN (1) CN105378847B (https=)
WO (1) WO2015005975A1 (https=)

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KR102414047B1 (ko) 2017-10-30 2022-06-29 에스케이하이닉스 주식회사 통합 메모리 디바이스 및 그의 동작 방법
US11544168B2 (en) 2017-10-30 2023-01-03 SK Hynix Inc. Memory system
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KR102578002B1 (ko) * 2018-07-03 2023-09-14 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
US10636476B2 (en) * 2018-11-01 2020-04-28 Intel Corporation Row hammer mitigation with randomization of target row selection
CN113168861B (zh) 2018-12-03 2024-05-14 美光科技公司 执行行锤刷新操作的半导体装置
CN117198356A (zh) 2018-12-21 2023-12-08 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10957377B2 (en) 2018-12-26 2021-03-23 Micron Technology, Inc. Apparatuses and methods for distributed targeted refresh operations
US11615831B2 (en) 2019-02-26 2023-03-28 Micron Technology, Inc. Apparatuses and methods for memory mat refresh sequencing
US11227649B2 (en) 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US10978132B2 (en) 2019-06-05 2021-04-13 Micron Technology, Inc. Apparatuses and methods for staggered timing of skipped refresh operations
US11023171B2 (en) * 2019-07-17 2021-06-01 Micron Technology, Inc. Performing a refresh operation based on a write to read time difference
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) * 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
CN111158585B (zh) * 2019-11-27 2023-08-01 核芯互联科技(青岛)有限公司 一种内存控制器刷新优化方法、装置、设备和存储介质
US11309010B2 (en) 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
CN114255799B (zh) * 2020-09-22 2023-10-17 长鑫存储技术有限公司 存储器数据刷新方法及其控制器、存储器
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US12308069B2 (en) * 2020-10-26 2025-05-20 Qualcomm Incorporated DRAM with quick random row refresh for rowhammer mitigation
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KR102890189B1 (ko) 2021-08-26 2025-11-21 삼성전자주식회사 메모리 장치
KR20230031617A (ko) * 2021-08-27 2023-03-07 에스케이하이닉스 주식회사 데이터를 리프레쉬하는 데이터 저장 장치 및 그 동작 방법
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US20150016203A1 (en) 2015-01-15
KR101763312B1 (ko) 2017-07-31
CN105378847A (zh) 2016-03-02
WO2015005975A1 (en) 2015-01-15
JP2016526750A (ja) 2016-09-05
JP6211186B2 (ja) 2017-10-11
KR20160030542A (ko) 2016-03-18
US9524771B2 (en) 2016-12-20
EP3020046A1 (en) 2016-05-18

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Granted publication date: 20180612