CN105378760B - Ic模块、双ic卡、以及ic模块的制造方法 - Google Patents

Ic模块、双ic卡、以及ic模块的制造方法 Download PDF

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Publication number
CN105378760B
CN105378760B CN201480033526.8A CN201480033526A CN105378760B CN 105378760 B CN105378760 B CN 105378760B CN 201480033526 A CN201480033526 A CN 201480033526A CN 105378760 B CN105378760 B CN 105378760B
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Prior art keywords
hole
substrate
chip
coil
module
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CN105378760A (zh
Inventor
沟口祥之介
塚田哲也
畠山惠理子
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Toppan Inc
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Toppan Printing Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07775Antenna details the antenna being on-chip
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
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    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
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    • GPHYSICS
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    • G06K19/07773Antenna details
    • G06K19/07777Antenna details the antenna being of the inductive type
    • G06K19/07779Antenna details the antenna being of the inductive type the inductive antenna being a coil
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Abstract

本发明的IC模块具有:薄板状的基材,其具有第一面和第二面,并具有第一贯穿孔和与所述第一贯穿孔分离的第二贯穿孔;IC芯片,其设置于所述第一面,具有接触型通信功能及非接触型通信功能,并形成有2个端子;连接线圈,其形成于所述第一面,具有2个端部;接触端子部,其设置于所述第二面,以与接触型外部设备接触的方式构成;过桥配线,其设置于所述第二面,设置于与所述第一贯穿孔及所述第二贯穿孔重叠的位置,与所述接触端子部电绝缘;第一导电线,其插入所述第一贯穿孔中,对所述IC芯片的第一端子和所述过桥配线进行连接;第二导电线,其插入所述第二贯穿孔中,对所述过桥配线和所述连接线圈的第一端部进行连接;以及第三导电线,其对所述连接线圈的第二端部和所述IC芯片的第二端子进行连接。

Description

IC模块、双IC卡、以及IC模块的制造方法
技术领域
本发明涉及一种能够进行接触型通信和非接触型通信的IC模块、双IC卡以及IC模块的制造方法。
本申请基于2013年6月25日向日本提出的特愿2013-132898号而要求优先权,在此援引其内容。
背景技术
搭载了具有接触型通信功能、以及非接触型通信功能的IC芯片的 IC模块,由于与使用者的用途相应地对通信方式进行区分使用,因此能够用于各种用途。具体地说,该IC模块安装于通过电磁耦合而能够在IC模块之间进行供电和通信的卡主体上,作为双IC卡进行使用。通过电磁耦合,使IC模块和卡主体电连接,从而能够抑制IC模块和卡主体之间的电连接变得不稳定。其原因在于,在利用焊料等导电性的连接部件对IC模块和卡主体直接进行连接的情况下,在将双IC卡弯曲时,连接部件可能破损。
如上所述,作为IC模块和卡主体通过电磁耦合而电连接的双IC 卡,已知例如专利文献1至3记载的双IC卡。
在双IC卡用的IC模块中,在表面形成有与接触型外部设备接触的接触接口用的端子(接触端子部),在背面形成有变压器耦合(电磁耦合)用的连接线圈。另外,关于IC模块的基材,为了对连接线圈的最外侧的端部进行桥接而使该端部向基材的中央进行移动,对基材实施镀敷通孔加工,在基材的表面形成电桥(过桥配线)。在这里,所谓镀敷通孔加工,是指通过冲压等而在基材处形成通孔(贯穿孔),通过镀敷处理等而在该通孔中形成配线。
此外,基材表面的端子和背面的IC芯片通过使用了插入基材的通孔中的导线的、作为公知的导线键合法的冲孔导线键合法而连接。
在信用卡等的、诸如大量的数据交换或清算业务的通信这样的要求可靠性和安全性的用途中,使用接触型通信的双IC卡。另一方面,在出入门禁管理等的、验证主要是通信内容且通信数据量少的用途中,使用非接触型通信的双IC卡。
专利文献1:国际公开第99/26195号
专利文献2:国际公开第98/15916号
专利文献3:国际公开第96/35190号
发明内容
但是,在利用了镀敷通孔加工的连接方法中,必须对基材实施镀敷处理。因此,IC模块的制造工序变得复杂,IC模块的制造成本增高。
本发明就是鉴于上述问题而提出的,其目的在于提供一种IC模块、具备该IC模块的双IC卡、以及IC模块的制造方法,该IC模块能够容易且廉价地进行制造,而不进行镀敷处理。
为了解决上述课题,本发明提出了以下手段。
本发明的第一方式所涉及的IC模块具有:薄板状的基材,其具有第一面和第二面,具有第一贯穿孔和与所述第一贯穿孔分离的第二贯穿孔;IC芯片,其设置于所述第一面,具有接触型通信功能及非接触型通信功能,形成有第一端子和第二端子;连接线圈,其形成于所述第一面,具有第一端部和第二端部;接触端子部,其设置于所述第二面,以与接触型外部设备接触的方式构成;过桥配线,其设置于所述第二面,在从所述基材的厚度方向观察时,设置于与所述第一贯穿孔及所述第二贯穿孔重叠的位置,与所述接触端子部电绝缘;第一导电线,其插入所述第一贯穿孔中,对所述IC芯片的所述第一端子和所述过桥配线进行连接;第二导电线,其插入所述第二贯穿孔中,对所述过桥配线和所述连接线圈的所述第一端部进行连接;以及第三导电线,其对所述连接线圈的所述第二端部和所述IC芯片的所述第二端子进行连接。
另外,在上述第一方式中,所述IC芯片和所述接触端子部也可以通过辅助导电线而连接,该辅助导电线插入形成于所述基材的辅助贯穿孔中。
另外,在上述第一方式中,也可以具有树脂封装部,该树脂封装部对所述IC芯片、所述第一导电线、所述第二导电线、以及所述第三导电线进行覆盖。
另外,本发明的第二方式所涉及的双IC卡具有:上述第一方式所涉及的IC模块;以及板状的卡主体,其具有天线,形成有收容所述IC 模块的凹部,该天线具有耦合用线圈及主线圈,该耦合用线圈用于与所述IC模块的所述连接线圈进行电磁耦合,该主线圈为了与非接触型外部设备进行非接触型通信而与所述耦合用线圈连接。
另外,在本发明的第三方式所涉及的IC模块的制造方法中,准备具有第一面和第二面的薄板状的基材,在所述第一面处形成连接线圈,在所述基材处形成彼此分离的第一贯穿孔和第二贯穿孔,在所述第二面处形成接触端子部,该接触端子部以与接触型外部设备接触的方式构成,在所述第二面处,以从所述基材的厚度方向观察时过桥配线与所述第一贯穿孔及所述第二贯穿孔重叠的方式,形成与所述接触端子部电绝缘的所述过桥配线,在所述基材的所述第一面,安装具有接触型通信功能及非接触型通信功能的IC芯片,通过插入所述第一贯穿孔中的第一导电线,对所述IC芯片的所述第一端子和所述过桥配线进行连接,通过插入所述第二贯穿孔中的第二导电线,对所述过桥配线和所述连接线圈的第一端部进行连接,通过第三导电线,对所述连接线圈的第二端部和所述IC芯片的所述第二端子进行连接。
另外,在上述第三方式中,也可以在所述基材处形成辅助通孔,通过插入所述辅助通孔中的辅助导电线,对所述IC芯片和所述接触端子部进行连接。
另外,在上述第三方式中,也可以利用树脂封装部,对所述IC芯片、所述第一导电线、所述第二导电线、以及所述第三导电线进行覆盖。
发明的效果
根据上述方式所涉及的IC模块、双IC卡、以及IC模块的制造方法,能够不进行镀敷通孔加工而容易且廉价地制造IC模块、及双IC 卡。
附图说明
图1是示意性地表示本发明的一个实施方式所涉及的双IC卡的侧面剖视图。
图2是使本发明的一个实施方式所涉及的双IC卡的卡主体的一部分透过而得到的俯视图。
图3是本发明的一个实施方式所涉及的双IC卡的IC模块的俯视图。
图4是图3中的剖断线A1-A1的剖视图。
图5是本发明的一个实施方式所涉及的IC模块的仰视图。
图6是本发明的一个实施方式的第1变形例所涉及的双IC卡中的侧面的剖视图。
图7是本发明的一个实施方式的第1变形例所涉及的双IC卡的仰视图。
图8是本发明的一个实施方式的第2变形例所涉及的双IC卡中的仰视图。
图9是图8中的剖断线A2-A2的剖视图。
图10是本发明的一个实施方式的第2变形例所涉及的双IC卡的俯视图。
图11是说明本发明的一个实施方式所涉及的IC模块的制造方法的剖视图。
图12是说明本发明的一个实施方式所涉及的IC模块的制造方法的剖视图。
图13是说明本发明的一个实施方式所涉及的IC模块的制造方法的剖视图。
图14是说明本发明的一个实施方式所涉及的IC模块的制造方法的剖视图。
图15是用于说明本发明的一个实施方式所涉及的双IC卡的原理的等价电路图。
具体实施方式
下面,参照图1至图15,对本发明的一个实施方式所涉及的双IC 卡进行说明。
如图1及图2所示,双IC卡1具有:板状的卡主体10,其形成有凹部11;以及IC模块30,其收容在该凹部11中。
此外,图1是示意性地表示双IC卡1的剖视图,将后述的天线 13的匝数简化而示出。在图2中示出卡主体10中的天线13及电容性元件14,使基板12透过而仅示出其外形。
卡主体10具有:基板12;天线13,其设置于基板12的形成有凹部11的开口11a的第一面12a;电容性元件14,其与天线13连接(电连接);以及一对卡基材15,其对基板12、天线13、及电容性元件 14进行夹持并层叠而成。
基板12使用PET(聚对苯二甲酸乙二醇酯)或聚萘二甲酸乙二醇酯(PEN)等具有绝缘性的材料,在俯视观察时形成为矩形状(参照图 2)。此外,各卡基材15在俯视观察时也形成为矩形状。
在基板12的靠近短边12c的位置(与中央相比更靠近短边12c的位置)、即卡基材15的靠近短边的位置,形成有贯穿基板12的厚度方向D的收容孔12d。收容孔12d在俯视观察时形成为具有与基板12 的短边及长边平行的边的矩形状。基板12的厚度例如为15~50μm(微米)。
天线13具有:耦合用线圈18,其用于与IC模块30的后述的连接线圈31电磁耦合;以及主线圈19,其为了与读写器等非接触型外部设备(未图示)进行非接触型通信而与耦合用线圈18连接。此外,耦合用线圈18是配置于图2中的区域R1内的线圈,主线圈19是配置于与区域R1相邻的区域R2内的线圈。在基板12相对于收容孔12d而靠近长边12e的位置(与中央相比更靠近长边12e的位置)、即卡基材 15的长边侧,基于IC卡的规格(X 6302-1:2005(ISO/IEC 7811 -1:2002))而设定有能够形成压花的压花区域R3。
在本例中,耦合用线圈18形成为螺旋状,在收容孔12d周围卷绕 5次。压花区域R3处的构成耦合用线圈18的裸线18a的宽度,大于除了压花区域R3以外处的裸线18b的宽度。在配置于耦合用线圈18最内侧的裸线18b的端部,设置有与裸线18b相比宽度较大、形成为大致圆形状的端子部20。该端子部20形成于第一面12a。
主线圈19形成为螺旋状,在区域R2内卷绕3次。压花区域R3 处的构成主线圈19的裸线19a的宽度,大于除了压花区域R3以外处的裸线19b的宽度。通过使裸线19a的宽度及前述裸线18a的宽度较大,从而在压花形成于压花区域R3时,能够防止裸线18a、19a断线。
配置于耦合用线圈18最外侧的裸线18a的端部,与配置于主线圈 19最外侧的裸线19a的端部连接。
利用蚀刻,对铜箔或铝箔进行图案化,从而形成耦合线圈18、主线圈19。耦合线圈18、主线圈19的厚度例如为5~50μm。
如图1及图2所示,电容性元件14具有:电极板14a,其设置于基板12的第一面12a;以及电极板14b,其设置于基板12的第二面12b。电极板14a、14b以对基板12进行夹持而相对的方式配置。
电极板14a与配置于主线圈19最内侧的裸线19b的端部连接。
设置于第二面12b的连接配线21与电极板14b连接。该连接配线 21延伸至基板12的第二面12b处的与端子部20相对的部分为止,未图示的端子部设置于该延伸的部分。耦合用线圈18的端子部20、和连接配线21的端子部通过公知的卷边(crimping)加工等而电连接。电容性元件14串联连接在耦合用线圈18和主线圈19之间。
卡基材15由非结晶聚酯等聚酯类材料、PVC(聚氯乙烯)等氯乙烯类材料、聚碳酸酯类材料、PET-G(聚对苯二甲酸乙二醇酯共聚物) 等具有绝缘性及耐久性的材料形成。
如图1所示,前述凹部11形成于卡基材15。凹部11具有:第一收容部24,其形成于卡基材15的侧面;以及第二收容部25,其形成于第一收容部24的底面,与第一收容部24相比直径较小。第一收容部24的位于卡基材15侧面侧的开口为前述开口11a。
如图3至图5所示,IC模块30具有:薄板状的模块基材(基材) 33;IC芯片34及连接线圈31,其设置于模块基材33的第一面33a;以及多个接触端子(接触端子部)35及电桥(过桥配线)36,其设置于模块基材33的第二面33b。
模块基材33以与基板12相同的材料在俯视观察时形成为矩形状。在厚度方向D上观察时,在与电桥36重叠的位置处彼此分离的第一通孔(第一贯穿孔)33c和第二通孔(第二贯穿孔)33d形成于模块基材 33处。模块基材33的厚度方向与前述基板12的厚度方向D一致。模块基材33处除了通孔33c、33d以外,还形成有通孔(辅助贯穿孔) 33e。模块基材33的厚度例如为50~200μm。
作为IC芯片34,能够使用具有接触型通信功能及非接触型通信功能、且具有公知的结构的IC芯片。在IC芯片34处,在芯片主体34a 的外表面形成有第一端子34b、第二端子34c以及多个连接端子34d。
连接线圈31形成为螺旋状。连接线圈31在IC芯片34、以及通孔33c、33e周围卷绕3次。第二通孔33d形成于连接线圈31的外侧。在配置于连接线圈31最外侧的裸线的端部(第一端部)、以及配置于最内侧的裸线的端部(第二端部),分别设置有与裸线相比宽度形成得较大的端子部39、40。通过蚀刻,对铜箔或铝箔进行图案化,从而形成有连接线圈31。连接线圈31的厚度例如为5~50μm。连接线圈 31通过与卡主体10的耦合用线圈18之间的电磁耦合而构成非接触端子部。
此外,形成为螺旋状的连接线圈31可以由一匝线圈构成,也可以由具有多匝的匝数(多圈)的螺旋状线圈构成。
通过在模块基材33的第二面33b上例如对铜箔进行层压,从而多个接触端子35及电桥36形成为规定的图案。电桥36形成为在厚度方向D上观察时跨越连接线圈31的L字状(参照图5)。
多个接触端子35及电桥36彼此电绝缘。在铜箔的露出至外部的部分处,可以通过镀敷设置厚度为0.5~3μm的镍层,也可以进一步在该镍膜上通过镀敷而设置厚度为0.01~0.3μm的金层。
各接触端子35是用于与自动提款机等接触型外部设备进行接触的端子。接触端子35与内置于IC芯片34的芯片主体34a中的未图示的元件等连接。
利用厚度为50~200μm的引线框,在模块基材33的第二面33b 处形成多个接触端子,利用铜线,在模块基材33的第一面33a处形成连接线圈。
IC芯片34的第一端子34b和电桥36通过插入第一通孔33c中的第一导线(第一导电线)41而连接。电桥36和连接线圈31的端子部 39通过插入第二通孔33d中的第二导线(第二导电线)42而连接。连接线圈31的端子部40和IC芯片34的第二端子34c通过第三导线(第三导电线)43而连接。
在本例中,IC芯片34的连接端子34d和接触端子35通过插入通孔33e中的连接导线(辅助导电线)44而连接。导线41、42、43、以及连接导线44由金或铜形成,外径例如为10~40μm。
如上所述,通过IC芯片34、连接线圈31、电桥36、以及导线41、 42、43、44,构成闭合电路。
IC芯片34的第一端子34b和电桥36、电桥36和连接线圈31通过使用了导线41、42的冲孔导线键合法而连接。
IC芯片34的连接端子34d和接触端子35也通过使用了连接导线 44的冲孔导线键合法而连接。连接线圈31和IC芯片34的第二端子 34c通过使用了第三导线43的导线键合法而连接。
此外,在本实施方式中,如图6及图7中示出的IC模块30A所示,也可以在IC模块30的各结构的基础上,还具有覆盖IC芯片34、第一导线41、第三导线43、以及连接导线44的树脂封装部51。在图 7中,使树脂封装部51透过,并以双点划线示出。树脂封装部51例如能够由公知的环氧树脂等形成。
通过使IC模块30A具有树脂封装部51,从而能够保护IC芯片 34,防止导线41、43的断线。
也可以利用树脂封装部51,对第一通孔33c内部的至少一部分进行封装。通过上述方式,能够防止导线41脱落或者断线。并且,也可以利用树脂封装部51将第一通孔33c的全部封装。
并且,也可以利用树脂,对第二通孔33d内部的至少一部分或全部进行封装。通过上述方式,能够防止导线42脱落或者断线。
另外,如图8至图10中示出的IC模块30B所示,为了使第二通孔33d配置于与连接线圈31的内周相比的内侧,也可以以下述方式构成,即,使连接线圈31的一部分向IC芯片34侧弯曲,利用树脂封装部51对插入第二通孔33d中的第二导线42进行覆盖(封装)(参照图9)。在该情况下,通孔33c、33d、33e全都被树脂封装部51覆盖。在本例中,电桥56形成为直线状(参照图10)。
通过以上述方式构成IC模块30B,从而能够防止导线41、42、 43的断线。
也可以利用树脂封装部51,对第一通孔33c、第二通孔33d内部的至少一部分进行封装。通过上述方式,能够防止导线脱落或者断线。并且,也可以利用树脂封装部51对第一通孔33c、第二通孔33d的全部进行封装。
此外,如果能够覆盖IC芯片34及导线41、42、43,且具有一定的强度,则树脂封装部51的大小优选较小。树脂封装部51不需要大至能够覆盖连接线圈31整体。
下面,对制造以上述方式构成的IC模块30的、IC模块30的制造方法进行说明。
首先,如图11所示,在模块基材33的第一面33a处形成连接线圈31及端子部39、40(端子部40未图示)。连接线圈31以下述等方式形成,即,对安装于模块基材33第一面33a处的铜箔实施公知的蚀刻,在铜箔上形成规定的图案。
如图12所示,在模块基材33中的未形成连接线圈31的部分,利用公知的冲压等,形成彼此分离的通孔33c、33d、33e(通孔33e未图示)。此外,也可以在模块基材33处形成通孔33c、33d、33e后,在该模块基材33处形成连接线圈31。
如图13所示,在模块基材33的第二面33b处,形成多个接触端子35及电桥36。通过使预先形成了规定的图案的铜箔层压至模块基材 33的第二面33b,从而能够形成接触端子35及电桥36。此时,在厚度方向D上观察时,以使电桥36与通孔33c、33d重叠的方式,对铜箔进行定位。
然后,如图14所示,将IC芯片34安装于模块基材33的第一面 33a。为了对IC芯片34进行安装,能够优选使用公知的芯片黏着用粘接剂。
然后,如图4及图5所示,通过使用了导线41、42、43、44的公知的冲孔导线键合法或导线键合法,对连接线圈31、IC芯片34、多个接触端子35、以及电桥36进行连接。具体地说,通过插入通孔33c中的第一导线41,对IC芯片34的第一端子34b和电桥36进行连接。通过插入第二通孔33d的第二导线42,对电桥36和连接线圈31的端子部39进行连接。通过第三导线43,对连接线圈31的端子部40和IC 芯片34的第二端子34c进行连接。
此时,通过插入通孔33e中的连接导线44,对IC芯片34的连接端子34d和接触端子35进行连接。
通过以上工序,制造IC模块30。
在基板12处例如通过利用通常的凹版印刷所进行的抗蚀剂涂敷方式的蚀刻,形成天线13及电容性元件14等。将基板12、天线13、以及电容性元件14夹持于一对卡基材15之间,利用通过热压而实现的层压或者粘接剂,使一对卡基材15彼此一体化。然后,冲裁而形成各个卡形状。
通过对卡基材15进行铣削加工,从而形成凹部11,制造卡主体 10。
如图1所示,以使IC模块30的IC芯片34收容于该卡主体10的第二收容部25中的方式,通过未图示的热熔片(hot melt sheet)等粘接剂等,对卡主体10和IC模块30进行连接,制造双IC卡1。
此外,在制造前述IC模块30B时,在未图示的模具中对IC芯片 34、导线41、42、43进行树脂封装,形成覆盖IC芯片34、导线41、 42、43的树脂封装部51。
然后,对以上述方式构成的双IC卡1的作用进行说明。图15是用于说明本双IC卡1的原理的等价电路图。
通过由读写器(非接触型外部设备)D10的发送/接收电路D11 产生的未图示的高频信号,在发送/接收线圈D12中感应出高频磁场。该高频磁场作为磁能而在空间中进行辐射。
此时,如果双IC卡1位于该高频磁场中,则通过高频磁场,电流在由双IC卡1的天线13及电容性元件14构成的并联共振电路中流动。此时,在耦合用线圈18中也感应出由高频磁场引起的电流,但由于与在主线圈19中感应出的量相比,相差大于或等于一个数量级,因此接收灵敏度较大地依赖于主线圈19的特性。
由主线圈19和电容性元件14之间的共振电路接收到的信号向耦合用线圈18传递。然后,通过耦合用线圈18和连接线圈31之间的电磁耦合,信号传递至IC芯片34。
此外,虽未图示,但在双IC卡1在与自动提款机等接触型外部设备之间进行供电和通信的情况下,使设置于自动提款机的端子与双IC 卡1的接触端子35接触。然后,在自动提款机的控制部和IC芯片34 之间进行供电和通信。
如以上说明所述,根据本实施方式的IC模块30及IC模块30的制造方法,通过冲孔导线键合法或导线键合法,使IC芯片34、连接线圈31及电桥36、以及导线41、42、43构成闭合电路,而不进行镀敷通孔加工。因此,在制造IC模块30时,不需要对模块基材33实施镀敷处理,能够容易且廉价地制造IC模块30。
通过插入形成于模块基材33的通孔33e中的连接导线44,使IC 芯片34和接触端子35连接。通过在IC芯片34和接触端子35之间的连接中还使用冲孔导线键合法,从而能够更廉价地制造IC模块30。
通过利用树脂封装部51,对IC芯片34、导线41(第一导电线)、导线42(第二导电线)、以及导线43(第三导电线)进行覆盖,从而能够保护IC芯片34,并且防止导线41、42、43的断线。
另外,根据本双IC卡1,能够容易且廉价地制造IC模块30,从而作为具有IC模块30的双IC卡1整体,也能够容易且廉价地进行制造。
以上,参照附图,对本发明的一个实施方式进行了详述,但具体的结构不限于该实施方式,还包含在不脱离本发明的主旨的范围内的结构的变更、组合等。
例如,在前述实施方式中,主线圈19及连接线圈31卷绕了3次,耦合用线圈18卷绕了5次。但是,这些线圈18、19、31卷绕的次数不限于此,这些线圈18、19、31卷绕大于或等于1次即可。
接触端子部所具有的接触端子35的数量也可以是1个,而不是多个。
在前述实施方式中,双IC卡1具有IC模块30。
但是,具有IC模块30的对象不限于此,例如也可以设置在嵌入件、或护照等小册子等中。在将IC模块30设置于小册子封底的情况下,在该封底的中央部形成凹部,在凹部的周围设置耦合用线圈,并且在封底的缘部设置主线圈。
标号的说明
1 双IC卡
10 卡主体
11 凹部
13 天线
18 耦合用线圈
19 主线圈
30、30A、30B IC 模块
31 连接线圈
33 模块基材(基材)
33a 第一面
33b 第二面
33c 第一通孔(第一贯穿孔)
33d 第二通孔(第二贯穿孔)
33e 通孔(辅助贯穿孔)
34 IC芯片
34b 第一端子
34c 第二端子
35 接触端子(接触端子部)
36、56 电桥(过桥配线)
41 第一导线(第一导电线)
42 第二导线(第二导电线)
43 第三导线(第三导电线)
44 连接导线(辅助导电线)
51 树脂封装部
D 厚度方向
D10 读写器

Claims (5)

1.一种IC模块,其具有:
薄板状的基材;
IC芯片,其设置于所述基材的第一面,具有接触型通信功能及非接触型通信功能,并形成有第一端子和第二端子;
树脂封装部,其以将所述IC芯片覆盖的方式设置于所述基材的第一面;
连接线圈,其设置于所述基材的第一面,形成为螺旋状;
接触端子部,其设置于所述基材的第二面,用于与接触型外部设备接触;以及
过桥配线,其以在所述基材的厚度方向上观察时位于所述树脂封装部的内侧区域的方式设置于所述第二面,与所述接触端子部电绝缘,
所述连接线圈具有:
第一端子部,其配置于第一端部,该第一端部位于在所述基材的厚度方向上观察时的外周侧;
第二端子部,其配置于第二端部,该第二端部位于在所述基材的厚度方向上观察时的内周侧;以及
裸线,其一部分以在所述基材的厚度方向上观察时所述第一端子部位于所述树脂封装部的内侧区域的方式向所述IC芯片侧弯曲,并且形成为将所述IC芯片包围的螺旋状,将所述第一端子部和所述第二端子部连接,
在所述基材形成第一贯穿孔和第二贯穿孔,该第一贯穿孔和第二贯穿孔在所述基材的厚度方向上观察与所述过桥配线重叠的位置处彼此分离,
所述IC芯片的所述第一端子和所述过桥配线通过插入所述第一贯穿孔的第一导电线而连接,
所述过桥配线和所述连接线圈的第一端部通过插入所述第二贯穿孔的第二导电线而连接,
所述连接线圈的第二端部和所述IC芯片的第二端子通过第三导电线而连接,
所述树脂封装部对所述IC芯片、所述第一导电线、所述第二导电线以及所述第三导电线进行覆盖。
2.根据权利要求1所述的IC模块,其中,
所述IC芯片和所述接触端子部通过辅助导电线而连接,该辅助导电线插入形成于所述基材处的辅助贯穿孔中。
3.一种双IC卡,其具有:
权利要求1所述的IC模块;以及
板状的卡主体,其具有天线,形成有收容所述IC模块的凹部,该天线具有耦合用线圈及主线圈,该耦合用线圈用于与所述IC模块的所述连接线圈进行电磁耦合,该主线圈为了与非接触型外部设备进行非接触型通信而与所述耦合用线圈连接。
4.一种IC模块的制造方法,其中,
在薄板状的基材的第一面处形成连接线圈,该连接线圈具有:螺旋状的裸线,其将配置具有接触型通信功能以及非接触型通信功能的IC芯片的区域包围;以及第一端子部,其配置于所述裸线的外周侧的端部,并且配置于与所述裸线的最外周相比更靠近所述IC芯片的位置,
在所述基材处形成彼此分离的第一贯穿孔和第二贯穿孔,
在所述基材的第二面处将接触端子部以及过桥配线以使在所述基材的厚度方向观察时所述过桥配线与所述第一贯穿孔及所述第二贯穿孔重叠的方式形成,该接触端子部用于与接触型外部设备接触,所述过桥配线与所述接触端子部电绝缘,
在所述基材的所述第一面,安装所述IC芯片,
通过插入所述第一贯穿孔中的第一导电线,对所述IC芯片的第一端子和所述过桥配线进行连接,
通过插入所述第二贯穿孔中的第二导电线,对所述过桥配线和所述连接线圈的所述第一端子部进行连接,
通过第三导电线,对所述连接线圈的所述裸线的内周侧的端部和所述IC芯片的第二端子进行连接,
利用树脂封装部,对所述IC芯片、所述第一导电线、所述第二导电线以及所述第三导电线进行覆盖。
5.根据权利要求4所述的IC模块的制造方法,其中,
在所述基材处形成辅助贯穿孔,
通过插入所述辅助贯穿孔中的辅助导电线,对所述IC芯片和所述接触端子部进行连接。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL2256672T3 (pl) * 2008-02-22 2016-11-30 Transponder i postać książki
JP2016212778A (ja) * 2015-05-13 2016-12-15 凸版印刷株式会社 デュアルインターフェース通信媒体
FR3047101B1 (fr) * 2016-01-26 2022-04-01 Linxens Holding Procede de fabrication d’un module de carte a puce et d’une carte a puce
DE102016106698A1 (de) * 2016-04-12 2017-10-12 Infineon Technologies Ag Chipkarte und Verfahren zum Herstellen einer Chipkarte
WO2018092897A1 (ja) * 2016-11-18 2018-05-24 凸版印刷株式会社 電磁結合デュアルicカード及びicモジュール
FR3074335B1 (fr) * 2017-11-24 2019-10-18 Smart Packaging Solutions Module electronique a antenne optimisee pour carte a puce a double interface de communication
JP7306123B2 (ja) * 2019-07-18 2023-07-11 凸版印刷株式会社 Icモジュール、デュアルicカードおよびicモジュールの製造方法
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KR20220032774A (ko) * 2020-09-08 2022-03-15 엘지이노텍 주식회사 스마트 ic 기판, 스마트 ic 모듈 및 이를 포함하는 ic 카드
FR3131411B1 (fr) * 2021-12-24 2024-01-05 Wisekey Semiconductors Procédé de fabrication d’un module sans contact ayant une bobine d'antenne à inductance finement ajustable

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009075782A (ja) * 2007-09-19 2009-04-09 Toshiba Corp Icモジュール及びicカード
CN101416206A (zh) * 2006-03-30 2009-04-22 王子制纸株式会社 Ic模块、ic引入线以及ic封装体

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63149191A (ja) * 1986-12-15 1988-06-21 日立マクセル株式会社 Icカ−ド
FR2625000B1 (fr) * 1987-12-22 1991-08-16 Sgs Thomson Microelectronics Structure de carte a puce
FR2721732B1 (fr) * 1994-06-22 1996-08-30 Solaic Sa Carte à mémoire sans contact dont le circuit électronique comporte un module.
DE19516227C2 (de) 1995-05-03 2002-02-07 Infineon Technologies Ag Datenträgeranordnung, insbesondere Chipkarte
BR9711887A (pt) 1996-10-09 2002-01-02 Pav Card Gmbh Processo e disposição conectiva para produção de um cartão inteligente
JPH11149536A (ja) * 1997-11-14 1999-06-02 Toppan Printing Co Ltd 複合icカード
EP1031939B1 (en) 1997-11-14 2005-09-14 Toppan Printing Co., Ltd. Composite ic card
CA2277119C (en) * 1997-11-14 2003-06-03 Western Atlas International, Inc. Seismic data acquisition and processing using non-linear distortion in a groundforce signal
IL122250A (en) * 1997-11-19 2003-07-31 On Track Innovations Ltd Smart card amenable to assembly using two manufacturing stages and a method of manufacture thereof
TWI234252B (en) * 2003-05-13 2005-06-11 Siliconware Precision Industries Co Ltd Flash-preventing window ball grid array semiconductor package and chip carrier and method for fabricating the same
US7777317B2 (en) * 2005-12-20 2010-08-17 Assa Abloy Identification Technologies Austria GmbH (Austria) Card and manufacturing method
EP2426627B1 (fr) * 2010-09-02 2016-10-12 Oberthur Technologies Module lumineux pour dispositif à microcircuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101416206A (zh) * 2006-03-30 2009-04-22 王子制纸株式会社 Ic模块、ic引入线以及ic封装体
JP2009075782A (ja) * 2007-09-19 2009-04-09 Toshiba Corp Icモジュール及びicカード

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