CN105355656A - 能降低米勒电容的超结igbt器件 - Google Patents

能降低米勒电容的超结igbt器件 Download PDF

Info

Publication number
CN105355656A
CN105355656A CN201510819602.4A CN201510819602A CN105355656A CN 105355656 A CN105355656 A CN 105355656A CN 201510819602 A CN201510819602 A CN 201510819602A CN 105355656 A CN105355656 A CN 105355656A
Authority
CN
China
Prior art keywords
conduction type
region
semiconductor substrate
type base
igbt device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510819602.4A
Other languages
English (en)
Other versions
CN105355656B (zh
Inventor
张须坤
张广银
卢烁今
朱阳军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
Original Assignee
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu IoT Research and Development Center, Jiangsu CAS IGBT Technology Co Ltd filed Critical Jiangsu IoT Research and Development Center
Priority to CN201510819602.4A priority Critical patent/CN105355656B/zh
Publication of CN105355656A publication Critical patent/CN105355656A/zh
Application granted granted Critical
Publication of CN105355656B publication Critical patent/CN105355656B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及一种能降低米勒电容的超结IGBT器件，其包括半导体基板，半导体基板的漂移区内设置第一导电类型柱以及第二导电类型柱；在第二导电类型柱内的上部设有第二导电类型基区，第二导电类型基区内设有第一导电类型源区，第一导电类型源区、第二导电类型基区与半导体基板上的发射极金属欧姆接触，在第二导电类型基区内用于形成导电沟道区域的上方覆盖有多晶硅栅极，多晶硅栅极通过覆盖在第二导电类型基区、第一导电类型柱上的绝缘层与第一导电类型源区、第二导电类型基区绝缘隔离，在绝缘层上覆盖有浮空栅极，所述浮空栅极通过绝缘层与多晶硅栅极绝缘隔离。本发明能有效减少米勒电容，并能屏蔽寄生电容，提高超结器件的高频特性，安全可靠。

Description

能降低米勒电容的超结IGBT器件
技术领域
本发明涉及一种超结IGBT器件，尤其是一种能降低米勒电容的超结IGBT器件，属于超结IGBT器件的技术领域。
背景技术
超结自1989年发明之日始，一直被视为突破“硅限”（siliconlimit）关键。基于超结的IGBT，比传统IGBT具有更低的通态电阻，应用前景非常可观。IGBT器件作为双极器件，其漂移区中少子注入引起的电导调制使IGBT得以在中高压领域代替BJT（BipolarJunctionTransistor—BJT）及GTO（GateTurn-OffThyristor）。但是，电导调制也使IGBT具有较长的拖尾电流，工作频率低、关断损耗较高。SJ-IGBT（超结IGBT）在柱体（包括N柱以及P柱）内的掺杂浓度达超过5E15后，柱体内电导调制消失，电子在N柱内流动，空穴在P柱内流动。此时，SJ-IGBT在柱体内的电流传输模式为多子运输，特性类似于多子器件，说明SJ-IGBT几乎没有拖尾电流，开关速度快。
仿真SJ-IGBT器件的开关特性可以发现，SJ-IGBT的在米勒平台时间段的损耗和换流时的损耗相当，如何降低米勒电容是SJ-IGBT器件通态特性和开关特性（Eoff）之间进一步优化的关键，现有SJ-IGBT阴极制作工艺与传统IGBT类似，栅极与N柱之间的覆盖电容及发射极与栅极、N柱之间的寄生电容直接影响米勒电容的大小和器件的开关特性。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种能降低米勒电容的超结IGBT器件，其结构紧凑，能有效减少米勒电容，并能屏蔽寄生电容，提高超结器件的高频特性，安全可靠。
按照本发明提供的技术方案，所述能降低米勒电容的超结IGBT器件，包括具有第一导电类型的半导体基板，所述半导体基板的漂移区内设置若干呈交错分布的第一导电类型柱以及第二导电类型柱；在所述第二导电类型柱内的上部设有第二导电类型基区，所述第二导电类型基区内设有第一导电类型源区，第一导电类型源区、第二导电类型基区与半导体基板上的发射极金属欧姆接触，在第二导电类型基区内用于形成导电沟道区域的上方覆盖有多晶硅栅极，所述多晶硅栅极通过覆盖在第二导电类型基区、第一导电类型柱上的绝缘层与第一导电类型源区、第二导电类型基区绝缘隔离，在绝缘层上覆盖有浮空栅极，所述浮空栅极通过绝缘层与多晶硅栅极绝缘隔离，且浮空栅极上覆盖有介电质层，浮空栅极、多晶硅栅极通过介电质层与发射极金属绝缘隔离。
在所述半导体基板的漂移区下方设有第一导电类型缓冲层，所述第一导电类型缓冲层上设有第二导电类型集电区，所述第二导电类型集电区上设置欧姆接触的集电极金属。
所述半导体基板包括硅衬底。
所述“第一导电类型”和“第二导电类型”两者中，对于N型超结IGBT，第一导电类型指N型，第二导电类型为P型；对于P型超结IGBT，第一导电类型与第二导电类型所指的类型与N型超结IGBT正好相反。
本发明的优点：由于多晶硅栅极仅覆盖P型基区内用于形成沟道区域，达到减少栅极面积，而栅极面积的减小可以有效降低栅电极与集电极之间的米勒电容，以提高IGBT器件的开关特性，降低开关损耗。
此外，在多晶硅栅极的上方设置浮空栅极，多晶硅栅极与上方的发射极金属间具有绝缘层、浮空栅极以及介电质层，即通过浮空栅极能屏蔽多晶硅栅极与发射极金属之间的寄生电容，降低IGBT器件的开关延迟；在发射极金属与N柱间具有绝缘层、浮空栅极以及介电质层，即能通过浮空栅极能屏蔽发射极金属与N柱之间的寄生电容，从而降低发射极与集电极之间的输出电容。
附图说明
图1为本发明的结构示意图。
附图标记说明：1-发射极金属、2-浮空栅极、3-介电质层、4-绝缘层、5-多晶硅栅极、6-N+源区、7-P型基区、8-N柱、9-P柱、10-N型缓冲层、11-P+集电区以及12-集电极金属。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图1所示：以N型超结IGBT器件为例，本发明包括具有N型的半导体基板，所述半导体基板的漂移区内设置若干呈交错分布的N柱8以及P柱9；在所述P柱9内的上部设有P型基区7，所述P型基区7内设有N+源区6，N+源区6、P型基区7与半导体基板上的发射极金属1欧姆接触，在P型基区7内用于形成导电沟道区域的上方覆盖有多晶硅栅极5，所述多晶硅栅极5通过覆盖在P基区7、N柱8上的绝缘层4与N+源区6、P型基区7绝缘隔离，在绝缘层4上覆盖有浮空栅极2，所述浮空栅极2通过绝缘层4与多晶硅栅极5绝缘隔离，且浮空栅极2上覆盖有介电质层3，浮空栅极2、多晶硅栅极5通过介电质层3与发射极金属1绝缘隔离。
具体地，所述半导体基板包括硅衬底，半导体基板也可以采用常用的半导体材料。对于N型超结IGBT器件，半导体基板的导电类型为N型，在N型半导体基板的漂移区内设置若干N柱8以及P柱9，N柱8、P柱9在半导体基板的漂移区内交替分布，一般地，N柱8的宽度与P柱9的宽度相一致，N柱8、P柱9的高度与漂移区在半导体基板的厚度相一致，N柱8、P柱9的顶端对应半导体基板的正面，通过半导体基板漂移区内的N柱8与P柱9形成所需的超结结构。
N+源区6对称分布于P型基区7内，P型基区7位于P柱9内的上部，P型基区7从半导体基板的正面向下延伸，P型基区7在P柱9内的宽度不小于P柱9的宽度。发射极金属1位于半导体基板的正面上，发射极金属1与N+源区6、P型基区7欧姆接触。多晶硅栅极5仅覆盖在P型基区7内用于形成沟道区域的上方，多晶硅栅极5通过绝缘层4与P型基区7、N+源区6以及N柱8绝缘隔离，绝缘层4一般可以为二氧化硅层，绝缘层4覆盖在N柱8的表面以及P型基区7内用于形成沟道区域的表面，绝缘层4位于半导体基板的正面上。
浮空栅极2一般也采用导电多晶硅，浮空栅极2覆盖在绝缘层4上，浮空栅极2通过绝缘层4与多晶硅栅极5绝缘隔离，在所述IGBT器件的截面上，浮空栅极2的长度域绝缘层4的长度相一致。此外，在所述IGBT器件的截面上，发射极金属1位于P柱9的上方，且发射极金属1还向N柱8的方向延伸；发射极金属1与所述发射极金属1下方的介电质层3与浮空栅极2绝缘隔离，且负控栅极2、多晶硅栅极5邻近发射极金属1的端部也通过介电质层3与所述发射极金属1绝缘隔离；介电质层3与N+源区6相接触。
进一步地，在所述半导体基板的漂移区下方设有N型缓冲层10，所述N型缓冲层10上设有P+集电区11，所述P+集电区11上设置欧姆接触的集电极金属12。
本发明实施例中，通过集电极金属12以及P+集电区11能用于形成IGBT器件的集电极，同时，通过发射极金属1用于形成IGBT器件的发射极，通过多晶硅栅极5形成IGBT器件的栅电极。
本发明实施例中，由于多晶硅栅极5仅覆盖P型基区7内用于形成沟道区域，达到减少栅极面积，而栅极面积的减小可以有效降低栅电极与集电极之间的米勒电容，以提高IGBT器件的开关特性，降低开关损耗。
此外，在多晶硅栅极5的上方设置浮空栅极2，多晶硅栅极5与上方的发射极金属1间具有绝缘层4、浮空栅极2以及介电质层3，即通过浮空栅极2能屏蔽多晶硅栅极5与发射极金属1之间的寄生电容，降低IGBT器件的开关延迟；在发射极金属1与N柱8间具有绝缘层4、浮空栅极2以及介电质层3，即能通过浮空栅极2能屏蔽发射极金属1与N柱8之间的寄生电容，从而降低发射极与集电极之间的输出电容。

Claims (3)

1.一种能降低米勒电容的超结IGBT器件，包括具有第一导电类型的半导体基板，所述半导体基板的漂移区内设置若干呈交错分布的第一导电类型柱以及第二导电类型柱；其特征是：在所述第二导电类型柱内的上部设有第二导电类型基区，所述第二导电类型基区内设有第一导电类型源区，第一导电类型源区、第二导电类型基区与半导体基板上的发射极金属（1）欧姆接触，在第二导电类型基区内用于形成导电沟道区域的上方覆盖有多晶硅栅极（5），所述多晶硅栅极（5）通过覆盖在第二导电类型基区、第一导电类型柱上的绝缘层（4）与第一导电类型源区、第二导电类型基区绝缘隔离，在绝缘层（4）上覆盖有浮空栅极（2），所述浮空栅极（2）通过绝缘层（4）与多晶硅栅极（5）绝缘隔离，且浮空栅极（2）上覆盖有介电质层（3），浮空栅极（2）、多晶硅栅极（5）通过介电质层（3）与发射极金属（1）绝缘隔离。
2.根据权利要求1所述的能降低米勒电容的超结IGBT器件，其特征是：在所述半导体基板的漂移区下方设有第一导电类型缓冲层，所述第一导电类型缓冲层上设有第二导电类型集电区，所述第二导电类型集电区上设置欧姆接触的集电极金属（12）。
3.根据权利要求1所述的能降低米勒电容的超结IGBT器件，其特征是：所述半导体基板包括硅衬底。
CN201510819602.4A 2015-11-23 2015-11-23 能降低米勒电容的超结igbt器件 Active CN105355656B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510819602.4A CN105355656B (zh) 2015-11-23 2015-11-23 能降低米勒电容的超结igbt器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510819602.4A CN105355656B (zh) 2015-11-23 2015-11-23 能降低米勒电容的超结igbt器件

Publications (2)

Publication Number Publication Date
CN105355656A true CN105355656A (zh) 2016-02-24
CN105355656B CN105355656B (zh) 2019-02-15

Family

ID=55331589

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510819602.4A Active CN105355656B (zh) 2015-11-23 2015-11-23 能降低米勒电容的超结igbt器件

Country Status (1)

Country Link
CN (1) CN105355656B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109671626A (zh) * 2018-12-12 2019-04-23 吉林华微电子股份有限公司 具有负反馈电容的igbt器件及制作方法
CN110444586A (zh) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 具有分流区的沟槽栅igbt器件及制备方法
CN113748520A (zh) * 2019-11-27 2021-12-03 苏州东微半导体股份有限公司 Igbt器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0475338A (ja) * 1990-07-18 1992-03-10 Seiko Epson Corp 機械・化学研磨法
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
US6967374B1 (en) * 2004-07-07 2005-11-22 Kabushiki Kaisha Toshiba Power semiconductor device
CN102569386A (zh) * 2010-12-17 2012-07-11 上海华虹Nec电子有限公司 具有屏蔽栅的vdmos器件及其制备方法
US9105487B2 (en) * 2012-07-18 2015-08-11 Infineon Technologies Ag Super junction semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0475338A (ja) * 1990-07-18 1992-03-10 Seiko Epson Corp 機械・化学研磨法
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
US6967374B1 (en) * 2004-07-07 2005-11-22 Kabushiki Kaisha Toshiba Power semiconductor device
CN102569386A (zh) * 2010-12-17 2012-07-11 上海华虹Nec电子有限公司 具有屏蔽栅的vdmos器件及其制备方法
US9105487B2 (en) * 2012-07-18 2015-08-11 Infineon Technologies Ag Super junction semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109671626A (zh) * 2018-12-12 2019-04-23 吉林华微电子股份有限公司 具有负反馈电容的igbt器件及制作方法
CN110444586A (zh) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 具有分流区的沟槽栅igbt器件及制备方法
CN113748520A (zh) * 2019-11-27 2021-12-03 苏州东微半导体股份有限公司 Igbt器件
CN113748520B (zh) * 2019-11-27 2022-05-31 苏州东微半导体股份有限公司 Igbt器件

Also Published As

Publication number Publication date
CN105355656B (zh) 2019-02-15

Similar Documents

Publication Publication Date Title
CN103383958B (zh) 一种rc-igbt器件及其制作方法
CN108198851A (zh) 一种具有增强载流子存储效应的超结igbt
CN102456718A (zh) 绝缘栅双极晶体管器件用于提升器件性能的新型上部结构
CN102005473B (zh) 具有改进终端的igbt
CN106298900A (zh) 一种高速soi‑ligbt
CN109192774A (zh) 栅极双箝位的igbt器件
CN104319287A (zh) 一种沟槽栅型半导体器件结构及其制作方法
CN105489644B (zh) Igbt器件及其制作方法
CN105355656A (zh) 能降低米勒电容的超结igbt器件
CN109065620B (zh) 一种具有低米勒电容的igbt器件
CN103258848B (zh) 一种具有正温度系数发射极镇流电阻的igbt器件
CN205231070U (zh) Igbt器件
CN208580747U (zh) 栅极双箝位的igbt器件
CN109148572A (zh) 一种反向阻断型fs-gbt
CN107799602A (zh) 能节省终端面积的屏蔽栅mosfet器件及其制备方法
CN102157550B (zh) 一种具有p埋层的纵向沟道SOI LIGBT器件单元
CN104299990A (zh) 绝缘栅双极晶体管及其制造方法
CN103681819B (zh) 一种沟槽型的绝缘栅双极性晶体管及其制备方法
CN106941115B (zh) 一种自驱动阳极辅助栅横向绝缘栅双极型晶体管
CN108767001B (zh) 具有屏蔽栅的沟槽型igbt器件
CN204885170U (zh) 具有自适应性的场截止电流控制型功率器件
CN110190114B (zh) 一种栅控双极-场效应复合碳化硅垂直双扩散金属氧化物半导体晶体管
CN202018966U (zh) 具有p埋层的纵向沟道SOI LIGBT器件单元
CN207338383U (zh) 绝缘栅双极晶体管及ipm模块
CN202058737U (zh) 具有p埋层的横向沟道soi ligbt器件单元

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant