CN105336579B - 一种半导体元件及其制备方法 - Google Patents

一种半导体元件及其制备方法 Download PDF

Info

Publication number
CN105336579B
CN105336579B CN201510629914.9A CN201510629914A CN105336579B CN 105336579 B CN105336579 B CN 105336579B CN 201510629914 A CN201510629914 A CN 201510629914A CN 105336579 B CN105336579 B CN 105336579B
Authority
CN
China
Prior art keywords
layer
oxygen
oxygen doping
preparation
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510629914.9A
Other languages
English (en)
Other versions
CN105336579A (zh
Inventor
徐志波
周圣伟
程志青
王肖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui Sanan Optoelectronics Co Ltd
Original Assignee
Anhui Sanan Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui Sanan Optoelectronics Co Ltd filed Critical Anhui Sanan Optoelectronics Co Ltd
Priority to CN201510629914.9A priority Critical patent/CN105336579B/zh
Publication of CN105336579A publication Critical patent/CN105336579A/zh
Priority to PCT/CN2016/097757 priority patent/WO2017054613A1/zh
Priority to US15/607,505 priority patent/US10158046B2/en
Application granted granted Critical
Publication of CN105336579B publication Critical patent/CN105336579B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

本发明提出了一种半导体元件，通过利用衬底上生长的金属保护层、金属氧化物保护层避免硅衬底表面非晶态层的形成；利用过渡层减小所述金属氧化物保护层与所述III‑IV族缓冲层的晶格差异，提高所述III‑IV族缓冲层的晶体质量。本发明同时提出一种制备方法，该方法可以避免在硅衬底界面附近非晶态层的形成，避免裂纹的产生。同时充分利用PVD法沉积的高质量多层缓冲结构，及在其上生长氮化镓或铟镓氮或铝镓氮外延层，制作成发光二极管元件或晶体管元件。

Description

一种半导体元件及其制备方法
技术领域
本发明属于半导体技术领域，特别涉及一种半导体元件及其制备方法。
背景技术
物理气相沉积法（PVD法）具有工艺过程简单、对环境污染小、原材消耗少、成膜均匀致密、与基板的结合力强等特点，目前被越来越多地应用于半导体元件的制备中，通常较多地用于底层的制备，例如沉积氮化铝层作为缓冲层，可降低及缓冲衬底与外延层之间因晶格失配和热失配产生的缺陷和应力，改善半导体元件的器件质量。
相较于化学气相沉积，PVD法溅射出来的原子具有较高的能量（一般在10~20eV）和较强的迁移能力，因此，采用PVD法可以沉积出高质量的缓冲层，特别是对于AlN这一类结合键能强的物质，采用PVD法沉积的膜层较MOCVD法沉积的膜层质量更佳。但是目前在硅衬底表面直接采用物理气相沉积的方法生长氮化铝，容易在衬底与氮化铝界面形成非晶态氧化硅层，导致后续形成的氮化铝层质量变差，造成下面问题：氮化铝层作为应力缓冲层，其释放应力的能力不一致，应力集中在界面上的非晶态氮化硅层上，容易导致裂纹的产生，破坏整个半导体器件质量；氮化铝层的致密性变差，产生孔隙，其后在化学气相沉积含镓的氮化物时，镓元素通过孔隙直接腐蚀硅衬底，形成坑洞，破坏整个半导体器件性能。
发明内容
针对上述问题，本发明提出了一种半导体元件，通过利用衬底上生长的铝金属保护层、氧化铝金属氧化物保护层避免硅衬底表面非晶态层的形成；利用氧掺杂氮化铝过渡层减小所述氧化铝金属氧化物保护层与所述氧掺杂氮化铝缓冲层的晶格差异，提高所述氧掺杂氮化铝缓冲层的晶体质量。本发明同时提出一种制备方法，该方法可以避免在硅衬底界面附近非晶态层的形成，避免裂纹的产生。同时充分利用PVD法沉积的高质量多层缓冲结构，及在其上生长氮化镓层或铟镓氮层或铝镓氮层，制作成发光二极管或晶体管元件。
本发明提供的技术方案为：一种半导体元件，包括硅衬底、多层缓冲结构和外延功能层，其中，所述多层缓冲结构包括依次排列生成的铝金属保护层、氧化铝金属氧化物保护层、氧掺杂氮化铝过渡层和氧掺杂氮化铝缓冲层；所述铝金属保护层、氧化铝金属氧化物保护层避免所述硅衬底表面非晶态层的形成；所述氧掺杂氮化铝过渡层用于减小所述氧化铝金属氧化物保护层与所述氧掺杂氮化铝缓冲层的晶格差异，提高所述氧掺杂氮化铝缓冲层的晶体质量。
优选的，所述铝金属保护层的厚度为1～100埃。
优选的，所述氧化铝金属氧化物保护层的厚度为1～500埃。
优选的，所述氧掺杂氮化铝过渡层的氧掺杂浓度≥1×1019cm-3。
优选的，所述氧掺杂氮化铝缓冲层的氧掺杂浓度≤4×1022cm-3。
同时，本发明提出一种半导体元件结构的制备方法，依次在一硅衬底上形成多层缓冲结构和外延功能层，其中，所述多层缓冲结构通过下面方法形成：
利用物理气相沉积法于所述硅衬底表面沉积铝金属保护层；
通入氧气，使所述铝金属保护层上表面氧化，然后采用物理气相沉积法于所述铝金属保护层表面沉积氧化铝金属氧化物保护层；
保持氧气持续通入，增加氮气通入，利用物理气相沉积法于所述氧化铝金属氧化物保护层表面沉积氧掺杂氮化铝过渡层；
关闭氧气，保持氮气持续通入，利用物理气相沉积法于所述氧掺杂氮化铝过渡层表面沉积氧掺杂氮化铝缓冲层，构成多层缓冲结构。
优选的，所述铝金属保护层的厚度为1～100埃。
优选的，所述氧化铝金属氧化物保护层的厚度为1～500埃。
优选的，所述氧掺杂氮化铝过渡层的氧浓度≥1×1019cm-3，所述氧掺杂氮化铝过渡层厚度为1～1000nm。
优选的，所述氧掺杂氮化铝过渡层的氧浓度≥1×1019cm-3，所述氧掺杂氮化铝过渡层厚度为5~50nm。
优选的，所述氧掺杂氮化铝缓冲层的氧浓度≤4×1022cm-3，所述氧掺杂氮化铝缓冲层厚度为10～1000nm。
优选的，所述氧掺杂氮化铝缓冲层的氧浓度≤4×1022cm-3，所述氧掺杂氮化铝缓冲层厚度为200~300nm。
优选的，所述氧掺杂氮化铝过渡层的氧掺杂浓度大于所述氧掺杂氮化铝缓冲层氧掺杂浓度。
优选的，所述外延功能层为氮化镓基发光二极管外延或铝镓氮晶体管外延层。
本发明至少具有以下有益效果：
1、本发明利用铝金属保护层、氧化铝金属氧化物保护层保护硅衬底表面，避免在硅衬底界面上非晶态层的形成，避免裂纹和孔隙的产生，消除后续含镓的氮化物中镓元素通过孔隙腐蚀硅衬底，破坏整个半导体器件质量；而利用氧掺杂氮化铝过渡层减小氧化铝金属氧化物保护层与氧掺杂氮化铝缓冲层的晶格差异，提高氧掺杂氮化铝缓冲层的晶体质量。
2、采用物理气相法沉积多层缓冲结构时，由于溅射原子的能量高，迁移率高，其沉积的膜层质量高于通常的化学气相沉积法，进而获得高平整度的缓冲层界面；继续在其表面生长氮化镓、铝镓氮、铟镓氮等膜层时，使得位错及缺陷密度大大减少，改善氮化物半导体器件的晶体质量，减少器件漏电现象，增加了器件的可靠性，提升整个发光半导体器件的发光效率及电子迁移率。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1为本发明实施例一之半导体结构示意图一。
图2为本发明实施例一之多层缓冲结构结构示意图。
图3为本发明实施例一之半导体结构示意图二。
图4为本发明实施例二之半导体结构示意图。
图中：10.硅衬底；20. 多层缓冲结构；21. 铝金属保护层；22. 氧化铝金属氧化物保护层；23. 氧掺杂氮化铝过渡层；24. 氧掺杂氮化铝缓冲层； 30. 外延功能层；31. 第一半导体层；32.发光层；33.第二半导体层； 34. 非掺杂半导体层；35. 铝镓氮层；36. 氮化镓半导体层；37. 铝镓氮半导体层；38. 氮化镓半导体覆盖层。
具体实施方式
下面结合附图和实施例对本发明的具体实施方式进行详细说明。
实施例1
参看附图1～2，本实施例提供一种半导体元件，其包括：硅衬底10、多层缓冲结构20和外延功能层30，此处，所述外延功能层30为第一半导体层31、发光层32和第二半导体层33组成的发光二极管外延层；第一半导体层31与第二半导体层33分别为掺杂有施主杂质的半导体层和掺杂有受主杂质的半导体层。当然，本发明的半导体元件中还可以包含非掺杂半导体层34（参看附图3）。多层缓冲结构20由厚度为1～100埃的铝金属保护层21、厚度为1～500埃的氧化铝金属氧化物保护层22、厚度为1～1000nm的氧掺杂氮化铝过渡层23及厚度为10～1000nm的氧掺杂氮化铝缓冲层24组成，本实施例优选氧掺杂氮化铝过渡层23的厚度为5~50nm，氧掺杂氮化铝缓冲层24厚度为200~300nm。而所述铝金属保护层21、氧化铝金属氧化物保护层22、氧掺杂氮化铝过渡层23、氧掺杂氮化铝缓冲层24的材料分别为铝金属、氧化铝、氧浓度≥1×1019cm-3的氧掺杂氮化铝和氧浓度≤4×1022cm-3的氧掺杂氮化铝，其中，为增加后续沉积外延层的晶体质量，此实施例优选过渡层23的氧掺杂浓度大于氧掺杂氮化铝缓冲层24的氧掺杂浓度。
因常规PVD法沉积氮化铝缓冲层时，均会掺入微量氧元素，而使用的硅衬底10容易被氧化，故当在硅衬底10表面直接沉积含微量氧元素的氮化铝缓冲层时，硅衬底10表面被氧化形成非晶态的氧化硅层，此非晶态层致使继续沉积的氮化铝缓冲层与衬底10的接触界面质量变差，容易导致裂纹的产生，破坏半导体器件的质量；同时，非晶态层使得氮化铝缓冲层致密性变差，产生空隙，其后在MOCVD法沉积含镓氮化物层时，镓元素通过空隙腐蚀硅衬底，形成坑洞，破坏半导体器件性能。而本实施例提出的多层缓冲结构多层缓冲结构20中，先利用铝铝金属保护层21覆盖硅衬底10表面，阻断硅衬底10表面与氧气直接接触，避免其被氧化；随后沉积氧化铝层22，减缓铝铝金属保护层21被后续沉积制程中氧气的氧化程度，进一步保护硅衬底10表面，避免非晶态层的形成；随后再沉积氧掺杂浓度≥1×1019cm-3的氧掺杂氮化铝过渡层23和氧掺杂浓度≤4×1022cm-3的氧掺杂氮化铝缓冲层24，氧掺杂氮化铝过渡层23有效降低氧化铝层22与氧掺杂氮化铝缓冲层24之间的晶格差异，提升氧掺杂氮化铝缓冲层24的晶格质量，进而减少后续沉积的外延层内部的晶体缺陷及位错，改善半导体元件的性能。
为实现上述结构及其作用，本发明提出一种半导体外延结构的制备方法，依次在硅衬底上形成多层缓冲结构和外延功能层，其中，所述多层缓冲层通过下面方法形成：
首先，提供一硅衬底10并置于PVD腔室中，对硅衬底10表面进行清洁，去除表面的杂质；而此步骤中用以清洁衬底10表面的方式为利用自偏压射频溅射方法在高温下H2或惰性气体中清洁表面；其中，惰性气体采用氩气、氦气或氖气中的一种，此处优选氩气进行清洁处理。
然后，利用PVD法于所述硅衬底10表面沉积铝金属保护层21；铝金属保护层21的材料为金属铝；此实施例中PVD法优选磁控溅射法。
通入氧气，使铝金属保护层21上层氧化，然后采用PVD法于铝金属保护层21表面沉积氧化铝金属氧化物保护层22；氧化铝金属氧化物保护层22的材料为氧化铝。
保持氧气持续通入，增加氮气通入，利用PVD法于氧化铝金属氧化物保护层22表面沉积氧掺杂氮化铝材料形成的氧掺杂氮化铝过渡层23，其氧浓度≥1×1019cm-3。
最后，关闭氧气，保持氮气持续通入，利用物理气相沉积法于氧掺杂氮化铝过渡层23表面沉积氧掺杂氮化铝材料形成的氧掺杂氮化铝缓冲层24，构成多层缓冲结构20；其中，所述氧掺杂氮化铝缓冲层24的氧浓度≤4×1022cm-3；
本方法形成的多层缓冲结构20晶体质量高，界面平整，使得后续生长的含镓元素发光二极管的位错及缺陷密度大大减少，减少器件漏电，增加了器件的可靠性，同时提升了整个发光半导体器件的发光效率。
实施例2
参看附图4，本实施例与实施例1的区别在于，在多层缓冲结构20表面沉积晶体管外延层作为外延功能层30，形成晶体管元件，其制备方法及结构如下：将沉积有铝金属保护层21、氧化铝金属氧化物保护层22、氧掺杂氮化铝过渡层23和氧掺杂氮化铝缓冲层24组成的多层缓冲结构20的衬底转入MOCVD腔室，利用MOCVD法沉积铝镓氮层35，进一步缓冲多层缓冲结构20的晶格应力，避免裂纹产生；随后再一层非故意掺杂或掺杂碳或掺杂铁的氮化镓半导体层36，接着再沉积铝镓氮半导体层37，该铝镓氮半导体层37通过电场极化作用在界面处产生高密度的电子气，最后再沉积氮化镓半导体覆盖层38，同时该覆盖层38也用作接触层，用以制作电极，形成最终晶体管元件。
应当理解的是，上述具体实施方案为本发明的优选实施例，本发明的范围不限于该实施例，凡依本发明所做的任何变更，皆属本发明的保护范围之内。

Claims (9)

1.一种半导体元件的制备方法，依次在一硅衬底上形成多层缓冲结构和外延功能层，其特征在于，所述多层缓冲结构通过下面方法形成：
利用物理气相沉积法于所述硅衬底表面沉积铝金属保护层；
通入氧气，使所述铝金属保护层上表面氧化，然后采用物理气相沉积法于所述铝金属保护层表面沉积氧化铝金属氧化物保护层；
保持氧气持续通入，增加氮气通入，利用物理气相沉积法于所述氧化铝金属氧化物保护层表面沉积氧掺杂氮化铝过渡层；
关闭氧气，保持氮气持续通入，利用物理气相沉积法于所述氧掺杂氮化铝过渡层表面沉积氧掺杂氮化铝缓冲层，构成多层缓冲结构。
2.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述铝金属保护层的厚度为1～100埃。
3.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧化铝金属氧化物保护层的厚度为1～500埃。
4.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧掺杂氮化铝过渡层的氧浓度≥1×1019cm-3，所述氧掺杂氮化铝过渡层厚度为1～1000nm。
5.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧掺杂氮化铝过渡层的氧浓度≥1×1019cm-3，所述氧掺杂氮化铝过渡层厚度为5~50nm。
6.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧掺杂氮化铝缓冲层的氧浓度≤4×1022cm-3，厚度为10～1000nm。
7.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧掺杂氮化铝缓冲层的氧浓度≤4×1022cm-3，厚度为200~300nm。
8.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述氧掺杂氮化铝过渡层的氧掺杂浓度大于所述氧掺杂氮化铝缓冲层的氧掺杂浓度。
9.根据权利要求1所述的一种半导体元件的制备方法，其特征在于：所述外延功能层为发光二极管外延层或晶体管外延层。
CN201510629914.9A 2015-09-29 2015-09-29 一种半导体元件及其制备方法 Active CN105336579B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510629914.9A CN105336579B (zh) 2015-09-29 2015-09-29 一种半导体元件及其制备方法
PCT/CN2016/097757 WO2017054613A1 (zh) 2015-09-29 2016-09-01 一种半导体元件及其制备方法
US15/607,505 US10158046B2 (en) 2015-09-29 2017-05-28 Semiconductor element and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510629914.9A CN105336579B (zh) 2015-09-29 2015-09-29 一种半导体元件及其制备方法

Publications (2)

Publication Number Publication Date
CN105336579A CN105336579A (zh) 2016-02-17
CN105336579B true CN105336579B (zh) 2018-07-10

Family

ID=55287027

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510629914.9A Active CN105336579B (zh) 2015-09-29 2015-09-29 一种半导体元件及其制备方法

Country Status (3)

Country Link
US (1) US10158046B2 (zh)
CN (1) CN105336579B (zh)
WO (1) WO2017054613A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336579B (zh) * 2015-09-29 2018-07-10 安徽三安光电有限公司 一种半导体元件及其制备方法
CN105762247A (zh) * 2016-03-02 2016-07-13 厦门乾照光电股份有限公司 一种具有复合结构的氮化物缓冲层制作方法
CN105609603A (zh) 2016-03-02 2016-05-25 厦门乾照光电股份有限公司 一种具有复合结构的氮化物缓冲层
CN106025026B (zh) * 2016-07-15 2018-06-19 厦门乾照光电股份有限公司 一种用于发光二极管的AlN缓冲层及其制作方法
CN108281525A (zh) * 2017-12-07 2018-07-13 上海芯元基半导体科技有限公司 一种复合衬底、半导体器件结构及其制备方法
WO2019123763A1 (ja) * 2017-12-19 2019-06-27 株式会社Sumco Ｉｉｉ族窒化物半導体基板の製造方法
CN110729385A (zh) * 2018-07-16 2020-01-24 江西兆驰半导体有限公司 一种含氧复合缓冲层结构及提高氮化镓系外延层晶体质量的方法
CN109768125A (zh) * 2018-12-29 2019-05-17 晶能光电（江西）有限公司 硅基外延片生长方法
CN113517175B (zh) * 2021-06-07 2023-02-24 西安电子科技大学 一种基于异质衬底的β-Ga2O3薄膜及其制备方法
CN116759505B (zh) * 2023-08-23 2023-11-17 江西兆驰半导体有限公司 基于硅衬底的led外延片及其制备方法、led

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1706030A (zh) * 2003-08-12 2005-12-07 日本电信电话株式会社 氮化物半导体生长用衬底
CN101515543A (zh) * 2008-02-20 2009-08-26 中国科学院半导体研究所 在硅衬底上生长的氮化镓薄膜结构及其生长方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3444208B2 (ja) * 1997-10-10 2003-09-08 豊田合成株式会社 ＧａＮ系の半導体素子
US20020084461A1 (en) * 2001-01-03 2002-07-04 Motorola, Inc. Structure and method for fabricating III-V nitride devices utilizing the formation of a compliant substrate
US20030015767A1 (en) * 2001-07-17 2003-01-23 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices with integrated control components
JP2004051446A (ja) * 2002-07-22 2004-02-19 Asahi Kasei Corp 酸化物単結晶薄膜形成方法および半導体薄膜形成方法
WO2010141994A1 (en) * 2009-06-12 2010-12-16 The Silanna Group Pty Ltd Process for producing a semiconductor-on-sapphire article
US9287351B2 (en) * 2011-06-30 2016-03-15 Kyocera Corporation Composite substrate and method for manufacturing same
DE102011114665B4 (de) * 2011-09-30 2023-09-21 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines optoelektronischen Nitrid-Verbindungshalbleiter-Bauelements
US9233844B2 (en) * 2012-06-27 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate
JP5667136B2 (ja) * 2012-09-25 2015-02-12 古河電気工業株式会社 窒化物系化合物半導体素子およびその製造方法
US8823025B1 (en) * 2013-02-20 2014-09-02 Translucent, Inc. III-N material grown on AIO/AIN buffer on Si substrate
US9356045B2 (en) * 2013-06-10 2016-05-31 Raytheon Company Semiconductor structure having column III-V isolation regions
CN105336579B (zh) * 2015-09-29 2018-07-10 安徽三安光电有限公司 一种半导体元件及其制备方法
US9773871B2 (en) * 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1706030A (zh) * 2003-08-12 2005-12-07 日本电信电话株式会社 氮化物半导体生长用衬底
CN101515543A (zh) * 2008-02-20 2009-08-26 中国科学院半导体研究所 在硅衬底上生长的氮化镓薄膜结构及其生长方法

Also Published As

Publication number Publication date
CN105336579A (zh) 2016-02-17
US20170263819A1 (en) 2017-09-14
WO2017054613A1 (zh) 2017-04-06
US10158046B2 (en) 2018-12-18

Similar Documents

Publication Publication Date Title
CN105336579B (zh) 一种半导体元件及其制备方法
US10224463B2 (en) Film forming method, method of manufacturing semiconductor light-emitting device, semiconductor light-emitting device, and illuminating device
JP5651467B2 (ja) 大領域ＳｉＣ基板の製造方法
CN102208337B (zh) 一种硅基复合衬底及其制造方法
WO2016011810A1 (zh) 一种氮化物半导体的制备方法
CN110085658B (zh) 氧化镓半导体及其制备方法
WO2007107048A1 (fr) PROCÉDÉ DE FABRICATION DE FILM MONOCRISTALLIN ZnO DE GRANDE QUALITÉ SUR SUBSTRAT DE SILICIUM (111)
WO2017161935A1 (zh) 氮化物底层、发光二极管及底层制备方法
CN112831768B (zh) 一种高结晶质量的氮化铪薄膜制备方法及应用
Yohannes et al. Growth of p-type Cu-doped GaN films with magnetron sputtering at and below 400° C
CN108899401A (zh) 基于石墨烯插入层结构的GaN基LED器件制备方法
CN104465918A (zh) 一种发光二极管外延片及其制备方法
JP2017147377A (ja) 炭化珪素半導体装置用ゲート絶縁膜の製造方法
JP2017041503A (ja) 半導体装置、および、その製造方法
TW201816204A (zh) 使用熱匹配基板的磊晶氮化鎵材料的生長
CN109671819A (zh) 一种GaN基发光二极管外延片及其制备方法
CN110729409B (zh) 一种有机光电器件封装薄膜及其制备方法
Pang et al. Growth of wurtzite and zinc-blende phased GaN on silicon (100) substrate with sputtered AlN buffer layer
KR101942749B1 (ko) 다층무기봉지박막 및 이의 제조방법
KR100945438B1 (ko) 반도체 기판과 이의 제조 방법 및 반도체 소자
CN105483617A (zh) 一种在非硅衬底上制备Mg2Si薄膜的方法
Zhang et al. Effect of AlN/GaN supercycle ratio on properties of AlxGa1− xN films using super-cycle plasma enhanced atomic layer deposition
Yang et al. In situ S-doping of cubic boron nitride thin films by plasma enhanced chemical vapor deposition
CN109301048A (zh) 一种氮化镓基发光二极管外延片及其生长方法
US20210249331A1 (en) Low-Temperature Deposition of High-Quality Aluminum Nitride Films for Heat Spreading Applications

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant