CN105304618A - 抗干扰抗腐蚀半导体集成电路的集成方法 - Google Patents

抗干扰抗腐蚀半导体集成电路的集成方法 Download PDF

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CN105304618A
CN105304618A CN201510881974.XA CN201510881974A CN105304618A CN 105304618 A CN105304618 A CN 105304618A CN 201510881974 A CN201510881974 A CN 201510881974A CN 105304618 A CN105304618 A CN 105304618A
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semiconductor integrated
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杨成刚
赵晓辉
刘学林
聂平健
杨晓琴
路兰艳
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Guizhou Zhenhua Fengguang Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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Abstract

抗干扰抗腐蚀半导体集成电路的集成方法，是将陶瓷与金属复合，用作管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体集成方法是：采用低温共烧陶瓷工艺及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、表面金属层、对外引脚等结构；在预先烧结成型的陶瓷管帽的内表面，采用涂覆金属浆料烧结方式或化学电镀方式或真空镀膜的方式形成所需管帽金属层；再进行半导体集成电路芯片的装贴、引线键合和封帽，满足电磁全频段的屏蔽和抗腐蚀的要求。用本发明方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域。

Description

抗干扰抗腐蚀半导体集成电路的集成方法
技术领域
本发明创造涉及集成电路，具体来说，涉及半导体集成电路，更进一步来说，涉及抗干扰抗腐蚀半导体集成电路。
技术背景
原有半导体集成电路的集成技术中，将半导体集成电路芯片封装在金属管基和金属管帽内，或封装在陶瓷管基和陶瓷管帽内，先将半导体集成电路芯片装贴在管基上，再采用键合丝（金丝或硅铝丝）进行芯片与管脚的引线键合，完成整个电器连接，最后将管基和管帽进行密封而成。此方法存在的主要问题是在高频或电磁干扰的环境中，金属能有效地屏蔽低频、中频和部分高频干扰的影响，当频率继续增高时，金属的屏蔽作用就会变差。相反，陶瓷对低频、中频没有屏蔽能力，但对高频有良好的屏蔽能力。因此，采用金属封装、陶瓷封装均不能满足从低频、中频到高频全频段的屏蔽要求。导致半导体集成电路在要求抗干扰的环境中使用时，需要在使用系统中增加大量的屏蔽措施，给使用造成诸多不便，不利于装备系统的小型化、集成化和轻便化。另一方面，由于采用金属外壳，抗腐蚀性差，不适用于带腐蚀性的恶劣气氛环境中。
中国专利数据库中，涉及半导体集成电路的专利以及专利申请件多达上千件，但涉及抗干扰半导体集成电路的专利仅有2012200511925号《环境因素采集系统以及半导体集成电路生产工艺测量设备》1件。迄今为止，尚无抗干扰抗腐蚀半导体集成电路集成方法的专利申请件。
发明内容
本发明旨在提供抗干扰抗腐蚀半导体集成电路的集成方法，将金属和陶瓷的特性有机地结合在一起，实现从低频到高频的电磁屏蔽，增加半导体集成电路的抗干扰能力；同时，解决抗腐蚀性问题。
为实现上述的目标，发明人将金属与陶瓷的复合材料用作封装外壳的管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体集成方法是：采用低温共烧陶瓷工艺（LTCC工艺）及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、表面金属层、对外引脚等结构；在预先烧结成型的陶瓷管帽的内表面，采用涂覆金属浆料烧结方式或化学电镀方式或真空镀膜的方式形成所需管帽金属层；再进行半导体集成电路芯片的装贴、引线键合或倒装键合，最后封帽；这样，管基和管帽外层为陶瓷材料、内层为金属材料，二者有机结合，即实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现半导体集成电路的抗干扰能力；同时，由于封装外层为陶瓷，具有很强的抗腐蚀能力，从而达到本发明的目的。
上述方法中，所述管帽金属层涂覆的金属是铬和金；所述管基金属层涂覆的金属是金。
本发明的方法具有以下优点：①从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，提升半导体集成电路的抗干扰能力；②抗腐蚀能力强；③陶瓷高温烧结成型与金属层成型的工艺兼容性；④可以实现多层布线与集成，实现高密度集成；⑤可集成更多的电路功能，实现系统集成；⑥实现表贴式安装，缩小装备体积，提升装备的高频性能；⑦提高装备系统的可靠性；⑧可扩展到其他电路模块的电磁屏蔽。
用本发明方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为原有半导体集成电路的管基示意图，图2为原有管帽示意图，图3为原有半导体集成电路组装示意图，图4为本发明的管帽结构示意图，图5为本发明的引线键合组装集成电路示意图，图6为本发明的倒装键合组装集成电路示意图。
图中，1为金属管基，2为金属底座，3为金属管脚，4为金属管帽，5为半导体集成电路芯片，6为键合丝，7为管帽陶瓷基体，8为管帽金属层，9为管基金属层，10为管基陶瓷基体，11为管基顶层陶瓷，12为封帽粘结材料，13为引脚，14为金属球焊接。
具体实施方式
实施例1：按以下工序集成本发明的引线键合组装的抗干扰抗腐蚀半导体集成电路：
（1）陶瓷管帽、陶瓷生瓷片、镀层材料的准备；
（2）在陶瓷管帽的内表面化学镀铬；
（3）在陶瓷管帽的内表面电镀金；
（4）电镀后陶瓷管帽的清洗与烘干；
（5）采用现有技术中的低温共烧陶瓷工艺（LTCC工艺）及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、内表面金属层、对外引脚等结构，金属层材料为金浆料烧结而成；
（6）在陶瓷管基底座上组装半导体集成电路芯片；
（7）用硅-铝丝或金丝键合以完成半导体集成电路芯片的电路连接；
（8）封帽，粘结材料12为低熔点玻璃浆料或低熔点陶瓷浆料固化而成；
（9）性能测试；
（10）老化筛选测试、密封性检查；
（11）产品编号打印、包装入库。
得到的引线键合组装的抗干扰抗腐蚀半导体集成电路如图5所示。
实施例2：按以下工序集成本发明的倒装键合组装抗干扰抗腐蚀半导体集成电路：
(1)陶瓷管帽、陶瓷生瓷片、镀层材料的准备；
(2)在陶瓷管帽的内表面化学镀铬；
(3)在陶瓷管帽的内表面电镀金；
(4)电镀后陶瓷管帽的清洗与烘干；
(5)采用现有技术中的低温共烧陶瓷工艺（LTCC工艺）及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、内表面金属层、对外引脚等结构，金属层材料为金浆料烧结而成；
(6)在陶瓷管基底座上组装半导体集成电路芯片；
(7)封帽，粘结材料12为低熔点玻璃浆料或低熔点陶瓷浆料固化而成；
(8)性能测试；
(9)老化筛选测试、密封性检查；
(10)产品编号打印、包装入库。
得到的倒装键合组装抗干扰抗腐蚀半导体集成电路如图6所示。

Claims (5)

1.抗干扰抗腐蚀半导体集成电路的集成方法，其特征是将陶瓷与金属复合，用作管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体集成方法是：采用低温共烧陶瓷工艺及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、表面金属层、对外引脚等结构；在预先烧结成型的陶瓷管帽的内表面，采用涂覆金属浆料烧结方式或化学电镀方式或真空镀膜的方式形成所需管帽金属层；再进行半导体集成电路芯片的装贴、引线键合和封帽；使封装内外电磁环境实现良好的隔离，以满足从低频到高频的电磁全频段的屏蔽和抗腐蚀的要求。
2.如权利要求1所述的方法，详细的集成工艺是：
陶瓷管帽、陶瓷生瓷片、镀层材料的准备；
在陶瓷管帽的内表面化学镀铬；
在陶瓷管帽的内表面电镀金；
电镀后陶瓷管帽的清洗与烘干；
采用现有技术中的低温共烧陶瓷工艺及厚膜印刷与烧结工艺制作管基底座，形成半导体集成电路芯片键合区、外表面金属层、对外引脚等结构，金属层材料为金浆料烧结而成；
在陶瓷管基底座上组装半导体集成电路芯片；
用硅-铝丝或金丝键合以完成半导体集成电路芯片的电路连接（倒装焊时不需要）；
封帽，粘结材料（12）为低熔点金属爆料再流化而成；
性能测试；
老化筛选测试、密封性检查；
产品编号打印、包装入库。
3.如权利要求1所述的方法，其特征在于所述半导体集成电路芯片的装贴为引线键合贴装。
4.如权利要求1所述的方法，其特征在于所述半导体集成电路芯片的装贴为倒装键合贴装。
5.如权利要求1所述的方法，其特征在于所述管帽金属层涂覆的金属是铬和金；所述管基金属层的金属是金。
CN201510881974.XA 2015-12-04 2015-12-04 抗干扰抗腐蚀半导体集成电路的集成方法 Pending CN105304618A (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250615A (ja) * 1995-03-13 1996-09-27 Sumitomo Kinzoku Electro Device:Kk 半導体チップ用セラミックパッケージ
US20040108588A1 (en) * 2002-09-24 2004-06-10 Cookson Electronics, Inc. Package for microchips
CN1947278A (zh) * 2004-04-22 2007-04-11 奥斯兰姆奥普托半导体有限责任公司 用于有机电子元件的封装及其制造方法和用途
CN104465607A (zh) * 2014-12-15 2015-03-25 贵州振华风光半导体有限公司 无引线平面表贴式微波薄膜混合集成电路及其集成方法
CN104485324A (zh) * 2014-12-15 2015-04-01 贵州振华风光半导体有限公司 无引线球脚表贴式微波薄膜混合集成电路及其集成方法

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