CN105226016B - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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CN105226016B
CN105226016B CN201510663063.XA CN201510663063A CN105226016B CN 105226016 B CN105226016 B CN 105226016B CN 201510663063 A CN201510663063 A CN 201510663063A CN 105226016 B CN105226016 B CN 105226016B
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substrate
pattern
gate
thin film
ito thin
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CN105226016A (zh
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林亮
杨成绍
姜涛
邹志翔
黄寅虎
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to CN201510663063.XA priority Critical patent/CN105226016B/zh
Publication of CN105226016A publication Critical patent/CN105226016A/zh
Priority to PCT/CN2016/099318 priority patent/WO2017063476A1/zh
Priority to US15/528,963 priority patent/US20170261820A1/en
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract

本发明公开了一种阵列基板及其制作方法，属于液晶显示器领域。所述方法包括：在基板上溅射一层氧化铟锡ITO薄膜；对所述基板进行退火处理；在所述ITO薄膜上形成一层栅极金属薄膜；对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案。在本发明实施例中，在ITO薄膜溅射完成后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和Gate交界面形成鼓包，提高ADS产品的良率。

Description

阵列基板及其制作方法
技术领域
本发明涉及LCD(Liquid Crystal Display，液晶显示器)领域，特别涉及一种阵列基板及其制作方法。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)LCD因其性能优良、大规模生产特性好、发展空间广阔等优点，成为目前显示器领域的主流产品。TFT LCD按照显示模式可以分为：扭曲向列(TN，Twisted Nematic)型、平面转换(IPS，In Plane Switching)型和高级超维场开关(ADS，Advanced Super Dimension Switch)型。
ADS型LCD的阵列基板包括基板、依次形成在基板上的公共电极、栅极、半导体层、源漏极、钝化层及像素电极。为了减少上述阵列基板的制作工艺，现有一种4次掩模(4MASK)制作工艺，具体如下：第一步，在基板上形成公共电极(1st ITO)和栅极(Gate)；第二步，在基板上形成半导体层和源漏极(S D)；第三步，在基板上形成钝化层并制作过孔(ViaHole)；第四步，在基板上形成像素电极(2nd ITO)。其中，4次MASK分别为：第一步中的ITOGate Mask，第二步中S D Mask，第三步中过Via Hole Mask和第四步中ITO Mask。
采用上述工艺制成的ADS型LCD的阵列基板，存在以下问题：公共电极ITO中会存在水汽残留，水汽残留一部分是为了防止公共电极ITO成膜时晶化，在进行ITO溅射时加入的水，另一部分是ITO成膜后从空气中吸收的水，水汽残留使得ITO和Gate交界面形成鼓包，这些鼓包在公共电极和栅极制备完成后的高温真空工艺中发生破裂，导致数据线栅极短路，严重影响ADS产品的良率。
发明内容
为了解决现有技术的问题，本发明实施例提供了一种阵列基板及其制作方法。所述技术方案如下：
第一方面，本发明实施例提供了一种阵列基板制作方法，所述方法包括：
在基板上溅射一层氧化铟锡ITO薄膜；
对所述基板进行退火处理，所述退火处理的温度为120至160摄氏度；
在所述ITO薄膜上形成一层栅极金属薄膜；
对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
在本发明实施例的另一种实现方式中，所述退火处理的温度为140摄氏度。
在本发明实施例的另一种实现方式中，所述退火处理的时间为30分钟。
在本发明实施例的另一种实现方式中，所述退火处理的气氛为氮气。
在本发明实施例的另一种实现方式中，所述对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案，包括：
采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案。
在本发明实施例的另一种实现方式中，所述采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，包括：
在所述基板上涂布光刻胶；
采用灰阶掩膜板对所述光刻胶进行曝光，得到光刻胶图案，所述光刻胶图案包括第一部分和第二部分，所述第一部分的厚度小于所述第二部分的厚度；
对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案。
在本发明实施例的另一种实现方式中，所述对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案，包括：
对所述基板进行第一次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜和所述ITO薄膜进行刻蚀，得到所述公共电极图案；
采用光刻胶灰化工艺，除去所述光刻胶图案中所述第一部分的光刻胶；
对所述基板进行第二次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜进行刻蚀，得到所述栅极图案；
除去剩余光刻胶。
在本发明实施例的另一种实现方式中，所述采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，还包括：
对形成有所述光刻胶图案的所述基板进行刻蚀后，对所述基板进行退火。
在本发明实施例的另一种实现方式中，所述方法还包括：
在形成有所述公共电极图案和所述栅极图案的所述基板上形成半导体层和源漏极；
在形成有所述半导体层和所述源漏极的所述基板上形成钝化层并制作过孔；
在形成有所述钝化层及所述过孔的所述基板上形成像素电极。
第二方面，本发明实施例还提供了一种阵列基板，所述阵列基板利用第一方面所述的方法制作而成。
本发明实施例提供的技术方案带来的有益效果是：
在本发明实施例中，在ITO薄膜溅射完成后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和Gate交界面形成鼓包，提高ADS产品的良率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种阵列基板制作方法的流程图；
图2是本发明实施例提供的另一种阵列基板制作方法的流程图；
图2a是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2b是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2c是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2d是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2e是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2f是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2g是本发明实施例提供的阵列基板制作过程中的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图1是本发明实施例提供的一种阵列基板制作方法的流程图，参见图1，该方法包括：
步骤101：在基板上溅射一层氧化铟锡(Indium Tin Oxide，ITO)薄膜。
步骤102：对基板进行退火处理。
步骤103：在ITO薄膜上形成一层栅极金属薄膜。
步骤104：对ITO薄膜和栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
其中，公共电极图案和栅极图案可以采用一次构图工艺处理ITO薄膜和栅极金属薄膜得到，具体见后文详细描述。公共电极图案和栅极图案也可以不采用一次构图工艺(如两次构图工艺)处理ITO薄膜和栅极金属薄膜得到，本发明对此不做赘述。
在本发明实施例中，在ITO薄膜溅射完成后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和Gate交界面形成鼓包，提高ADS产品的良率。
图2是本发明实施例提供的另一种阵列基板制作方法的流程图，参见图2，该方法包括：
步骤201：在基板上溅射一层ITO薄膜。
如图2a所示，在基板20上溅射一层ITO薄膜210。
步骤202：对基板进行退火处理。
其中，退火处理的温度为120至160摄氏度。本实施例选用的退火温度为120至160摄氏度，既不会因为温度太低导致水汽释放不充分，又不会因为温度太高导致ITO薄膜210晶化，影响后续刻蚀。
优选地，退火处理的温度为140摄氏度，使得水汽释放充分程度和晶化程度平衡。
其中，退火处理的时间为30分钟。本实施例选用的退火温度为30分钟，既不会因为时间太短导致水汽释放不充分，又不会因为时间太长导致栅极金属晶化，影响后续刻蚀。
其中，退火处理的气氛为氮气。当然，在本实施例中除了采用氮气作为退火气氛外，还可以选择其他常见退火气氛。
步骤203：在ITO薄膜上形成一层栅极金属薄膜。
具体地，可以采用溅射工艺在ITO薄膜上形成一层栅极金属薄膜。
如图2b所示，在形成有ITO薄膜210的基板20上形成栅极金属薄膜220。
步骤204：采用灰阶掩膜刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案。
本实施例采用灰阶掩膜刻蚀工艺实现一次构图工艺得到公共电极图案和栅极图案，节省制作步骤。
具体地，采用灰阶掩膜刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案，包括：
步骤一，在基板上涂布光刻胶；如图2c所示，在形成有ITO薄膜210及栅极金属薄膜220的基板20上涂布光刻胶230。
步骤二，采用灰阶掩膜板对光刻胶进行曝光，得到光刻胶图案，光刻胶图案包括第一部分和第二部分，第一部分的厚度小于第二部分的厚度；如图2d所示，光刻胶图案包括第一部分231和第二部分232。
步骤三，对形成有光刻胶图案的基板进行刻蚀，得到公共电极图案和栅极图案。
其中，步骤三可以参见图2e-2g，具体包括：
对基板20进行第一次刻蚀工艺，对未覆盖光刻胶的栅极金属薄膜210和ITO薄膜220进行刻蚀，得到公共电极图案21，如图2e所示；采用光刻胶灰化工艺，除去光刻胶图案中第一部分231的光刻胶；对基板20进行第二次刻蚀工艺，对未覆盖光刻胶的栅极金属薄膜220进行刻蚀，得到栅极图案22，如图2f所述；除去剩余光刻胶(第二部分232)，如图2g所示。
进一步地，采用灰阶掩膜刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案，还包括：
对形成有光刻胶图案的基板进行刻蚀后，对基板进行退火。
步骤205：在形成有公共电极图案和栅极图案的基板上形成半导体层和源漏极。
具体地，步骤205可以采用一次构图工艺形成半导体层和源漏极。步骤205也可以先通过构图工艺形成半导体层，再通过构图工艺形成源漏极。其中，源漏极包括源电极和漏电极。
步骤206：在形成有半导体层和源漏极的基板上形成钝化层并制作过孔。
其中，过孔形成于钝化层上并使源漏极中的漏电极暴露出来。
步骤207：在形成有钝化层及过孔的基板上形成像素电极。
其中，像素电极与漏电极相连接。
其中，步骤205至步骤207可以采用现有ADS型TFT LCD阵列基板中制作工艺实现。
在本发明实施例中，在ITO薄膜溅射完成后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和Gate交界面形成鼓包，提高ADS产品的良率。
本发明实施例还提供了一种阵列基板，该阵列基板利用图1或者图2对应的方法制作而成。
在该阵列基板制作过程中，在ITO薄膜溅射完成后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和Gate交界面形成鼓包，提高ADS产品的良率。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种阵列基板制作方法，其特征在于，所述方法包括：
在基板上溅射一层氧化铟锡ITO薄膜；
对所述基板进行退火处理，所述退火处理的温度为120至160摄氏度；
在所述ITO薄膜上形成一层栅极金属薄膜；
对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
2.根据权利要求1所述的方法，其特征在于，所述退火处理的温度为140摄氏度。
3.根据权利要求1所述的方法，其特征在于，所述退火处理的时间为30分钟。
4.根据权利要求1所述的方法，其特征在于，所述退火处理的气氛为氮气。
5.根据权利要求1所述的方法，其特征在于，所述对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案，包括：
采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案。
6.根据权利要求5所述的方法，其特征在于，所述采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，包括：
在所述基板上涂布光刻胶；
采用灰阶掩膜板对所述光刻胶进行曝光，得到光刻胶图案，所述光刻胶图案包括第一部分和第二部分，所述第一部分的厚度小于所述第二部分的厚度；
对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案。
7.根据权利要求6所述的方法，其特征在于，所述对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案，包括：
对所述基板进行第一次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜和所述ITO薄膜进行刻蚀，得到所述公共电极图案；
采用光刻胶灰化工艺，除去所述光刻胶图案中所述第一部分的光刻胶；
对所述基板进行第二次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜进行刻蚀，得到所述栅极图案；
除去剩余光刻胶。
8.根据权利要求6所述的方法，其特征在于，所述采用灰阶掩膜刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，还包括：
对形成有所述光刻胶图案的所述基板进行刻蚀后，对所述基板进行退火。
9.根据权利要求1所述的方法，其特征在于，所述方法还包括：
在形成有所述公共电极图案和所述栅极图案的所述基板上形成半导体层和源漏极；
在形成有所述半导体层和所述源漏极的所述基板上形成钝化层并制作过孔；
在形成有所述钝化层及所述过孔的所述基板上形成像素电极。
10.一种阵列基板，其特征在于，所述阵列基板利用权利要求1-9所述的方法制作而成。
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CN103441129A (zh) * 2013-08-23 2013-12-11 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN103887285B (zh) * 2014-03-18 2017-05-24 江西沃格光电股份有限公司 防静电tft基板的制备方法
CN105226016B (zh) * 2015-10-14 2018-11-23 京东方科技集团股份有限公司 阵列基板及其制作方法

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