CN105223744A - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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CN105223744A
CN105223744A CN201510719680.7A CN201510719680A CN105223744A CN 105223744 A CN105223744 A CN 105223744A CN 201510719680 A CN201510719680 A CN 201510719680A CN 105223744 A CN105223744 A CN 105223744A
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CN105223744B (zh
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严允晟
林允植
崔贤植
李会
田正牧
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BOE Technology Group Co Ltd
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Abstract

本发明提供了一种阵列基板及其制作方法、显示装置，该阵列基板包括：衬板和形成在所述衬板上的电极图形；所述电极图形包括多个条状电极；所述衬板的上表面具有多个条状凸起，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，所述夹角适于使配向膜摩擦方向沿各个条状凸起的延伸方向。本发明提供的阵列基板，在进行配向膜的摩擦时，可以顺着条状凸起的延伸方向进行，从而避免条状凸起处的段差对摩擦得到的夹角的影响，避免由此导致的漏光现象。

Description

阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
在液晶显示技术中，高级超维场转换技术(ADvancedSuperDimensionSwitch，ADS)模式以透过率高、宽视角、响应速度快和功耗低的优点逐渐取代扭曲向列相技术(TwistedNematic，TN)液晶模式，成为液晶显示领域的重要技术之一。
参见图1，为现有技术中的一种常见的ADS显示装置的阵列基板的结构示意图，包括衬板100以及形成在衬板100上方的条状的像素电极210和公共电极220，该衬板100的上表面形成有多个条状凸起，为了方面理解，图1衬板100的条状凸起和除条状凸起之外的其他部分采用不同的图案进行表示；各个条状电极210和220对应的位于各个条状凸起的上方，延伸方向与条状凸起的延伸方向相同。一般的，为了保证能够正常的显示，需要配向膜中的擦痕与条状电极200的延伸方向呈特定的夹角α。参见图1，对于这样的阵列基板，在进行摩擦时，就需要摩擦的方向与条状电极210和220呈特定的夹角α，即需要与条状凸起呈特定的夹角。但是在实际应用中由于段差的原因，在条状凸起的位置对配向膜摩擦的摩擦不够充分，导致在该位置处得到的擦痕与条状电极的延伸方向的夹角不符合要求，这样会导致漏光。
发明内容
本发明的一个目的解决上述技术问题。
第一方面，本发明提供了一种阵列基板，包括：衬板和形成在所述衬板上的电极图形；所述电极图形包括多个条状电极；
所述衬板的上表面具有多个条状凸起，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，所述夹角适于使配向膜摩擦方向沿各个条状凸起的延伸方向。
进一步，所述电极图形包括公共电极图形和/或像素电极图形。
进一步，所述衬板包括基底、形成在基底上方的薄膜晶体管阵列以及形成在薄膜晶体管阵列上方的钝化层；
所述钝化层的上表面具有多个条状凸起。
进一步，所述薄膜晶体管阵列包括栅绝缘层；
所述条状凸起包括钝化层和栅绝缘层。
进一步，所述夹角小于10.5°大于9.5°。
进一步，还包括：形成在衬板以及电极图形上方的配向膜，所述配向膜为对配向膜材料沿各个条状凸起的延伸方向摩擦得到的。
第二方面，本发明提供了一种阵列基板的制作方法，包括：
提供上表面具有多个条状凸起的衬板；
在衬板上对应形成电极图形；所述电极图形包括多个条状电极，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起具有预设夹角，所述夹角适于使对配向膜的摩擦方向沿各个条状凸起的延伸方向。
进一步，所述电极图形包括公共电极图形和/或像素电极图形。
进一步，所述夹角小于10.5°大于9.5°。
进一步，所述方法还包括：
在所述衬板和所述电极图形上方形成配向膜材料；
对配向膜材料沿各个条状凸起的延伸方向进行摩擦得到配向膜。
第三方面，本发明提供了一种显示装置，包括上述任一项所述的阵列基板。
本发明提供的各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，且夹角适于使对配向膜的摩擦方向沿各个条状凸起的延伸方向。这样在进行摩擦时，就可以顺着条状凸起的延伸方向进行，从而避免条状凸起处的段差对摩擦得到的夹角的影响，避免由此导致的漏光现象。
附图说明
图1为现有技术中的阵列基板的结构示意图；
图2为本发明实施例一提供的一种阵列基板的结构示意图；
图3为本发明实施例二提供的一种阵列基板的结构示意图；
图4为本发明实施例三提供的一种阵列基板的结构示意图；
图5为本发明实施例四提供的一种阵列基板的结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
第一方面，本发明提供了一种阵列基板，包括：衬板和形成在所述衬板上的电极图形；所述电极图形包括多个条状电极；
所述衬板的上表面具有多个条状凸起，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，所述夹角适于使配向膜摩擦方向沿各个条状凸起的延伸方向。
本发明提供的各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，且夹角适于使配向膜摩擦方向沿各个条状凸起的延伸方向。这样在进行摩擦时，就可以顺着条状凸起的延伸方向进行，从而消除段差对相应位置处摩擦得到的夹角的影响，避免由此导致的漏光现象。
第二方面，本发明还提供了一种阵列基板的制作方法，包括：
提供上表面具有多个条状凸起的衬板；
在衬板上对应形成电极图形；所述电极图形包括多个条状电极，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起具有预设夹角，所述夹角适于使对配向膜的摩擦方向沿各个条状凸起的延伸方向。
在具体实施时，上述的阵列基板的具体结构可以表现为多种不同的形式，相应的制作方法也可能不尽相同，下面结合附图进行具体说明。
实施例一
本发明实施例一提供的阵列基板的结构示意图可以参考图2，包括：衬板100和形成在衬板上的像素电极210和公共电极220；其中在衬板100的上表面具有多个条状凸起，各个像素电极210和公共电极220也均为条状，且均一对一制作在一个条状凸起的上方。像素电极210和公共电极220间隔排布；且各个条状电极210或220的宽度均大于相应的条状凸起的宽度。
参见图2，条状的像素电极210以及公共电极220的延伸方向与条状凸起的延伸方向均呈预设的夹角α，该夹角α能够使得对配向膜的摩擦方向沿各个条状凸起的延伸方向。也即是，通过使条状的像素电极210以及公共电极220的延伸方向与条状凸起的延伸方向均呈预设的夹角α，能够在顺着凸起的延伸方向对配向膜进行摩擦的情况下使得对配向膜摩擦得到的擦痕与像素电极210和公共电极220的夹角能够使得相应的显示装置进行正常的显示。这样在进行摩擦时，就可以顺着条状凸起的延伸方向对配向膜进行摩擦，避免段差对摩擦的影响，进而避免漏光现象。
在具体实施时，这里的夹角α的值可以小于10.5°大于9.5°。在这个范围内，能够使得相应的显示装置的漏光程度最轻。
在具体实施时，这里的衬板100何以具体包括基底以及形成在基底上方的薄膜晶体管阵列、形成在薄膜晶体管阵列上方的钝化层(图中未示出具体结构)；此时这里的钝化层构成衬板的最上层，且钝化层的上表面具有多个条状凸起。
在具体实施时，上述的薄膜晶体管阵列包括栅绝缘层，此时上述的条状凸起可以具体包括钝化层和栅绝缘层；其中钝化层可以位于栅绝缘层的上方，栅绝缘层的上表面具有条状凸起，从而导致位于栅绝缘层的上表面上的钝化层的上表面也具有条状凸起。在实际应用中，这里的条状凸起也可以仅由钝化层构成，此时位于其下方的绝缘层并不构成凸起。当条状凸起包括栅绝缘层时，条状凸起的整体厚度可以在0.6-1.0μm；当仅包含钝化层时，条状凸起的整体厚度可以在0.2-0.6μm之间。
在具体实施时，上述的阵列基板还可以包括：形成在衬板以及电极图形上方的配向膜(图中未示出)，所述配向膜为对配向膜材料沿各个条状凸起的延伸方向摩擦得到的。
对于实施例一的阵列基板的制作方法可以包括：
步骤S1，提供上表面具有多个条状凸起的衬板；
具体来说，可以在基底上形成薄膜晶体管阵列以及钝化层，由于在薄膜晶体管阵列中的栅极、源极、漏极、有源层以及连接源极的数据线、连接栅极的栅线等结构呈图案化分布，在形成钝化层之前得到的结构的上表面高低不平，其中会形成一些条状凸起，在这样的结构之上沉积钝化层材料得到的钝化层的上表面自然也会包括多个条状凸起；
步骤S2，在衬板上对应形成电极图形；该电极图形包括像素电极图形和公共电极图形；其中，像素电极图形和公共电极图形均包括多个条状电极，且每一个条状电极对应形成在一个条状凸起上；各个条状电极的延伸方向与各个条状凸起具有预设夹角，所述夹角适于使对配向膜的摩擦方向沿各个条状凸起的延伸方向。
在具体实施时，上述的步骤S2可以具体包括：在衬板上沉积电极材料层，并对电极材料层进行一次图案化得到公共电极图形和像素电极图形。这样可以减少图案化工艺的次数，降低制作难度。
在步骤S2之后，上述的方法还可以包括：
在衬板和电极图形之上配向膜材料；
对配向膜材料沿各个条状凸起的延伸方向进行摩擦得到配向膜。
这样可以使得上述的摩擦过程不受段差的影响。
实施例二
参见图3，与实施一不同的是，本发明实施例二提供的阵列基板中，其中的各个条状电极210和220的宽度均小于条状凸起的宽度。
图3中的阵列基板同样能够达到本发明所要达到的基本目的。另外，各个条状电极的宽度等于条状凸起的宽度时，相应的技术方案同样能够达到本发明所要达到的基本目的。因此，条状电极210和220的宽度与条状凸起的宽度的大小关系并不会影响本发明的实施。
对实施例二的阵列基板的制作方法可以参考对实施例一的阵列基板的制作过程，在此不再详细说明。
实施例三
参见图4，与实施一不同的是，本发明实施例三提供的阵列基板中，仅有像素电极210一对一形成在应一个条状凸起的上方，公共电极220没有形成在条状凸起的上方，且公共电极220的宽度小于条状凸起的宽度。
这样的设置除了能够达到本发明的基本目的之外，能够使得相应的显示装置具有更好的响应速度。
不难理解的是，在实际应用中，也可以将公共电极220制作在条状凸起的上方，而像素电极210不制作在条状凸起的上方。
对实施例三的阵列基板的制作方法可以参考对实施例一的阵列基板的制作过程，在此不再详细说明。
实施例四
参见图5，与实施例三不同的是，本发明实施例四提供的阵列基板中，像素电极210和公共电极220的宽度均小于条状凸起的宽度。
实施例四提供的阵列基板同样能够达到本发明所要达到的基本目的。相应的制作方法可以参考对实施例一的阵列基板的制作过程，在此不再详细说明。
另外，经过仿真模拟发现，本发明提供的阵列基板相对于常规的阵列基板中的IPS模式的阵列基板，像素电极和公共电极之间的电容的容值大幅提升，就无需再制作用于存储像素电极的电压的存储电容Cst；比如对于46寸的IPS模式的阵列基板中，像素电极和公共电极之间的电容的容值大概为0.05pF，而本发明提供的阵列基板中，像素电极和公共电极之间的电容的容值大概为0.1-0.3pF，电容值大幅提升，这样就无需额外的制作存储电容Cst，可以降低设计和制作难度。另外，如果还制作存储电容Cst，则可以缩小像素电极和公共电极之间的电容值的大小，这样就可以缩小像素电极和公共电极所需占用的空间，也能够降低设计和制作难度。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

1.一种阵列基板，其特征在于，包括：衬板和形成在所述衬板上的电极图形；所述电极图形包括多个条状电极；
所述衬板的上表面具有多个条状凸起，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起的延伸方向具有夹角，所述夹角适于使配向膜摩擦方向沿各个条状凸起的延伸方向。
2.如权利要求1所述的阵列基板，其特征在于，所述电极图形包括公共电极图形和/或像素电极图形。
3.如权利要求1的阵列基板，其特征在于，
所述衬板包括基底、形成在基底上方的薄膜晶体管阵列以及形成在薄膜晶体管阵列上方的钝化层；
所述钝化层的上表面具有多个条状凸起。
4.如权利要求3所述的阵列基板，其特征在于，所述薄膜晶体管阵列包括栅绝缘层；
所述条状凸起包括钝化层和栅绝缘层。
5.如权利要求1所述的阵列基板，其特征在于，所述夹角小于10.5°大于9.5°。
6.如权利要求1所述的阵列基板，其特征在于，还包括：形成在衬板以及电极图形上方的配向膜，所述配向膜为对配向膜材料沿各个条状凸起的延伸方向摩擦得到的。
7.一种阵列基板的制作方法，其特征在于，包括：
提供上表面具有多个条状凸起的衬板；
在衬板上对应形成电极图形；所述电极图形包括多个条状电极，所述多个条状电极中的至少一部分条状电极对应形成在各个条状凸起上；各个条状电极的延伸方向与各个条状凸起具有预设夹角，所述夹角适于使对配向膜的摩擦方向沿各个条状凸起的延伸方向。
8.如权利要求7所述的方法，其特征在于，所述电极图形包括公共电极图形和/或像素电极图形。
9.如权利要求7所述的方法，其特征在于，所述夹角小于10.5°大于9.5°。
10.如权利要求7所述的方法，其特征在于，还包括：
在所述衬板和所述电极图形上方形成配向膜材料；
对配向膜材料沿各个条状凸起的延伸方向进行摩擦得到配向膜。
11.一种显示装置，其特征在于，包括如权利要求1-6任一项所述的阵列基板。
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