CN105185738B - A kind of semiconductor devices and preparation method, electronic device - Google Patents
A kind of semiconductor devices and preparation method, electronic device Download PDFInfo
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- CN105185738B CN105185738B CN201410279762.XA CN201410279762A CN105185738B CN 105185738 B CN105185738 B CN 105185738B CN 201410279762 A CN201410279762 A CN 201410279762A CN 105185738 B CN105185738 B CN 105185738B
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Abstract
The present invention provides a kind of semiconductor devices and preparation method, electronic devices to be formed with cmos device and the interconnection layer on the cmos device on the substrate the method includes providing substrate；The dielectric layer with cavity is formed on the substrate, and the cavity is located at the top of the interconnection layer, to define the shape of through-hole；MEMS layer is formed on the dielectric layer, to cover the dielectric layer；The MEMS layer is patterned, to form via openings above the cavity, exposes the cavity and the interconnection layer；Conductive material is filled in the cavity and the via openings, to form through-hole, to connect the cmos device and the MEMS layer.The present invention is before forming MEMS layer, cavity or sacrificial material layer are formed in the CMOS metal upperside interconnection layer, to replace the dielectric layer to be removed, the dielectric layer is etched under the depth of 10um so as to avoid after patterning MEMS layer, it is not only simple and practicable relative to existing method, but also improve the performance of device.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation method, electronics
Device.
Background technology
With the continuous development of semiconductor technology, integrated CMOS and MEMS (MEMS) device have become most advanced
Technology, wherein embedded with MEMS cmos device due to better performance and lower cost, becoming the master of integrated CMOS
Want trend.
Wherein, there are many methods in integratecCMOS devices to realize the connection of cmos device and MEMS device, such as total
Crystalline substance engagement (eutectic bonding) or interior bone (internal via) etc..
Eutectic bonding (eutectic bonding) technology will produce high contact resistance and high electricity for circuit connection
Source resistance, to increase device operating lag and power loss.
And for usually having the thicker MEMS layer being made of Si, SiGe, polysilicon (Poly) or other materials
MEMS device, it is necessary to realize the connection using the through-hole (high aspect ratio via) of high-aspect-ratio.
Deep reaction ion etching (DRIE) is usually selected for the MEMS device with thicker MEMS material layer at present
Method forms the through-hole of the high-aspect-ratio, but in this process, more than 10um depth and the smaller feelings of opening
Under condition, removing the dielectric layer in cmos device above metal wire will become extremely difficult, even not possible with.
Therefore, it is necessary to the preparation methods to current semiconductor devices to be improved further, to eliminate the above problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention in order to overcome the problems, such as presently, there are, provide a kind of preparation method of semiconductor devices, including：
Substrate is provided, is formed with cmos device and the interconnection layer on the cmos device on the substrate；
The dielectric layer with cavity is formed on the substrate, and the cavity is located at the top of the interconnection layer, with definition
The shape of through-hole；
MEMS layer is formed on the dielectric layer, to cover the dielectric layer；
The MEMS layer is patterned, to form via openings above the cavity, exposes the cavity and the interconnection
Layer；
Conductive material is filled in the cavity and the via openings, to form through-hole, to connect the cmos device
With the MEMS layer.
Optionally, the method still further comprises following steps：
Before forming the MEMS layer, sacrificial material layer is filled in the cavity, to define the shape of through-hole；
And after forming the opening, the sacrificial material layer is removed, to expose the interconnection layer.
Optionally, the sacrificial material layer includes amorphous carbon.
Optionally, ashing method is selected to remove the sacrificial material layer.
Optionally, it is still further comprised before filling the conductive material：
Depositing insulating layer, to cover the MEMS layer and the interconnection layer；
The insulating layer for removing the upperside interconnection layer, to expose the interconnection layer.
Optionally, optionally blanket etching method removes the insulating layer of the upperside interconnection layer.
Optionally, the insulating layer selects stearic acid tetraethoxysilane.
Optionally, the MEMS layer selects Si, epi polysilicon or SiGe, and the method for selecting deep reaction ion etching
The MEMS layer is etched, the via openings are formed, to obtain the through-hole with high-aspect-ratio.
Optionally, if the interconnection layer includes spaced stem portion.
Optionally, the interconnection layer includes metal Al；
The dielectric layer includes oxide；
The conductive material includes W, polysilicon, SiGe or Cu.
The present invention also provides a kind of semiconductor devices that above-mentioned method is prepared.
The present invention also provides a kind of electronic devices, including the semiconductor devices that the above method is prepared.
The present invention is in order to solve the problems, such as that the semiconductor devices preparation process dielectric layer is difficult to etch, to the preparation
Technique is improved, and before forming MEMS layer, cavity or expendable material are formed in the CMOS metal upperside interconnection layer
Layer, to replace the dielectric layer to be removed, is given an account of so as to avoid being etched under the depth of 10um after patterning MEMS layer
Electric layer.The wherein described sacrificial material layer selects the material easily removed, such as amorphous carbon etc..The method system through the invention
Standby obtained through-hole has high-aspect-ratio, not only simple and practicable relative to existing method, but also improves the performance of device and good
Rate.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the preparation process schematic diagram of semiconductor devices described in the prior art；
Fig. 2 a-2g are the preparation process schematic diagram of semiconductor devices described in the embodiment of the invention；
Fig. 3 is the preparation technology flow chart of semiconductor devices described in the embodiment of the invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
Mostly through-hole is selected to be attached in the current integratecCMOS devices, wherein selecting the work that through-hole 10 is attached
Skill as shown in Figure 1, providing substrate 101, various cmos devices are formed in the substrate 101 and being located at the CMOS devices first
Then metal interconnecting layer 102 above part forms dielectric layer 103, MEMS layer 104, patterns the dielectric layer 103, MEMS layer
104 form the through-hole pattern with high-aspect-ratio, but since the MEMS layer 104 has larger thickness, relatively deep
Through-hole pattern described in the removal of dielectric layer 103 become very difficult, or even can not achieve.
In order to solve the problems, such as semiconductor devices preparation process described in the prior art in the present invention, one is provided
The new semiconductor devices preparation method of kind, the method includes：
Substrate is provided, is formed with cmos device and the interconnection layer on the cmos device on the substrate；
The dielectric layer with cavity is formed on the substrate, and the cavity is located at the top of the interconnection layer, with definition
The shape of through-hole；
MEMS layer is formed on the dielectric layer, to cover the dielectric layer；
The MEMS layer is patterned, to form via openings above the cavity, exposes the cavity and the interconnection
Layer；
Conductive material is filled in the cavity and the via openings, to form through-hole, to connect the cmos device
With the MEMS layer.
Optionally, sacrificial material layer can also be further filled in the cavity, separately below in embodiment 1 and embodiment
Described two situations are described in detail in 2.
Embodiment 1
Below in conjunction with the accompanying drawings 2a-2g to the present invention one specifically embodiment be further described.
First, step 201 is executed, substrate 201 is provided first, cmos device is formed in the substrate 201.
Specifically, with reference to Fig. 2 a, the substrate 201 includes semiconductor substrate, and is formed over the substrate various
Active device, wherein the semiconductor substrate can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Various active devices are formed on the semiconductor substrate, such as form cmos device on the semiconductor substrate
And other active devices, the active device are not limited to a certain kind.
Then step 202 is executed, forms interconnection layer 202 in the substrate 201.
Specifically, the interconnection layer 202 selects metal contact wires, is used for the cmos device and MEMS shapes in the substrate
At electrical connection, optionally, the interconnection layer 202 includes several mutually isolated part, wherein several parts pass through dielectric
Layer is mutually isolated.
The method of formation interconnection layer 202 is on the substrate：Depositing first dielectric layer on the substrate, then in institute
It states and forms patterned photoresist layer on the first dielectric layer, the pattern of opening is formed on the photoresist layer, then with described
Photoresist layer is mask patterning first dielectric layer, to form multiple openings in first dielectric layer.
Then metal material is filled in said opening, and to form metal layer, the metal layer is located at intermediate part can
Using the electrode as MEMS device, such as motion sensor or the bottom electrode of inertial sensor, it is located at the gold of both sides
Belong to layer as interconnection layer 202, is electrically connected for forming the cmos device of the MEMS device and bottom.
Wherein, the metal material can be with aluminium, copper, gold, silver, tungsten and other similar materials.
Then step 203 is executed, forms the dielectric layer 203 with cavity in the substrate 201, the cavity is located at institute
State the top of interconnection layer 202.
Specifically, the dielectric layer 203 on the interconnection layer 202, it is described that there is dielectric layer 203 can use such as oxygen
Compound, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..Alternatively, can also use in carbon fluorine
The film etc. of SiCN films is formd in compound (CF).The dielectric layer 203 selects SiO in this embodiment2。
Then the dielectric layer 203 is patterned, to form cavity, for defining the shape that form through-hole.
Dry etching dielectric layer 203 can be selected in this step, and CF can be selected in the dry etching4、CHF3,
In addition N is added2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow be CF410-200sccm, CHF310-
200sccm, N2Or CO2Or O210-400sccm, the etching pressure be 30-150mTorr, etching period 5-120s, preferably
For 5-60s, more preferably 5-30s.
Then sacrificial material layer 204 form through-hole pattern, obtain figure as shown in Figure 2 a to fill the cavity
Case, wherein the sacrificial material layer selects the material easily removed in subsequent step, such as the sacrificial material layer include but
It is not limited to amorphous carbon.The wherein described amorphous carbon can be removed by ashing method, be lost without dry method or wet method
The problem of carving, being not easy removal to avoid the dielectric layer described in the groove of high-aspect-ratio in the prior art.
Step 204 is executed, MEMS layer 205 is formed on the dielectric layer 203, to cover the dielectric layer 203.
Specifically, as shown in Figure 2 b, in this step, the MEMS layer 205 selects Si, epi polysilicon or SiGe,
But it is not limited to cited material.
Optionally, various MEMS components, such as the customary components of various sensors can be formed in the MEMS layer 205
Deng details are not described herein.
Step 205 is executed, the MEMS layer 205 is patterned, to form via openings in the top of the cavity, exposes institute
State sacrificial material layer and the interconnection layer 202.
Specifically, as shown in Figure 2 c, the method for selecting deep reaction ion etching in this step etches the MEMS layer, shape
At the via openings, to obtain the through-hole with high-aspect-ratio.
Specifically, formed on the MEMS layer 205 organic distribution layer (Organic distribution layer,
ODL), siliceous bottom antireflective coating (Si-BARC) is deposited on the siliceous bottom antireflective coating (Si-BARC)
The photoresist layer patterned, wherein pattern definition on the photoresist figure for the opening of being formed, then with described
Photoresist layer is that mask layer etches organic distribution layer, bottom antireflective coating, the MEMS layer 205, forms the through-hole
Opening.
The via openings are located at the top of the sacrificial material layer, expose the sacrificial material layer 204, optionally, choosing
The MEMS layer 205 is etched with deep reaction ion etching (DRIE) method, in the deep reaction ion etching (DRIE) step
It selects gas hexa-fluoride (SF6) to be used as process gas, applies radio-frequency power supply so that hexa-fluoride reaction gas forms high electricity
From it is 20mTorr-8Torr to control operating pressure in the etching step, and frequency power is 600W, and 13.5MHz, Dc bias can
With the continuous control in -500V-1000V, ensure the needs of anisotropic etching, selects deep reaction ion etching (DRIE) can be with
Keep very high etching selection ratio.Deep reaction ion etching (DRIE) system can select the common equipment of ability, and
It is not limited to a certain model.
Optionally, the MEMS layer 205 is etched in this step, to expose the expendable material of 202 top of the interconnection layer
Layer, without exposing the sacrificial material layer above bottom electrode.
Step 206 is executed, the sacrificial material layer 204 is removed, to expose the interconnection layer 202.
Specifically, as shown in Figure 2 d, it selects ashing method to remove the sacrificial material layer 204 in this step, can select
Originally common ashing method is received, it is not limited to a certain.
In the present invention in order to solve the problems, such as that the dielectric layer is difficult to etch, in the CMOS metal upperside interconnection layer shape
At sacrificial material layer, to replace the dielectric layer to be removed, and the sacrificial material layer can be more prone to by ashing method etc.
Method removal, so as to avoid after pattern MEMS layer under the depth of 10um the etching removal dielectric layer, relatively
It is not only simple and practicable in existing method, but also improve the performance and yield of device.
Step 207 is executed, forms insulating layer 206 on the side wall of the MEMS layer 205 and the dielectric layer 203；
Specifically, with reference to Fig. 2 e-2f, insulating layer is formed on the side wall of the MEMS layer 205 and the dielectric layer 203
Method is：The MEMS layer 205 and the articulamentum 202 is completely covered, as shown in Figure 2 e in deposition of dielectric materials；Selectivity erosion
The dielectric material for removing 202 top of the interconnection layer is carved, to form insulating layer on the side wall of the groove of through-hole to be formed
206, as shown in figure 2f.
Optionally, the insulating layer selects stearic acid tetraethoxysilane.
Step 208 is executed, in the disposed thereon conductive material 207 of the interconnection layer, through-hole is formed, to connect the CMOS
Device and the MEMS layer.
Specifically, as shown in Figure 2 g, the conductive material 207 is selected a kind of or more in W, polysilicon, SiGe and Cu
Kind.
Optionally, it the step of still further comprising planarization after depositing the conductive material 207, is led described in planarization
Electric material 207 is to the insulating layer 206.Wherein, it can use in this embodiment conventional flat in field of semiconductor manufacture
Change method realizes the planarization on surface.The non-limiting examples of the flattening method include mechanical planarization method and chemical machine
Tool polishes flattening method.
So far, the introduction of the correlation step of the semiconductor device fabrication processes of the embodiment of the present invention is completed.In above-mentioned step
Can also include other correlation steps, details are not described herein again after rapid.Also, in addition to the foregoing steps, the system of the present embodiment
Preparation Method can also include other steps among above-mentioned each step or between different steps, these steps can pass through
Various techniques in the prior art realize that details are not described herein again.
The present invention is in order to solve the problems, such as that dielectric layer described in the semiconductor devices preparation process is difficult to etch, to described
Preparation process is improved, and before forming MEMS layer, cavity or sacrifice are formed in the CMOS metal upperside interconnection layer
Material layer etches institute so as to avoid after patterning MEMS layer to replace the dielectric layer to be removed under the depth of 10um
Give an account of electric layer.The wherein described sacrificial material layer selects the material easily removed, such as amorphous carbon etc..The side through the invention
The through-hole that method is prepared has high-aspect-ratio, not only simple and practicable relative to existing method, but also improves the performance of device
And yield.
Fig. 3 is the preparation technology flow chart of sensor described in the embodiment of the invention, specifically includes following step
Suddenly：
Step 201 provides substrate, is formed with cmos device and the interconnection on the cmos device on the substrate
Layer；
Step 202 forms the dielectric layer with cavity on the substrate, and the cavity is located at the top of the interconnection layer；
Step 203 fills sacrificial material layer in the cavity, to define the shape of through-hole；
Step 204 forms MEMS layer on the dielectric layer, to cover the dielectric layer；
Step 205 patterns the MEMS layer, to form via openings above the cavity, exposes the expendable material
Layer；
Step 206 removes the sacrificial material layer, to expose the interconnection layer；
Step 207 fills conductive material in the cavity and the via openings, described to connect to form through-hole
Cmos device and the MEMS layer.
Embodiment 2
In this embodiment in order to more simplify the preparation process, can further to method described in embodiment 1 into
Row improves, such as in step 203, dielectric layer 203 is formed in the substrate 201, and pattern and formed after cavity not
Sacrificial material layer 204 is refilled, the pattern of the through-hole is defined with this, to also avoid in subsequent step described in removal
The step of sacrificial material layer 204, directly exposes the interconnection layer 202 after patterning the MEMS layer 205.In embodiment 2
Other steps be referred to embodiment 1.
Embodiment 3
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects the method system described in embodiment 1 or 2
It is standby.Interior bone described in the semiconductor devices that the method is prepared through the invention can preferably connect the CMOS
Device and MEMS device, switching performance are more stablized, and the yield of the semiconductor devices is improved.
Embodiment 4
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment 3.Wherein, semiconductor device
Part is semiconductor devices described in embodiment 3, or the semiconductor devices that the preparation method according to embodiment 1 or 2 obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products for including the semiconductor devices.The electronic device of the embodiment of the present invention is partly led due to the use of above-mentioned
Body device, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of preparation method of semiconductor devices, including：
Substrate is provided, is formed with cmos device and the interconnection layer on the cmos device on the substrate；
The dielectric layer with cavity is formed on the substrate, and the cavity runs through the dielectric layer, and the cavity is located at described
The top of interconnection layer, to define the shape of through-hole；
MEMS layer is formed on the dielectric layer, to cover the dielectric layer and the cavity；
The MEMS layer is patterned, to form via openings above the cavity, exposes the cavity and the interconnection layer；
Conductive material is filled in the cavity and the via openings, to form through-hole, to connect the cmos device and institute
State MEMS layer.
2. according to the method described in claim 1, it is characterized in that, the method still further comprises following steps：
Before forming the MEMS layer, sacrificial material layer is filled in the cavity, to define the shape of through-hole；
And after forming the opening, the sacrificial material layer is removed, to expose the interconnection layer.
3. according to the method described in claim 2, it is characterized in that, the sacrificial material layer includes amorphous carbon.
4. according to the method in claim 2 or 3, which is characterized in that ashing method is selected to remove the sacrificial material layer.
5. according to the method described in claim 1, it is characterized in that, being still further comprised before filling the conductive material：
Depositing insulating layer, to cover the MEMS layer and the interconnection layer；
The insulating layer for removing the upperside interconnection layer, to expose the interconnection layer.
6. according to the method described in claim 5, it is characterized in that, optionally blanket etching method removes the upperside interconnection layer
The insulating layer.
7. according to the method described in claim 5, it is characterized in that, the insulating layer selects stearic acid tetraethoxysilane.
8. according to the method described in claim 1, it is characterized in that, the MEMS layer selects Si, epi polysilicon or SiGe,
And the method for selecting deep reaction ion etching etches the MEMS layer, the via openings is formed, to obtain with high-aspect-ratio
The through-hole.
9. according to the method described in claim 1, it is characterized in that, if the interconnection layer includes spaced stem portion.
10. according to the method described in claim 1, it is characterized in that, the interconnection layer includes metal Al；
The dielectric layer includes oxide；
The conductive material includes W, polysilicon, SiGe or Cu.
11. a kind of semiconductor devices that the method based on described in one of claims 1 to 10 is prepared.
12. a kind of electronic device, including the semiconductor devices described in claim 11.
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| CN102420169A (en) * | 2011-05-13 | 2012-04-18 | 上海华力微电子有限公司 | Double-Damascus process of super-thick top-layer metal by virtue of filling sacrifice material in through hole |
| CN103081090A (en) * | 2010-09-10 | 2013-05-01 | Soitec公司 | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
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| US7297629B2 (en) * | 2004-09-15 | 2007-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ultra-thick metal-copper dual damascene process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103081090A (en) * | 2010-09-10 | 2013-05-01 | Soitec公司 | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
| CN102420169A (en) * | 2011-05-13 | 2012-04-18 | 上海华力微电子有限公司 | Double-Damascus process of super-thick top-layer metal by virtue of filling sacrifice material in through hole |
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