CN105185738A - Semiconductor device, preparation method and electronic device - Google Patents
Semiconductor device, preparation method and electronic device Download PDFInfo
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- CN105185738A CN105185738A CN201410279762.XA CN201410279762A CN105185738A CN 105185738 A CN105185738 A CN 105185738A CN 201410279762 A CN201410279762 A CN 201410279762A CN 105185738 A CN105185738 A CN 105185738A
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Abstract
The invention provides a semiconductor device, a preparation method and an electronic device. The method comprises steps: a substrate is provided, a CMOS device and an interconnection layer located on the CMOS device are formed on the substrate; a dielectric layer with a cavity is formed on the substrate, and the cavity is located above the interconnection layer to define a shape of a through hole; an MEMS layer is formed on the dielectric layer to cover the dielectric layer; the MEMS layer is patterned, a through hole is formed in the upper part of the cavity, and the cavity and the interconnection layer are exposed; conductive materials are loaded in the cavity and the through hole opening, a through hole is formed, and the CMOS device and the MEMS layer are connected. Before the MEMS layer is formed, a cavity or a sacrificial material layer is formed above the CMOS metal interconnection layer to replace the dielectric layer to be removed, and therefore etching of the dielectric layer in a depth of 10 micrometers after the MEMS layer is patterned is avoided. The preparation method is simple and practical compared with present methods, and the performances of the device are raised.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method, electronic installation.
Background technology
Along with the development of semiconductor technology, integrated CMOS and MEMS (micro electro mechanical system) (MEMS) device become state-of-the-art technology day by day, the cmos device being wherein embedded with MEMS, owing to having better performance and lower cost, becomes the main trend of integrated CMOS.
Wherein, have multiple method to realize the connection of cmos device and MEMS in integratecCMOS devices, such as eutectic engages (eutecticbonding) or interior bone (internalvia) etc.
Eutectic engages (eutecticbonding) technology can produce high contact resistance and high source resistance for circuit connection, thus increases the operating lag of device and the loss of power.
And for usually having the MEMS of the thicker MEMS layer be made up of Si, SiGe, polysilicon (Poly) or other materials, just need to use the through hole (highaspectratiovia) of high-aspect-ratio to realize described connection.
Usually select the method for deep reaction ion etching (DRIE) to form the through hole of described high-aspect-ratio for the MEMS with thicker MEMS material layer at present, but in this process, when more than the 10um degree of depth and also opening less, the dielectric layer removed in cmos device above metal wire will become very difficult, or even impossible.
Therefore, need to be improved further the preparation method of current semiconductor device, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device, comprising:
Substrate is provided, is formed with cmos device on the substrate and is positioned at the interconnection layer on described cmos device;
Form the dielectric layer with cavity on the substrate, described cavity is positioned at the top of described interconnection layer, to define the shape of through hole;
Described dielectric layer forms MEMS layer, to cover described dielectric layer;
MEMS layer described in patterning, to form via openings above described cavity, exposes described cavity and described interconnection layer;
Filled conductive material in described cavity and described via openings, to form through hole, connects described cmos device and described MEMS layer.
Alternatively, described method is also further comprising the steps:
Before the described MEMS layer of formation, in described cavity, fill sacrificial material layer, to define the shape of through hole;
And, after the described opening of formation, remove described sacrificial material layer, to expose described interconnection layer.
Alternatively, described sacrificial material layer comprises amorphous carbon.
Alternatively, ashing method is selected to remove described sacrificial material layer.
Alternatively, also comprised further before the described electric conducting material of filling:
Depositing insulating layer, to cover described MEMS layer and described interconnection layer;
Remove the described insulating barrier of described upperside interconnection layer, to expose described interconnection layer.
Alternatively, optionally blanket etching method removes the described insulating barrier of described upperside interconnection layer.
Alternatively, described insulating barrier selects stearic acid tetraethoxysilane.
Alternatively, described MEMS layer selects Si, epi polysilicon or SiGe, and selects the method for deep reaction ion etching to etch described MEMS layer, forms described via openings, to obtain the described through hole with high-aspect-ratio.
Alternatively, described interconnection layer comprises spaced some parts.
Alternatively, described interconnection layer comprises metal A l;
Described dielectric layer comprises oxide;
Described electric conducting material comprises W, polysilicon, SiGe or Cu.
Present invention also offers the semiconductor device that a kind of above-mentioned method prepares.
Present invention also offers a kind of electronic installation, comprise the described semiconductor device that said method prepares.
The problem that the present invention is difficult to etch to solve described semiconductor device preparation process dielectric layer, described preparation technology is improved, before formation MEMS layer, cavity or sacrificial material layer is formed above described CMOS metal interconnecting layer, replace the dielectric layer that will remove, thus etch described dielectric layer under avoiding the degree of depth at 10um after patterning MEMS layer.Wherein said sacrificial material layer selects the material easily removed, such as amorphous carbon etc.The through hole prepared by the method for the invention has high-aspect-ratio, not only simple relative to existing method, and improves performance and the yield of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
The preparation process schematic diagram that Fig. 1 is semiconductor device described in prior art;
The preparation process schematic diagram that Fig. 2 a-2g is semiconductor device described in the embodiment of the invention;
Preparation technology's flow chart that Fig. 3 is semiconductor device described in the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Through hole is mostly selected to connect in current described integratecCMOS devices, wherein select technique that through hole 10 carries out connecting as shown in Figure 1, first substrate 101 is provided, the metal interconnecting layer 102 described substrate 101 being formed with various cmos device and being positioned at above described cmos device, then dielectric layer 103 is formed, MEMS layer 104, dielectric layer 103 described in patterning, MEMS layer 104 forms the through-hole pattern with high-aspect-ratio, but because described MEMS layer 104 has larger thickness, therefore described in darker through-hole pattern, dielectric layer 103 removes the very difficult of change, even can not realize.
In order to solve Problems existing in the preparation process of semiconductor device described in prior art in the present invention, provide a kind of new semiconductor device preparation method, described method comprises:
Substrate is provided, is formed with cmos device on the substrate and is positioned at the interconnection layer on described cmos device;
Form the dielectric layer with cavity on the substrate, described cavity is positioned at the top of described interconnection layer, to define the shape of through hole;
Described dielectric layer forms MEMS layer, to cover described dielectric layer;
MEMS layer described in patterning, to form via openings above described cavity, exposes described cavity and described interconnection layer;
Filled conductive material in described cavity and described via openings, to form through hole, connects described cmos device and described MEMS layer.
Alternatively, in described cavity, sacrificial material layer can also be filled further, in embodiment 1 and embodiment 2, described two kinds of situations are described in detail respectively below.
Embodiment 1
Below in conjunction with accompanying drawing 2a-2g to of the present invention one particularly execution mode be further described.
First, perform step 201, first substrate 201 is provided, described substrate 201 is formed with cmos device.
Particularly, with reference to Fig. 2 a, described substrate 201 comprises Semiconductor substrate, and the various active devices formed over the substrate, wherein said Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Form various active device on the semiconductor substrate, such as form cmos device and other active device on the semiconductor substrate, described active device is not limited to a certain.
Then perform step 202, described substrate 201 forms interconnection layer 202.
Particularly, described interconnection layer 202 selects metal contact wires, and for the cmos device in described substrate and MEMS are formed electrical connection, alternatively, described interconnection layer 202 comprises some mutually isolated parts, and wherein said some parts are mutually isolated by dielectric layer.
The method forming interconnection layer 202 is on the substrate: depositing first dielectric layer on the substrate, then on described first dielectric layer, form the photoresist layer of patterning, described photoresist layer is formed with the pattern of opening, then be mask patterning described first dielectric layer with described photoresist layer, to form multiple opening in described first dielectric layer.
Then metal material is filled in said opening, to form metal level, described metal level is positioned at middle part can as the electrode of MEMS, such as the bottom electrode of motion sensor or inertial sensor, the metal level being positioned at both sides, as interconnection layer 202, is electrically connected for being formed by the cmos device of described MEMS and bottom.
Wherein, described metal material can aluminium, copper, gold, silver, tungsten and other similar materials.
Then perform step 203, described substrate 201 is formed the dielectric layer 203 with cavity, and described cavity is positioned at the top of described interconnection layer 202.
Particularly, dielectric layer 203 on described interconnection layer 202, described in there is dielectric layer 203 can use such as oxide, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Described dielectric layer 203 selects SiO in this embodiment
2.
Then dielectric layer 203 described in patterning, to form cavity, for defining the shape that will form through hole.
Dry etching dielectric layer 203 can be selected in this step, can CF be selected in described dry etching
4, CHF
3, add N in addition
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is preferably 5-60s, is more preferably 5-30s.
Then sacrificial material layer 204, to fill described cavity, forms through-hole pattern, obtain pattern as shown in Figure 2 a, wherein, described sacrificial material layer selects the material easily removed in subsequent step, and such as described sacrificial material layer includes but are not limited to: amorphous carbon.Wherein said amorphous carbon can be removed by ashing method, and does not need dry method or wet etching, is not easy the problem removed to avoid in prior art dielectric layer described in the groove of high-aspect-ratio.
Perform step 204, described dielectric layer 203 forms MEMS layer 205, to cover described dielectric layer 203.
Particularly, as shown in Figure 2 b, in this step, described MEMS layer 205 selects Si, epi polysilicon or SiGe, but is not limited to cited material.
Alternatively, can form various MEMS components and parts in described MEMS layer 205, such as the customary components etc. of various transducer, does not repeat them here.
Perform step 205, MEMS layer 205 described in patterning, to form via openings above described cavity, exposes described sacrificial material layer and described interconnection layer 202.
Particularly, as shown in Figure 2 c, select the method for deep reaction ion etching to etch described MEMS layer in this step, form described via openings, to obtain the described through hole with high-aspect-ratio.
Particularly, described MEMS layer 205 forms organic distribution layer (Organicdistributionlayer, ODL), siliceous bottom antireflective coating (Si-BARC), the photoresist layer of deposit patterned is gone up described siliceous bottom antireflective coating (Si-BARC), pattern definition on wherein said photoresist will to form the figure of opening, then etch described organic distribution layer, bottom antireflective coating, described MEMS layer 205 with described photoresist layer for mask layer, form described via openings.
Described via openings is positioned at the top of described sacrificial material layer, expose described sacrificial material layer 204, alternatively, deep reaction ion etching (DRIE) method is selected to etch described MEMS layer 205, in described deep reaction ion etching (DRIE) step, select gas hexa-fluoride (SF6) as process gas, apply radio-frequency power supply, hexa-fluoride reacting gas is made to form high ionization, controlling operating pressure in described etching step is 20mTorr-8Torr, frequently power is 600W, 13.5MHz, direct current (DC) bias can continuous control in-500V-1000V, ensure the needs of anisotropic etching, select deep reaction ion etching (DRIE) that very high etching selection ratio can be kept.The equipment that described deep reaction ion etching (DRIE) system can select ability conventional, is not limited to a certain model.
Alternatively, etch described MEMS layer 205 in this step, to expose the sacrificial material layer above described interconnection layer 202, and do not expose the sacrificial material layer above bottom electrode.
Perform step 206, remove described sacrificial material layer 204, to expose described interconnection layer 202.
Particularly, as shown in Figure 2 d, select ashing method to remove described sacrificial material layer 204 in this step, can select and originally receive conventional ashing method, be not limited to a certain.
In the present invention in order to solve the problem that described dielectric layer is difficult to etch, sacrificial material layer is formed above described CMOS metal interconnecting layer, replace the dielectric layer that will remove, and the method that described sacrificial material layer can be more prone to by ashing method etc. is removed, thus described dielectric layer is removed in etching under avoiding the degree of depth at 10um after patterning MEMS layer, not only simple relative to existing method, and improve performance and the yield of device.
Perform step 207, the sidewall of described MEMS layer 205 and described dielectric layer 203 forms insulating barrier 206;
Particularly, with reference to Fig. 2 e-2f, the method that the sidewall of described MEMS layer 205 and described dielectric layer 203 is formed insulating barrier is: deposition of dielectric materials, covers described MEMS layer 205 and described articulamentum 202, as shown in Figure 2 e completely; Selective etch removes the described dielectric material above described interconnection layer 202, to form insulating barrier 206 on the sidewall of groove that will form through hole, as shown in figure 2f.
Alternatively, described insulating barrier selects stearic acid tetraethoxysilane.
Perform step 208, at the disposed thereon electric conducting material 207 of described interconnection layer, form through hole, to connect described cmos device and described MEMS layer.
Particularly, as shown in Figure 2 g, one or more in W, polysilicon, SiGe and Cu selected by described electric conducting material 207.
Alternatively, after the described electric conducting material 207 of deposition, also comprise the step of planarization further, electric conducting material 207 described in planarization is to described insulating barrier 206.Wherein, flattening method conventional in field of semiconductor manufacture can be used in this embodiment to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.
So far, the introduction of the correlation step of the semiconductor device fabrication processes of the embodiment of the present invention is completed.After the above step, other correlation step can also be comprised, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also comprise other steps among each step above-mentioned or between different steps, and these steps all can be realized by various technique of the prior art, repeat no more herein.
The problem that the present invention is difficult to etch to solve dielectric layer described in described semiconductor device preparation process, described preparation technology is improved, before formation MEMS layer, cavity or sacrificial material layer is formed above described CMOS metal interconnecting layer, replace the dielectric layer that will remove, thus etch described dielectric layer under avoiding the degree of depth at 10um after patterning MEMS layer.Wherein said sacrificial material layer selects the material easily removed, such as amorphous carbon etc.The through hole prepared by the method for the invention has high-aspect-ratio, not only simple relative to existing method, and improves performance and the yield of device.
Preparation technology's flow chart that Fig. 3 is transducer described in the embodiment of the invention, specifically comprises the following steps:
Step 201 provides substrate, is formed with cmos device on the substrate and is positioned at the interconnection layer on described cmos device;
Step 202 forms the dielectric layer with cavity on the substrate, and described cavity is positioned at the top of described interconnection layer;
Step 203 fills sacrificial material layer in described cavity, to define the shape of through hole;
Step 204 forms MEMS layer on described dielectric layer, to cover described dielectric layer;
MEMS layer described in step 205 patterning, to form via openings above described cavity, exposes described sacrificial material layer;
Step 206 removes described sacrificial material layer, to expose described interconnection layer;
Step 207 is filled conductive material in described cavity and described via openings, to form through hole, connects described cmos device and described MEMS layer.
Embodiment 2
In this embodiment in order to more simplify described preparation technology, can improve method described in embodiment 1 further, such as in step 203, described substrate 201 forms dielectric layer 203, and patterning does not recharge sacrificial material layer 204 after forming cavity, defines the pattern of described through hole, thus it also avoid the step removing described sacrificial material layer 204 in subsequent step with this, after MEMS layer 205 described in patterning, directly expose described interconnection layer 202.Other step in embodiment 2 all can with reference to embodiment 1.
Embodiment 3
Present invention also offers a kind of semiconductor device, described semiconductor device selects the method described in embodiment 1 or 2 to prepare.Interior bone described in the semiconductor device prepared by the method for the invention can better connect described cmos device and MEMS, and switching performance is more stable, improves the yield of described semiconductor device.
Embodiment 4
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment 3.Wherein, semiconductor device is the semiconductor device described in embodiment 3, or the semiconductor device that the preparation method according to embodiment 1 or 2 obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a preparation method for semiconductor device, comprising:
Substrate is provided, is formed with cmos device on the substrate and is positioned at the interconnection layer on described cmos device;
Form the dielectric layer with cavity on the substrate, described cavity is positioned at the top of described interconnection layer, to define the shape of through hole;
Described dielectric layer forms MEMS layer, to cover described dielectric layer;
MEMS layer described in patterning, to form via openings above described cavity, exposes described cavity and described interconnection layer;
Filled conductive material in described cavity and described via openings, to form through hole, connects described cmos device and described MEMS layer.
2. method according to claim 1, is characterized in that, described method is also further comprising the steps:
Before the described MEMS layer of formation, in described cavity, fill sacrificial material layer, to define the shape of through hole;
And, after the described opening of formation, remove described sacrificial material layer, to expose described interconnection layer.
3. method according to claim 2, is characterized in that, described sacrificial material layer comprises amorphous carbon.
4. according to the method in claim 2 or 3, it is characterized in that, select ashing method to remove described sacrificial material layer.
5. method according to claim 1, is characterized in that, also comprises further before the described electric conducting material of filling:
Depositing insulating layer, to cover described MEMS layer and described interconnection layer;
Remove the described insulating barrier of described upperside interconnection layer, to expose described interconnection layer.
6. method according to claim 5, is characterized in that, optionally blanket etching method removes the described insulating barrier of described upperside interconnection layer.
7. method according to claim 5, is characterized in that, described insulating barrier selects stearic acid tetraethoxysilane.
8. method according to claim 1, it is characterized in that, described MEMS layer selects Si, epi polysilicon or SiGe, and selects the method for deep reaction ion etching to etch described MEMS layer, form described via openings, to obtain the described through hole with high-aspect-ratio.
9. method according to claim 1, is characterized in that, described interconnection layer comprises spaced some parts.
10. method according to claim 1, is characterized in that, described interconnection layer comprises metal A l;
Described dielectric layer comprises oxide;
Described electric conducting material comprises W, polysilicon, SiGe or Cu.
11. 1 kinds of semiconductor device prepared based on the method one of claim 1 to 10 Suo Shu.
12. 1 kinds of electronic installations, comprise semiconductor device according to claim 11.
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| CN111052346A (en) * | 2017-08-13 | 2020-04-21 | 应用材料公司 | Self-aligned high aspect ratio structure and manufacturing method thereof |
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| US20060057842A1 (en) * | 2004-09-15 | 2006-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ultra-thick metal-copper dual damascene process |
| CN102420169A (en) * | 2011-05-13 | 2012-04-18 | 上海华力微电子有限公司 | Double-Damascus process of super-thick top-layer metal by virtue of filling sacrifice material in through hole |
| CN103081090A (en) * | 2010-09-10 | 2013-05-01 | Soitec公司 | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
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| US20060057842A1 (en) * | 2004-09-15 | 2006-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ultra-thick metal-copper dual damascene process |
| CN103081090A (en) * | 2010-09-10 | 2013-05-01 | Soitec公司 | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
| CN102420169A (en) * | 2011-05-13 | 2012-04-18 | 上海华力微电子有限公司 | Double-Damascus process of super-thick top-layer metal by virtue of filling sacrifice material in through hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111052346A (en) * | 2017-08-13 | 2020-04-21 | 应用材料公司 | Self-aligned high aspect ratio structure and manufacturing method thereof |
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