CN105097653B - A kind of structure of silicon hole and preparation method thereof - Google Patents
A kind of structure of silicon hole and preparation method thereof Download PDFInfo
- Publication number
- CN105097653B CN105097653B CN201410191475.3A CN201410191475A CN105097653B CN 105097653 B CN105097653 B CN 105097653B CN 201410191475 A CN201410191475 A CN 201410191475A CN 105097653 B CN105097653 B CN 105097653B
- Authority
- CN
- China
- Prior art keywords
- silicon hole
- mask layer
- semiconductor substrate
- silicon
- hole groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of structure of silicon hole and preparation method thereof, the described method includes：There is provided Semiconductor substrate, formed with silicon hole groove in the Semiconductor substrate, wherein the silicon hole groove bottom center region formed with column；By the way of electrochemical plating, metal material is filled in the silicon hole groove.Production method according to the present invention, can effectively avoid the generation in metal filled hole in silicon hole, and then improve the electric conductivity and its breakdown characteristics of interconnecting silicon through holes, enhance its reliability and stability.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of structure of silicon hole and preparation method thereof.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked be subject to consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple and different functions in circuit version, thus go out
3D integrated circuits (integrated circuit, IC) technology, 3D integrated circuits (integrated circuit, IC) quilt are showed
A kind of system-level integrated morphology is defined as, multiple chips are stacked in vertical plane direction, so that space is saved, each chip
Marginal portion can draw multiple pins as needed, utilize these pins as needed, it would be desirable to which the chip of interconnection leads to
Metal wire interconnection is crossed, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and between chip
Connection relation is more complicated, then just may require that final wire laying mode is more chaotic, and can lead using more metal lines
Cause volume increase.
Therefore, silicon hole (Through is mostly used in 3D IC technologies and 2.5D silicon intermediary layer technologies at present
Silicon Via, TSV), silicon hole technology is for a kind of novel encapsulated technology by different chip packages together, it is logical
Cross and make through hole through substrate, being wherein filled with conductive material, then by multiple chips or stacked wafer together, utilize
Through hole realizes the electrical connection between chip.The density that TSV can be such that chip is stacked in three-dimensional is maximum, and appearance and size is most
It is small, and substantially improve the performance of chip speed and low-power consumption.
The production method of prior art silicon hole is：Step 1: providing Semiconductor substrate, the Semiconductor substrate is etched,
Form groove；Step 2: in the side wall and bottom deposit oxide-isolation layer of the groove；Step 3: in the side of the groove
Adhesion layer and Seed Layer are sequentially formed on wall and bottom；Step 4: electroplate (Electro-Chemical using electrochemistry
Plating, ECP) method form the metal filled groove；Step 5: then performing planarisation step, silicon hole is obtained.
But as shown in Figure 1, due to the high depth-to-width ratio of silicon hole and the plating filling mode of its (bottom up) from bottom to top, hold
Filling cavity 101 is easily formed in the conductive material intermediate region of filling, and the presence in cavity can influence the reliability and stabilization of TSV
The characteristics such as property.
Therefore, it is necessary to a kind of new production method is proposed, to solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, the embodiment of the present invention one proposes a kind of making side of silicon hole
Method, comprises the following steps：Semiconductor substrate is provided, formed with silicon hole groove in the Semiconductor substrate, wherein described
The bottom center region of silicon hole groove is formed with column；By the way of electrochemical plating, filled in the silicon hole groove
Metal material.
Further, the stem height is less than or equal to the half of the silicon hole groove height.
Further, before filling metal material in the silicon hole groove, it is additionally included in shape in the silicon hole groove
The step of into separation layer.
Further, before the metal material is filled, be additionally included in the silicon hole groove bottom and side wall and
The step of adhesion layer and Seed Layer are sequentially formed on the surrounded surface of the column.
Further, the metal material is copper.
Further, the forming method of the silicon hole groove is：The first mask is formed on the semiconductor substrate surface
Layer；First mask layer is patterned, to form column mask corresponding with the column pattern；In the Semiconductor substrate table
Face forms the second mask layer, and second mask layer has the patterns of openings corresponding to the silicon hole groove；With patterned
First mask layer and the second mask layer are mask, etch the Semiconductor substrate, stop at desired depth；Described in removal
First mask layer and second mask layer；The 3rd mask layer, the 3rd mask layer are formed in the semiconductor substrate surface
With the patterns of openings corresponding to the silicon hole groove, using the 3rd mask layer as mask, continue to etch the semiconductor
Substrate, to form complete silicon hole groove.
Further, first mask layer is oxide hard-mask layer.
Further, the etching is carried out using deep reaction ion etching.
The embodiment of the present invention two provides a kind of through-silicon via structure, including Semiconductor substrate and positioned at the Semiconductor substrate
In silicon hole, the silicon hole bottom center region is formed with column.
Further, the stem height is less than or equal to the half of the silicon hole height.
Further, the material of the column is silicon.
To sum up shown, production method according to the present invention, can effectively avoid the generation in metal filled hole in silicon hole, into
And the electric conductivity and its breakdown characteristics of interconnecting silicon through holes are improved, enhance its reliability and stability.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the schematic diagram of the filling mode of prior art electrochemistry plating metal；
Fig. 2 a~2h by implemented successively according to the step of embodiment of the present invention one acquisition device diagrammatic cross-section；
Fig. 3 is flow chart the step of implementation successively according to the method for the embodiment of the present invention one；
Fig. 4 is the schematic diagram according to two through-silicon via structure of the embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
It should be appreciated that when the term " comprising " and/or " including " is used in this specification, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
Embodiment one
The present invention is in order to solve the problems, such as present in current silicon hole manufacturing process, there is provided a kind of new production method,
2a-2h and Fig. 3 flow charts are further described the method below in conjunction with the accompanying drawings.
First, with reference to figure 2a, step 301 is performed, there is provided Semiconductor substrate 200, forms first on semiconductor substrate 200
Mask layer 201.
The Semiconductor substrate 200 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx are laminated on insulator
(SiGeOI) etc..It could be formed with other active areas or active device in the substrate, details are not described herein.
Wherein, first mask layer 201 selects oxide hard-mask layer, and the oxide hard-mask layer can be selected
Ion strengthens one or more combinations in TEOS layers of PETEOS layers of ethyl orthosilicate and ethyl orthosilicate.Preferably,
The deposition process of first mask layer 201 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or
Atomic layer deposition (ALD) method etc., preferred chemical vapor deposition (CVD) method in of the invention.
Then, with reference to shown in figure 2b, step 302 is performed, patterns first mask layer 201, is stood with being formed with described
The corresponding column mask of column pattern.
Specifically, with diluted hydrofluoric acid DHF (wherein comprising HF, H2O2And H2O the oxide hard-mask layer) is etched
201.Wherein, the concentration of the DHF does not limit strictly, in the present invention preferred HF:H2O2:H2O=0.1-1.5:1:5.
Then, with reference to shown in figure 2c, step 303 is performed, the second mask layer 202, institute are formed on 200 surface of Semiconductor substrate
Stating the second mask layer 202 has the patterns of openings for corresponding to silicon hole groove；With patterned first mask layer 201 and
Two mask layers 202 are mask, etch the Semiconductor substrate 200, stop at desired depth.
Second mask layer 202 is photoresist, and photoresist 202, patterning are coated on the semiconductor substrate surface
The photoresist, to form the pattern of silicon hole groove.With patterned first mask layer, 201 and second mask layer 202
For mask, the surface of the Semiconductor substrate exposed is etched, predetermined etching depth is less than or equal to pre-formed silicon hole groove
The half of depth, the etching is carried out using deep reaction ion etching (DRIE).As an example, DRIE is to oxide
Etching speed be less than 10A/loop, the etching speed to silicon is 2750A/loop.And since the first mask layer is oxide hard
Mask layer, can't be to central area as the mask of silicon hole intermediate region Semiconductor substrate, therefore when carrying out the etching
Semiconductor substrate performs etching.
With reference to shown in figure 2d, step 304 is performed, removes 201 and second mask layer 202 of the first mask layer.
First mask layer 201 is removed first, and the minimizing technology can select dry etching to remove the hard mask
Layer 201, selects SiCoNi processing procedures to etch the hard mask layer 201, the SiCoNi processing procedures are to described in the dry etching
Hard mask layer 201 has a high selectivity, and design parameter in the SiCoNi processing procedures, those skilled in the art can be according to technique
Need to make choice, it is not limited to a certain numerical value.
The second mask layer 202 is removed, as an example, the second mask layer is photoresist layer.The method for removing photoresist
Optional wet method is removed photoresist or cineration technics removes photoresist.
With reference to shown in figure 2e, step 305 is performed, forms the 3rd mask layer 203 in the semiconductor substrate surface, the 3rd covers
Film layer 203 has the patterns of openings corresponding to silicon hole groove.
With reference to shown in figure 2f, step 306 is performed, with the 3rd mask layer 203 for mask, continues etch semiconductor substrates 200,
To form complete silicon hole groove 204.
The etching is carried out using deep reaction ion etching (DRIE).In the deep reaction ion etching (DRIE) step
Select gas hexa-fluoride (SiF6) process gas is used as, apply radio-frequency power supply so that hexa-fluoride reaction air inlet forms high electricity
From it is 20mTorr-8Torr that operating pressure is controlled in the etching step, and frequency power is 600W, and 13.5MHz, Dc bias can
With the continuous control in -500V~1000V, ensure the needs of anisotropic etching, select deep reaction ion etching (DRIE) can
To keep very high etching photoresist to select ratio.Deep reaction ion etching (DRIE) system can select ability is common to set
It is standby, it is not limited to a certain model.Since in abovementioned steps, a part is had been completed to the etching of silicon hole groove, this step
When rapid, only need to etch remaining part semiconductor substrate 200 again can complete the making of whole groove 204.Simultaneously as at it
During preceding etching, silicon hole central area Semiconductor substrate is not performed etching, and during this step, silicon hole central area semiconductor
Substrate is not covered by mask layer, therefore also synchronously it is performed etching.Therefore also just in the bottom center region of silicon hole groove 204
Column 205 is formd, 205 height of institute's formation column is less than or equal to the half of the silicon hole groove height.Etch
Cheng Hou, removes the photoresist on 200 surface of Semiconductor substrate, this step is the prior art, and this will not be repeated here.
With reference to shown in figure 2g, step 307, the shape in 300 surface of Semiconductor substrate and the silicon hole groove 204 are performed
Into separation layer 206.
Separation layer 206 covers bottom and the side wall of groove, can be used for by the material to be filled in substrate and groove every
Leave, the two is not electrically connected.Separation layer 206 can use any suitable material, such as can be silica or nitridation
Silicon.Can be for example, by aoxidizing, depositing or any appropriate technique forms separation layer.Specifically, one in the present invention is specific
In ground embodiment, the separation layer 206 is formed by the method for thermal oxide, the separation layer 205 is SiO2Layer, its thickness
For 8~50 angstroms, but it is not limited to the thickness.
With reference to shown in figure 2h, step 308 is performed, by the way of electrochemical plating, is filled in the silicon hole groove 204
Metal material 207.
, need to be the four of the bottom of the silicon hole groove 204 and side wall and the column before metal material is filled
Adhesion layer and Seed Layer are sequentially formed in perimeter surface, to put it more simply, being not shown in diagram.Preferably, the adhesion layer
Forming method can select physical vaporous deposition and chemical vapour deposition technique, specifically, evaporation, electron beam can be selected to steam
Hair, plasma spray deposition and sputtering, preferred plasma spray deposition and sputtering method form described in the present invention
Adhesion layer.The thickness of the adhesion layer is not limited in a certain numerical value or scope, can be adjusted as needed.As
It is preferred that the adhesive layer material can be titanium tungsten etc., but it is not limited to above-mentioned material.Seed Layer can be sunk using physical vapor
The methods of product, atomic layer deposition, chemical vapor deposition or plasma reinforced chemical vapour deposition, makes, and material can be metal,
Such as copper, gold, but it is not limited to above-mentioned material.Seed Layer can include the identical material that packing material as described below uses,
Although the scope of the present invention is not limited in this respect.
Metal material 207 is selected, such as the groove 204 for selecting metallic copper to fill the silicon hole, pass through in the present invention
The method of Cu electroplating (ECP) carries out the filling.When carrying out Cu electroplating (ECP), copper coating thickness (um)=electric current
Density (ASF) × electroplating time (min) × electroplating efficiency × 0.0202；General electro-coppering current efficiency is 90-100%, at this
Need to fill the groove 204 in invention, therefore need in plating use additive, the additive is flat dose
(LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).Due to depositing for silicon hole bottom portion of groove column
The filing effect of (bottom up) from bottom to top is being bypassed, is reducing the generation of filling hole.
Finally, also need to be chemically-mechanicapolish polished (CMP) technique, planarize the metal material to the Semiconductor substrate
Surface, to form silicon hole.It can realize table using flattening method conventional in field of semiconductor manufacture in this step
The planarization in face.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing planarization side
Method.Chemically mechanical polishing flattening method is more often used.
Embodiment two
As shown in figure 4, the present invention also provides a kind of through-silicon via structure 402 of the making of the method according to embodiment one, bag
Include Semiconductor substrate and the silicon hole in the Semiconductor substrate, the through-silicon via structure bottom center region formed with
Column 401.As an example, 401 height of column is less than or equal to the half of the silicon hole height.As one
A example, the material of the column 401 is silicon.The filling that (bottom up) from bottom to top has been bypassed by the design of column is imitated
Should, reduce the generation of filling hole.And then the electric conductivity and its breakdown characteristics of interconnecting silicon through holes are improved, enhance it
Reliability and stability.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of production method of silicon hole, including：
Semiconductor substrate is provided, formed with silicon hole groove in the Semiconductor substrate, wherein in the silicon hole groove
Bottom center region includes formed with column, the forming method of the silicon hole groove：
The first mask layer is formed on the semiconductor substrate surface；
First mask layer is patterned, to form column mask corresponding with the column pattern；
The second mask layer is formed in the semiconductor substrate surface, second mask layer, which has, corresponds to the silicon hole groove
Patterns of openings；
Using patterned first mask layer and the second mask layer as mask, the Semiconductor substrate is etched, is stopped at predetermined
Depth；
Remove first mask layer and second mask layer；
The 3rd mask layer is formed in the semiconductor substrate surface, the 3rd mask layer, which has, corresponds to the silicon hole groove
Patterns of openings, using the 3rd mask layer as mask, continue to etch the Semiconductor substrate, to form silicon hole groove；
By the way of electrochemical plating, metal material is filled in the silicon hole groove.
2. the method as described in claim 1, it is characterised in that it is high that the stem height is less than or equal to the silicon hole groove
The half of degree.
3. the method as described in claim 1, it is characterised in that before filling metal material in the silicon hole groove, also
It is included in the silicon hole groove the step of forming separation layer.
4. the method as described in claim 1, it is characterised in that before the metal material is filled, be additionally included in the silicon
The step of adhesion layer and Seed Layer being sequentially formed on the surrounded surface of the bottom of through hole groove and side wall and the column.
5. the method as described in claim 1, it is characterised in that the metal material is copper.
6. the method as described in claim 1, it is characterised in that first mask layer is oxide hard-mask layer.
7. the method as described in claim 1, it is characterised in that the etching is carried out using deep reaction ion etching.
8. the through-silicon via structure that a kind of method using described in one of 1-7 prepares, including Semiconductor substrate and positioned at institute
The silicon hole in Semiconductor substrate is stated, the silicon hole bottom center region is formed with column.
9. structure as claimed in claim 8, it is characterised in that the stem height is less than or equal to the silicon hole height
Half.
10. structure as claimed in claim 8, it is characterised in that the material of the column is silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410191475.3A CN105097653B (en) | 2014-05-07 | 2014-05-07 | A kind of structure of silicon hole and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410191475.3A CN105097653B (en) | 2014-05-07 | 2014-05-07 | A kind of structure of silicon hole and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097653A CN105097653A (en) | 2015-11-25 |
| CN105097653B true CN105097653B (en) | 2018-05-08 |
Family
ID=54577784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410191475.3A Active CN105097653B (en) | 2014-05-07 | 2014-05-07 | A kind of structure of silicon hole and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105097653B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010853B (en) * | 2017-12-15 | 2021-06-22 | 西安科锐盛创新科技有限公司 | Adapter plate based on through silicon via and preparation method thereof |
| CN108054139B (en) * | 2017-12-15 | 2020-12-18 | 浙江清华柔性电子技术研究院 | TSV adapter plate and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383920B1 (en) * | 2001-01-10 | 2002-05-07 | International Business Machines Corporation | Process of enclosing via for improved reliability in dual damascene interconnects |
| CN1197128C (en) * | 1999-05-03 | 2005-04-13 | 自由度半导体公司 | Method for forming copper layer on semiconductor wafer |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Manufacturing method for vertically interconnecting carbon nanotube bundles |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100045857A (en) * | 2008-10-24 | 2010-05-04 | 삼성전자주식회사 | Semiconductor chip, stack module, memory card, and method of fabricating the semiconductor chip |
| US8431431B2 (en) * | 2011-07-12 | 2013-04-30 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
-
2014
- 2014-05-07 CN CN201410191475.3A patent/CN105097653B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1197128C (en) * | 1999-05-03 | 2005-04-13 | 自由度半导体公司 | Method for forming copper layer on semiconductor wafer |
| US6383920B1 (en) * | 2001-01-10 | 2002-05-07 | International Business Machines Corporation | Process of enclosing via for improved reliability in dual damascene interconnects |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Manufacturing method for vertically interconnecting carbon nanotube bundles |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097653A (en) | 2015-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI719052B (en) | Semiconductor devices and methods of forming the same | |
| JP5562087B2 (en) | Via structure and via etching process to form it | |
| CN104916578B (en) | Air gap scheme for BEOL techniques | |
| CN106711084B (en) | The more block pieces deposition formed for air gap | |
| US10141394B2 (en) | Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof | |
| TWI653691B (en) | Bonding structures and methods forming the same | |
| KR20130031822A (en) | Method of forming and patterning conformal insulation layer in vias and etched structures | |
| US10062656B2 (en) | Composite bond structure in stacked semiconductor structure | |
| CN103390581A (en) | Through-silicon-via etching method | |
| TW201739028A (en) | 3DIC structure and method for hybrid bonding semiconductor wafers | |
| CN104752323B (en) | A kind of semiconductor devices and preparation method thereof | |
| CN104752324A (en) | Preparation method of semiconductor device | |
| CN105097777B (en) | A kind of semiconductor devices and preparation method thereof | |
| KR101701573B1 (en) | Bi-layer hard mask for robust metalization profile | |
| CN105097653B (en) | A kind of structure of silicon hole and preparation method thereof | |
| US7927966B2 (en) | Method of manufacturing openings in a substrate, a via in substrate, and a semiconductor device comprising such a via | |
| US8551856B2 (en) | Embedded capacitor and method of fabricating the same | |
| CN104900543B (en) | A kind of semiconductor devices and preparation method thereof | |
| CN103227145B (en) | Integrated circuit and for the treatment of the method with the integrated circuit imbedding feature | |
| CN105895507B (en) | Radio frequency capacity cell based on silicon-on-insulator substrate and preparation method thereof | |
| CN104347490B (en) | The method of silicon hole filling | |
| CN105845650B (en) | A kind of through-silicon via structure and preparation method thereof | |
| KR102656751B1 (en) | Method for manufacturing hollow MEMS structures | |
| US9478464B2 (en) | Method for manufacturing through-hole silicon via | |
| CN108064412A (en) | Body block layer transferring plates with multiple etching stopping layers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |