CN105140116A - 磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法 - Google Patents

磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法 Download PDF

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CN105140116A
CN105140116A CN201510490465.4A CN201510490465A CN105140116A CN 105140116 A CN105140116 A CN 105140116A CN 201510490465 A CN201510490465 A CN 201510490465A CN 105140116 A CN105140116 A CN 105140116A
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hard mask
photoresist
etching
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张振兴
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明提供了一种磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法,包括:沉积氧化物硬掩膜层;在所述氧化物硬掩膜层上布置抗反射涂层;在所述抗反射涂层上布置光刻胶并且使得光刻胶图案化,随后在抗反射层的刻蚀过程中使图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜;利用图案化的光刻胶对氧化物硬掩膜层进行干法软刻蚀;执行灰化处理以及湿法刻蚀。

Description

磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法
技术领域
本发明涉及半导体制造领域,更具体地说,本发明涉及一种磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法。
背景技术
对于0.30um功率器件产品,在磁增强反应离子蚀刻设备(例如AMATsuper-E)下,氧化物硬掩膜刻蚀存在侧壁粗糙的问题。具体地说,在现有技术中,对于硬掩膜刻蚀,一般步骤是:首先沉积氧化物硬掩膜层;随后布置光刻胶并且使得光刻胶图案化;随后利用图案化的光刻胶对氧化物硬掩膜层进行刻蚀;随后执行灰化处理以及湿法刻蚀。
但是,图1示意性地示出了根据现有技术的磁增强反应离子蚀刻方法导致的侧壁粗糙问题的显微示图。如图1中虚线框所示,利用现有技术的方法,得到的氧化物硬掩膜的侧壁并不光滑,而是存在条纹状的纹理。
发明内容
本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种能够针对磁增强反应离子蚀刻改进硬掩膜侧壁粗糙度的方法。
为了实现上述技术目的,根据本发明,提供了一种磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法,包括:
第一步骤:沉积氧化物硬掩膜层;
第二步骤:在所述氧化物硬掩膜层上布置抗反射涂层;
第三步骤:在所述抗反射涂层上布置光刻胶并且使得光刻胶图案化,随后在抗反射层的刻蚀过程中使图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜;
第四步骤:利用图案化的光刻胶对氧化物硬掩膜层进行干法软刻蚀;
第五步骤:执行灰化处理,以及利用软刻蚀后的氧化物硬掩膜层执行湿法刻蚀。
优选地,所述氧化物硬掩膜层的材料是氧化硅。
优选地,所述氧化物硬掩膜层的厚度介于2500A-3500A之间。
优选地,所述氧化物硬掩膜层的厚度为3000A。
优选地,所述抗反射涂层的厚度介于600A-1000A之间。
优选地,所述抗反射涂层的厚度为800A。
优选地,所述软刻蚀的功率介于150W至350W之间。
优选地,所述软刻蚀的功率不大于300W。
优选地,所述软刻蚀的刻蚀气体选自CF4、CHF3和CH2F2
在本发明中,由于在图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜,能够有助于使得侧壁变得光滑,从而光滑的侧壁轮廓可以被传递至氧化物硬掩膜上。而且,相对于传统刻蚀功率更小的软刻蚀可以降低等离子体对侧壁的伤害。
附图说明
结合附图,并通过参考下面的详细描述,将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征,其中:
图1示意性地示出了根据现有技术的磁增强反应离子蚀刻方法得到的侧壁粗糙问题的显微示图。
图2示意性地示出了根据本发明优选实施例的磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法的流程图。
图3示意性地示出了根据本发明优选实施例的磁增强反应离子蚀刻方法得到的光滑侧壁的显微示图。
需要说明的是,附图用于说明本发明,而非限制本发明。注意,表示结构的附图可能并非按比例绘制。并且,附图中,相同或者类似的元件标有相同或者类似的标号。
具体实施方式
为了使本发明的内容更加清楚和易懂,下面结合具体实施例和附图对本发明的内容进行详细描述。
图2示意性地示出了根据本发明优选实施例的磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法的流程图。
如图2所示,根据本发明优选实施例的磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法包括:
第一步骤S1:沉积氧化物硬掩膜层;例如,所述氧化物硬掩膜层的材料是氧化硅。优选地,所述氧化物硬掩膜层的厚度介于2500A-3500A之间。进一步优选地,所述氧化物硬掩膜层的厚度为3000A。
第二步骤S2:在所述氧化物硬掩膜层上布置抗反射涂层;优选地,所述抗反射涂层的厚度介于600A-1000A之间。进一步优选地,所述抗反射涂层的厚度为800A。
第三步骤S3:在所述抗反射涂层上布置光刻胶并且使得光刻胶图案化,随后在抗反射层的刻蚀过程中(即,在使得抗反射层相应地图案化以具有与图案化的光刻胶相同的图案的过程中)使图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜;
第四步骤S4:利用图案化的光刻胶对氧化物硬掩膜层进行干法软刻蚀(SoftEtching);优选地,所述软刻蚀的功率介于150W至350W之间。优选地,所述软刻蚀的功率不大于300W。优选地,所述软刻蚀的刻蚀气体选自CF4、CHF3和CH2F2
第五步骤S5:执行灰化处理,以及利用软刻蚀后的氧化物硬掩膜层执行湿法刻蚀。
图3示意性地示出了根据本发明上述优选实施例的磁增强反应离子蚀刻方法得到的光滑侧壁的显微示图。
可以看出,在本发明中,由于在图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜,能够有助于使得侧壁变得光滑,从而光滑的侧壁轮廓可以被传递至氧化物硬掩膜上。而且,相对于传统刻蚀功率更小的软刻蚀可以降低等离子体对侧壁的伤害。
此外,需要说明的是,除非特别说明或者指出,否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。
可以理解的是,虽然本发明已以较佳实施例披露如上,然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言,在不脱离本发明技术方案范围情况下,都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。

Claims (9)

1.一种磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法,其特征在于包括:
第一步骤:沉积氧化物硬掩膜层;
第二步骤:在所述氧化物硬掩膜层上布置抗反射涂层;
第三步骤:在所述抗反射涂层上布置光刻胶并且使得光刻胶图案化,随后在抗反射层的刻蚀过程中使图案化的光刻胶和抗反射涂层的侧壁上布置聚合物薄膜;
第四步骤:利用图案化的光刻胶对氧化物硬掩膜层进行干法软刻蚀;
第五步骤:执行灰化处理,以及利用软刻蚀后的氧化物硬掩膜层执行湿法刻蚀。
2.根据权利要求1所述的方法,其特征在于,所述氧化物硬掩膜层的材料是氧化硅。
3.根据权利要求1或2所述的方法,其特征在于,所述氧化物硬掩膜层的厚度介于2500A-3500A之间。
4.根据权利要求1或2所述的方法,其特征在于,所述氧化物硬掩膜层的厚度为3000A。
5.根据权利要求1或2所述的方法,其特征在于,所述抗反射涂层的厚度介于600A-1000A之间。
6.根据权利要求1或2所述的方法,其特征在于,所述抗反射涂层的厚度为800A。
7.根据权利要求1或2所述的方法,其特征在于,所述软刻蚀的功率介于150W至350W之间。
8.根据权利要求1或2所述的方法,其特征在于,所述软刻蚀的功率不大于300W。
9.根据权利要求1或2所述的方法,其特征在于,所述软刻蚀的刻蚀气体选自CF4、CHF3和CH2F2
CN201510490465.4A 2015-08-11 2015-08-11 磁增强反应离子蚀刻下的硬掩膜侧壁粗糙度改进方法 Pending CN105140116A (zh)

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Cited By (1)

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CN106348246A (zh) * 2016-11-11 2017-01-25 宁波大学 一种改善波导侧壁的icp刻蚀方法

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Publication number Priority date Publication date Assignee Title
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Application publication date: 20151209