CN109037040B - 提高双大马士革刻蚀次沟槽工艺窗口的方法 - Google Patents

提高双大马士革刻蚀次沟槽工艺窗口的方法 Download PDF

Info

Publication number
CN109037040B
CN109037040B CN201810768565.2A CN201810768565A CN109037040B CN 109037040 B CN109037040 B CN 109037040B CN 201810768565 A CN201810768565 A CN 201810768565A CN 109037040 B CN109037040 B CN 109037040B
Authority
CN
China
Prior art keywords
etching
barrier layer
photoresist
light
dual damascene
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810768565.2A
Other languages
English (en)
Other versions
CN109037040A (zh
Inventor
俞春兰
张钱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN201810768565.2A priority Critical patent/CN109037040B/zh
Publication of CN109037040A publication Critical patent/CN109037040A/zh
Application granted granted Critical
Publication of CN109037040B publication Critical patent/CN109037040B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及提高双大马士革刻蚀次沟槽工艺窗口的方法,涉及半导体集成电路制造技术,包括S1:在硅片上依次淀积底部刻蚀阻挡层、下层氧化物介质层、中间刻蚀阻挡层及上层氧化物介质层,并进行薄膜沉淀及孔洞刻蚀工艺,形成孔洞,之后进行光阻塞沉淀工艺,形成光阻塞;S2:进行所述光阻塞回刻;S3:涂光阻,进行光阻刻蚀,形成沟槽图形;S4:以所述光阻为掩膜,通过刻蚀工艺形成所述沟槽,刻蚀工艺完成后所述光阻塞高于所述中间刻蚀阻挡层的顶部,且在所述光阻塞的两侧形成突出阻塞;S5:光阻塞回刻,所述突出阻塞暴露;S6:刻蚀以去除所述突出阻塞;S7:去所述光阻及所述光阻塞;S8:进行所述底部刻蚀阻挡层刻蚀,以提高次沟槽的工艺窗口。

Description

提高双大马士革刻蚀次沟槽工艺窗口的方法
技术领域
本发明涉及一种半导体集成电路制造技术,尤其涉及一种提高双大马士革刻蚀次沟槽工艺窗口的方法。
背景技术
在半导体集成电路制造过程中,双大马士革刻蚀工艺是顶层刻蚀常见的刻蚀工艺。请参阅图1a至图1f,图1a至图1f分别为现有技术的双大马士革刻蚀工艺过程示意图,如图1a所示,在硅片上依次淀积底部刻蚀阻挡层410、下层氧化物介质层210、中间刻蚀阻挡层420及上层氧化物介质层220,并进行薄膜沉淀及孔洞刻蚀工艺,形成孔洞900,之后进行光阻塞沉淀工艺,形成光阻塞100;如图1b所示,进行光阻塞回刻;如图1c所示,涂光阻500,进行光阻刻蚀;如图1d所示,以光阻500为掩膜,进行沟槽800刻蚀,为了避免栅栏的产生,通常刻蚀过程控制光阻塞100的高度比沟槽800底部低,对于中间刻蚀阻挡层420和下层氧化物介质层210的保护有所欠缺,中间刻蚀阻挡层420的边缘被刻蚀,致使暴露出下层氧化物介质层210,等离子轰击下层氧化物介质层210时,由于孔洞900顶角处的两个面都暴露出来,导致容易产生次沟槽700;如图1e所示,进行去光阻及光阻塞100;如图1f所示,进行底部刻蚀阻挡层410刻蚀。在现有应用中,只能减少次沟槽700,却无法杜绝,导致次沟槽工艺窗口很小。
因此在半导体集成电路制造过程中,需要一种提高双大马士革刻蚀次沟槽工艺窗口的方法。
发明内容
本发明的目的在于提供一种提高双大马士革刻蚀次沟槽工艺窗口的方法,以提高双大马士革刻蚀次沟槽的工艺窗口。
本发明提供的提高双大马士革刻蚀次沟槽工艺窗口的方法,包括:S1:在硅片上依次淀积底部刻蚀阻挡层、下层氧化物介质层、中间刻蚀阻挡层及上层氧化物介质层,并进行薄膜沉淀及孔洞刻蚀工艺,形成孔洞,之后进行光阻塞沉淀工艺,形成光阻塞;S2:进行所述光阻塞回刻;S3:涂光阻,进行光阻刻蚀,形成沟槽图形;S4:以所述光阻为掩膜,通过刻蚀工艺形成所述沟槽,刻蚀工艺完成后所述光阻塞高于所述中间刻蚀阻挡层的顶部,且在所述光阻塞的两侧形成突出阻塞;S5:光阻塞回刻,所述突出阻塞暴露;S6:刻蚀以去除所述突出阻塞;S7:去所述光阻及所述光阻塞;以及S8:进行所述底部刻蚀阻挡层刻蚀。
更进一步的,所述步骤S4中所述沟槽止于所述中间刻蚀阻挡层。
更进一步的,所述步骤S4中所述突出阻塞位于所述中间刻蚀阻挡层之上。
更进一步的,所述步骤S4中所述突出阻塞由残留的所述上层氧化物介质层构成。
更进一步的,所述步骤S4中所述突出阻塞为三角形结构。
更进一步的,所述步骤S5中进行光阻塞回刻,以使所述光阻塞低于所述中间刻蚀阻挡层的顶部。
更进一步的,所述步骤S6中需要程式刻蚀所述突出阻塞对所述中间刻蚀阻挡层的选择比大于5。
更进一步的,所述中间刻蚀阻挡层为氮化物材料。
更进一步的,所述突出阻塞为氧化物
材料。
更进一步的,所述步骤S4中刻蚀工艺完成后所述光阻塞比所述中间刻蚀阻挡层的顶部高
Figure GDA0001794061330000031
之间。
更进一步的,所述步骤S5中进行所述光阻塞回刻,使所述光阻塞比所述中间刻蚀阻挡层的顶部低
Figure GDA0001794061330000032
之间。
本发明提供的提高双大马士革刻蚀次沟槽工艺窗口的方法,在双大马士革刻蚀工艺中通过提高光阻塞高度,使其产生突出阻塞,来保护刻蚀阻挡层和下层氧化物介质层,再在之后的工艺程式中加入光阻塞高度降低和突出阻塞去除步骤,提高了次沟槽的工艺窗口。
附图说明
图1a至图1f分别为现有技术的双大马士革刻蚀工艺过程示意图。
图2a至图2h分别为本发明一实施例的双大马士革刻蚀工艺过程示意图。
具体实施方式
下面将结合附图,对本发明中的技术方案进行清楚、完整的描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
本发明一实施例中,提供一种提高双大马士革刻蚀次沟槽工艺窗口的方法,请参阅图2a至图2h,图2a至图2h分别为本发明一实施例的双大马士革刻蚀工艺过程示意图。本发明的一实施例的提高双大马士革刻蚀次沟槽工艺窗口的方法包括以下步骤:
S1:在硅片上依次淀积底部刻蚀阻挡层、下层氧化物介质层、中间刻蚀阻挡层及上层氧化物介质层,并进行薄膜沉淀及孔洞刻蚀工艺,形成孔洞,之后进行光阻塞沉淀工艺,形成光阻塞。具体的,如图2a所示,在硅片上依次淀积底部刻蚀阻挡层410、下层氧化物介质层210、中间刻蚀阻挡层420及上层氧化物介质层220,并进行薄膜沉淀形成孔洞图形,之后进行孔洞刻蚀工艺,形成孔洞900,之后进行光阻塞沉淀工艺,具体的,在孔洞900中及上层氧化物介质层220之上沉淀光阻塞材料,形成光阻塞100。
S2:进行光阻塞回刻。如图2b所示,进行光阻塞100回刻,使光阻塞100低于上层氧化物介质层220的顶部221。
S3:涂光阻,进行光阻刻蚀,形成沟槽图形。如图2c所示,在上层氧化物介质层220上涂光阻500,进行光阻刻蚀,形成沟槽图形。
S4:以光阻为掩膜,通过刻蚀工艺形成沟槽,刻蚀工艺完成后光阻塞高于中间刻蚀阻挡层的顶部,且在光阻塞的两侧形成突出阻塞。如图2d所示,以光阻500为掩膜,通过干法或湿法刻蚀工艺形成沟槽800,沟槽800止于中间刻蚀阻挡层420,光阻塞100高于中间刻蚀阻挡层420的顶部421,即高于沟槽800底部,且在中间刻蚀阻挡层420之上及光阻塞100的两侧形成突出阻塞600。在本发明一实施例中,突出阻塞600由残留的上层氧化物介质层220构成。在本发明一实施例中,突出阻塞为三角形结构。在本发明一实施例中,刻蚀工艺完成后光阻塞100比中间刻蚀阻挡层420的顶部421高
Figure GDA0001794061330000041
之间。
S5:光阻塞回刻,突出阻塞暴露。如图2e所示,光阻塞100回刻,使光阻塞100低于中间刻蚀阻挡层420的顶部421,突出阻塞600暴露出来。
在本发明一实施例中,进行光阻塞100回刻,使光阻塞100比中间刻蚀阻挡层420的顶部421低
Figure GDA0001794061330000042
之间。
S6:刻蚀以去除突出阻塞。如图2f所示,在本发明一实施例中,通过使用炭氟气体和氧气去除突出阻塞。且在本发明一实施例中,需要程式刻蚀突出阻塞600(即氧化物)对中间刻蚀阻挡层420(即氮化物)的选择比大于5,以使在去除突出阻塞时中间刻蚀阻挡层420的边缘不被刻蚀,以保护下层氧化物介质层210,如此减小次沟槽,更优的避免次沟槽的产生,以提高次沟槽的工艺窗口。
S7:去光阻及光阻塞。如图2g所示,为去光阻500及光阻塞100之后的示意图。
S8:进行底部刻蚀阻挡层刻蚀。如图2h所示进行底部刻蚀阻挡层410刻蚀,形成双大马士革结构。
在本发明一实施例中,光阻塞100可为底部抗反射涂层材料、氮化硅,碳氮化硅,氮氧化硅等材料;底部刻蚀阻挡层410和中间刻蚀阻挡层420为氮化硅、碳氮化硅及氮氧化硅等氮化物材料;下层氧化物介质层210和上层氧化物介质层220为二氧化硅及其掺杂材料等氧化物材料;同样的,突出阻塞600为二氧化硅及其掺杂材料等氧化物材料。
本发明一实施例中,双大马士革刻蚀工艺中通过提高光阻塞高度,使其产生突出阻塞,来保护刻蚀阻挡层和下层氧化物介质层,再在之后的工艺程式中加入光阻塞高度降低和突出阻塞去除步骤,提高了次沟槽的工艺窗口。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (7)

1.一种提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,包括:
S1:在硅片上依次淀积底部刻蚀阻挡层、下层氧化物介质层、中间刻蚀阻挡层及上层氧化物介质层,并进行薄膜沉淀及孔洞刻蚀工艺,形成孔洞,之后进行光阻塞沉淀工艺,形成光阻塞;
S2:进行所述光阻塞回刻;
S3:涂光阻,进行光阻刻蚀,形成沟槽图形;
S4:以所述光阻为掩膜,通过刻蚀工艺形成所述沟槽,所述沟槽止于所述中间刻蚀阻挡层,刻蚀工艺完成后所述光阻塞高于所述中间刻蚀阻挡层的顶部,并在中间刻蚀阻挡层之上及光阻塞的两侧由残留的所述上层氧化物介质层形成突出阻塞;
S5:光阻塞回刻,所述突出阻塞暴露;
S6:刻蚀以去除所述突出阻塞,其中在该步骤S6中需要程式刻蚀所述突出阻塞对所述中间刻蚀阻挡层的选择比大于5;
S7:去所述光阻及所述光阻塞;以及
S8:进行所述底部刻蚀阻挡层刻蚀。
2.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述步骤S4中所述突出阻塞为三角形结构。
3.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述步骤S5中进行光阻塞回刻,以使所述光阻塞低于所述中间刻蚀阻挡层的顶部。
4.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述中间刻蚀阻挡层为氮化物材料。
5.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述突出阻塞为氧化物材料。
6.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述步骤S4中刻蚀工艺完成后所述光阻塞比所述中间刻蚀阻挡层的顶部高
Figure FDA0002646653090000021
Figure FDA0002646653090000022
之间。
7.根据权利要求1所述的提高双大马士革刻蚀次沟槽工艺窗口的方法,其特征在于,所述步骤S5中进行所述光阻塞回刻,使所述光阻塞比所述中间刻蚀阻挡层的顶部低
Figure FDA0002646653090000023
之间。
CN201810768565.2A 2018-07-13 2018-07-13 提高双大马士革刻蚀次沟槽工艺窗口的方法 Active CN109037040B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810768565.2A CN109037040B (zh) 2018-07-13 2018-07-13 提高双大马士革刻蚀次沟槽工艺窗口的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810768565.2A CN109037040B (zh) 2018-07-13 2018-07-13 提高双大马士革刻蚀次沟槽工艺窗口的方法

Publications (2)

Publication Number Publication Date
CN109037040A CN109037040A (zh) 2018-12-18
CN109037040B true CN109037040B (zh) 2021-02-02

Family

ID=64641046

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810768565.2A Active CN109037040B (zh) 2018-07-13 2018-07-13 提高双大马士革刻蚀次沟槽工艺窗口的方法

Country Status (1)

Country Link
CN (1) CN109037040B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109727859A (zh) * 2018-12-29 2019-05-07 上海华力微电子有限公司 多层结构的顶部膜层的去除方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020061047A (ko) * 2001-01-12 2002-07-22 주식회사 하이닉스반도체 듀얼 다마신 형성 방법
WO2005029556A2 (en) * 2003-09-19 2005-03-31 Brewer Science Inc. Method of filling structures for forming via-first dual damascene interconnects
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
TW200837877A (en) * 2007-03-01 2008-09-16 United Microelectronics Corp Method of forming composite opening and method of dual damascene process using the same
CN101937869A (zh) * 2009-06-30 2011-01-05 上海华虹Nec电子有限公司 无介质膜栅栏残留风险的大马士革工艺集成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
KR20020061047A (ko) * 2001-01-12 2002-07-22 주식회사 하이닉스반도체 듀얼 다마신 형성 방법
WO2005029556A2 (en) * 2003-09-19 2005-03-31 Brewer Science Inc. Method of filling structures for forming via-first dual damascene interconnects
TW200837877A (en) * 2007-03-01 2008-09-16 United Microelectronics Corp Method of forming composite opening and method of dual damascene process using the same
CN101937869A (zh) * 2009-06-30 2011-01-05 上海华虹Nec电子有限公司 无介质膜栅栏残留风险的大马士革工艺集成方法

Also Published As

Publication number Publication date
CN109037040A (zh) 2018-12-18

Similar Documents

Publication Publication Date Title
US9887350B2 (en) MTJ etching with improved uniformity and profile by adding passivation step
JP5122106B2 (ja) 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法
US7141460B2 (en) Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers
KR100954107B1 (ko) 반도체 소자의 제조방법
CN100517576C (zh) 半导体器件的制造方法
JP2009164553A (ja) フラッシュメモリ素子及びその製造方法
US11329218B2 (en) Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices
WO2007116515A1 (ja) 半導体装置及びその製造方法、ドライエッチング方法、並びに配線材料の作製方法
CN109037040B (zh) 提高双大马士革刻蚀次沟槽工艺窗口的方法
KR100714287B1 (ko) 반도체 소자의 패턴 형성방법
US8125069B2 (en) Semiconductor device and etching apparatus
TWI287258B (en) Method for fabricating semiconductor device
US20090102025A1 (en) Semiconductor device and method for manufacturing the same, dry-etching process, method for making electrical connections, and etching apparatus
KR100390040B1 (ko) 반도체소자의 듀얼게이트 제조방법
KR100862315B1 (ko) 마스크 리워크 방법
JPH10189594A (ja) 半導体素子の金属配線形成方法
KR20060122578A (ko) 반도체 메모리 소자의 하드 마스크 형성방법
TWI449085B (zh) 半導體元件的製程方法
KR20070096600A (ko) 반도체 소자의 제조방법
KR20050001104A (ko) 반도체소자 제조 방법
KR20090067596A (ko) 반도체 소자 제조 방법
KR100576438B1 (ko) 반도체 소자 제조 방법
KR100895230B1 (ko) 반도체 장치 및 그 제조 방법, 건식 에칭 방법 및 건식 에칭 장치, 그리고 배선 재료의 제작 방법
KR100838483B1 (ko) 반도체 소자의 게이트 식각방법
JP2008016852A (ja) フラッシュメモリ素子の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant