CN105122436B - 一种半导体封装件及在其上形成半导体接合区的方法 - Google Patents

一种半导体封装件及在其上形成半导体接合区的方法 Download PDF

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CN105122436B
CN105122436B CN201480022044.2A CN201480022044A CN105122436B CN 105122436 B CN105122436 B CN 105122436B CN 201480022044 A CN201480022044 A CN 201480022044A CN 105122436 B CN105122436 B CN 105122436B
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拉梅什·科塔达帕尼
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Materion Corp
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Abstract

通过在安装晶片(52,54)之前利用定位焊(点焊)至封装件(12)的片状预制体(14)来减少将半导体晶片(52,54)焊接至电子封装件(12)所需的金量。将仅略大于要附接至封装件(12)的半导体晶片(52,54)的预制体(14)放置在晶片接合位置(16)处，并在两个间隔的位置(18)处将该预制体(14)定位焊(点焊)至封装件(12)。预制体(14)包括金或诸如AuSn或AuGe之类的金合金。

Description

一种半导体封装件及在其上形成半导体接合区的方法
背景技术
本公开涉及将半导体芯片晶片接合(die bond)至陶瓷或金属，更具体地，涉及利用金晶片接合片状预制体将半导体芯片晶片接合至半导体封装件。
将半导体芯片晶片接合至封装件或座(header)通常涉及利用金合金对半导体封装件进行金属化并将晶片接合至基板。对于功率器件(例如，需要高质量晶片接合以从封装件散热并且在一些情况下在晶片的底部和晶片接合区域之间提供低阻抗界面的功率器件)，晶片接合极其重要。
对于封装件制造商，在半导体封装件上所镀的金的量是封装件成本的重要因素。封装件上金层的厚度必须足够提供用于晶片附接工艺的牢固接合表面。此外，当制造晶片时同一制造商晶片类型的变化影响晶片接合。
因此，应当认识到的是，高度期望的是在仍旧保持相当水平的性能的同时比传统封装件需要更少金的封装件。
此外，还高度期望的是能够容易地调整晶片接合区域处金的厚度以适应晶片类型和其他特征的变化的封装件。
通过引用并入
通过引用将发明人为Jech David和Kothandapani Ramesh、申请人为WilliamsAdvanced Materials Inc.、国际申请号为 PCT/US2007/080552的WIPO专利公布WO200804577并入本文。
发明内容
根据本公开的一个方面，在封装件上形成晶片接合区的方法包括：形成晶片接合片状预制体；将该晶片接合片状预制体放置在半导体封装件的晶片接合区域上；以及在一个以上的位置处将晶片接合片状预制体定位接合至半导体封装件。
根据本公开，进一步地，使用金锡晶片接合片状预制体。
根据本公开，进一步地，金锡晶片接合片状预制体大约13μm (0.0005英寸)厚。
根据本公开，进一步地，通过电阻焊接借助于具有仅一个主电流峰的焊接电流波形的电流来将预制体定位接合至封装件。
根据另一方面，在半导体封装件上形成半导体接合区的方法包括如下步骤：形成具有宽度、长度和实质均匀厚度的含金的晶片接合片状预制体；将晶片接合片状预制体放置在半导体封装件上的晶片接合区域上；以及在两个间隔的点处将晶片接合片状预制体焊接至封装件的晶片接合区域，所述两个间隔的点的总面积大大小于片状预制体的面积。
晶片接合片状预制体可含有金和锡。晶片接合片状预制体可为约13μm厚。可将晶片接合片状预制体轧制为13μm的最终厚度。可利用具有仅一个主电流峰的焊接电流波形通过电流电阻焊接将晶片接合片状预制体焊接至封装件的晶片接合区域。将晶片接合片状预制体焊接至封装件的晶片接合区域包括：使用具有非常小的接触区域 (约0.3mm至0.5mm)的工作电极。所述方法可进一步包括：将晶片放置在晶片接合片状预制体上；以及通过至少部分地熔化晶片接合片状预制体而将所述晶片附接至封装件的晶片接合区域。晶片接合片状预制体可以略微大于晶片的覆盖区。焊点的总面积可约为0.4mm至 0.7mm。
根据另一方面，半导体封装件包括：铜钨底座，其具有晶片接合区；以及含有金和锡的晶片接合片，其在彼此间隔的至少两个位置处焊接至底座的晶片接合区。
晶片接合片可以为具有约13μm厚度的预制体。晶片接合片可点焊至底座的晶片接合区。所述至少两个位置可包括具有约6.20mm ×2.39mm的面积的焊点。
根据又一方面，半导体封装件通过如下步骤形成：形成具有宽度、长度和实质均匀厚度的含金的晶片接合片状预制体；将晶片接合片状预制体放置在半导体封装件上的晶片接合区域上；在两个间隔的点处将晶片接合预制体焊接至封装件的晶片接合区域，所述两个间隔的点的总面积大大小于片状预制体的面积。
晶片接合片状预制体可为约13μm厚。可将晶片接合片状预制体轧制为最终厚度。可利用具有仅一个主电流峰的焊接电流波形通过电流电阻焊接将晶片接合片状预制体焊接至晶片接合区域。可将晶片接合片状预制体点焊至晶片接合区域。所述至少两个点可包括具有约 0.4mm至0.7mm的面积的焊点。
附图说明
参照附图对本公开进行描述，其中：
图1是根据本公开的具有金晶片接合预制体的准备好接收半导体芯片或晶片的示例封装件的顶视图；
图2是图1的陶瓷封装件和将金晶片接合条点焊至陶瓷封装件的方法的电学示意的组合截面图；
图3是图1的陶瓷封装件的顶视图，其中半导体芯片或晶片接合至该陶瓷封装件；
图4是准备好接收半导体芯片或晶片的第二示例封装件的顶视图，其中金锡预制体在恰当位置；和
图5是准备好接收半导体芯片或晶片的第三示例封装件的顶视图，其中金锡预制体在恰当位置。
在整个附图中相应的参考标记指示相应的部分。附图中的元素不必按比例绘制，以更好地示出本公开的特征。这里示出的示例示出了本公开的一个实施例，而不应当解释为以任何方式对本公开的范围进行限制。
具体实施方式
参考图1，本公开的一个示例性实施例10包括双芯片封装件12，其具有附接至晶片接合区域16的矩形的金或金合金(诸如AuSn和 AuGe)的晶片接合片状预制体14。晶片接合片状预制体14通过定位焊点18固定，其中针对每个晶片接合片状预制体14设置两个间隔的焊点。尽管示出的是两个间隔的焊点，但是应当认识到的是，根据应用，可以使用更多或更少的焊点。然而，在大多数应用中，如所示的两个间隔的焊点是优选的。每个晶片接合片状预制体14是将要在后续步骤中用来将晶片接合至封装件12的接合体。
所示的封装件12(有时称作座)具有用于安装两个晶片的位置。其他封装件或座具有用于安装仅单个半导体晶片或两个以上晶片的位置。这种单个或多个位置的座在不同场合相等地用在本公开中。
示例性封装件或座12是铜钨混合体，在座中常用来提供导电性、导热性和耐热性。封装件12具有水平构件20，其跨越封装件12的宽度并且与陶瓷上的导电区域22和24电连接。两个上部引线26和 28电连接且热连接至封装件上的导电区域30和32。导电区域30和32包括晶片接合区域16。两个下部引线34和36电连接且热连接至导电区域38和40。
本公开的一个示例性应用是将氮化镓半导体晶片安装至铜钨封装件12。在将金锡混合体用作接合材料(例如，金锡预制体)的情况下，更好地将氮化镓接合至铜钨合金。
金锡晶片接合片状预制体的厚度应当足够用于可靠地将半导体晶片晶片接合至封装件12。例如，优选的厚度为大约13μm(0.0005 英寸)。金锡晶片接合片状预制体的尺寸与晶片的尺寸大约相同或者通常仅略微大于要安装的晶片的底部，从而最小化用金量。
与传统技术(包括向更大区域镀金的技术)相比，根据本公开，将晶片安装在封装件上而使用的金量更少。此外，与电镀工艺相比，本公开用时更少且成本更低。相应地，取消电镀工艺降低了成本。根据本公开描述的工艺可以用于未镀金或仅非常薄地镀金的座和封装件。金锡片状预制体的使用在利用最少量的金的情况下提供了可靠的晶片接合。
现在转至图2，通过定位焊点18将预制体14附接至封装件12。将认识到的是，定位焊点18应当足够牢固以在将晶片附接至封装件之前保持金锡晶片接合片状预制体14附接至封装件12。利用具有焊接电极46(在图2中示意性地示出仅一个)、电源48和工件接触部50的定位焊机来形成定位焊点18。工件接触部50压到适当的引线 26或28上并且电极46压到定位焊点位置18处相应的金锡晶片接合预制体14上，如图2所示。焊接电极46具有工作端部，当对着预制体14时，其具有非常小的接触区域(例如，1mm至1.5mm)。这在预制体14和封装件12之间创建了非常小的焊点18。
申请人发现，焊点18可以非常小，并且因为在每个预制体14 中创建了两个间隔的焊点，因此其仍然可以将预制体保持在恰当位置。两个小的、间隔的焊点18可靠地将预制体14保持在恰当位置，从而防止预制体14相对于封装件12的横向和旋转移动。在一个实施例中，焊点大约为0.3mm至0.5mm。
根据本公开使用的金锡片本来是金和锡的均匀混合体。金锡箔或片会被熔融和再凝固改变。例如，金和锡会通过有时被称作相分离的方式而分离。如果用于将晶片接合至封装件的金锡片的一大部分发生了相分离，则可能连累接合成为不稳定点。
将认识到的是，当附接晶片时，金晶片接合片状预制体必须至少部分地熔化并接合至晶片和封装件两者。相应地，应当小心操作以最小化点焊过程中的相分离问题。
根据本公开，相分离问题通过如下方式来最小化：1)仅创建非常小的焊接区域(熔融区域)，以及2)向电极施加单个主电流峰的焊接电流。执行双脉冲电阻焊接来将金锡预制体接合到封装件上。
在一些点焊方法中，在预期用于创建焊点的电流之前施加预热电流。申请人发现，这些方法会导致金锡预制体的相分离问题。
根据本公开，申请人在点焊工艺过程中将电流集中在一个峰中，从而避免在其他点焊技术中出现的相分离问题。
图3示出了在将半导体芯片52和54晶片接合至封装件12上后的封装件12。在一个特定实施例中，芯片52和54覆盖了晶片接合片状预制体14的大约98％的面积。
尽管图中示出的金锡晶片接合片状预制体是矩形的，但是该预制体将通常成形为晶片的底部轮廓。实际上，根据本公开，可以使用任何期望形状的预制体。
图4和图5示出了附接有金锡预制体的封装件或座的示例。例如，首先将金锡片轧制或以其他方式处理为13μm厚的薄片。然后，将金锡片切割为适合待安装晶片的尺寸。例如，20mm×1.2mm尺寸的晶片可能需要2.1mm×1.3mm尺寸的预制体。用于所有尺寸的厚度可以保持为13μm。这种尺寸的预制体具有足够用于这种尺寸的晶片的接合体体积。
将认识到的是，应当将预制体14精确地放置在晶片将要安装至封装件12的位置，使得接合体(金锡)在其能够用于接合的位置。相应地，在预制体附接中使用非常严格的公差。这在放置晶片以附接时变得非常重要。通常，在不施加压力的情况下将晶片放置在封装件或座上。如果其上放置晶片的预制体未被固定住，则晶片可能移动。在所示实施例中，通过定位焊点将预制体保持在恰当位置，使得晶片不会移动并且被安装在其预期位置处。
如上所述，由于对于可靠地将芯片晶片接合至封装件，无需对整个封装件充分地镀金，因此与诸如电镀之类的其他方法相比，极大地减少了封装件(包括金锡晶片接合片状预制体)上使用的金的总量。由于制造定制厚度的金晶片接合片状预制体的成本大大少于制造具有定制厚度的镀金的封装件，因此降低了用于新晶片类型的每种封装件的成本，这对于半导体制造商的小封装件订单而言可以更加显著。
尽管已参照特定实施例对本公开进行了描述，但是本领域技术人员将认识到的是，可以在不脱离本公开的范围的情况下做出各种改变并且其要素可以替换为等价物。此外，可以在不脱离本公开的范围的情况下做出许多修改以使特定情形或材料适应于本公开的教导。
因此，并非意在将本公开限制为作为为了实现本公开而设想的最佳模式而公开的特定实施例，而是本公开将包括落入所附权利要求及其等价物的范围和精神内的所有实施例。

Claims (9)

1.一种在包括铜钨底座的半导体封装件上形成半导体接合区的方法，包括步骤：
形成具有宽度、长度和均匀厚度的含金的晶片接合片状预制体；
将所述晶片接合片状预制体放置在半导体封装件上的晶片接合区域上；和
在两个间隔的点处将所述晶片接合片状预制体焊接至所述晶片接合区域，
其中，所述半导体封装件未镀金；
所述晶片接合片状预制体本来是金和锡的均匀混合体，所述金和锡的均匀混合体容易通过熔融和再凝固而在金和锡之间发生相分离；并且
利用具有仅一个主电流峰的焊接电流波形通过电流电阻焊接来将所述晶片接合片状预制体焊接至所述晶片接合区域以最小化所述相分离，其中，在预期用于创建焊点的电流之前不施加预热电流。
2.根据权利要求1所述的方法，其中所述晶片接合片状预制体具有13μm的厚度。
3.根据权利要求2所述的方法，其中所述晶片接合片状预制体被轧制为13μm的厚度。
4.根据权利要求1或2所述的方法，进一步包括将晶片放置在所述晶片接合片状预制体上。
5.根据权利要求4所述的方法，进一步包括通过至少部分地熔化所述晶片接合片状预制体将晶片附接至所述晶片接合区域。
6.一种半导体封装件，包括铜钨底座，并且通过如下步骤形成：
形成具有宽度、长度和均匀厚度的含金的晶片接合片状预制体；
将所述晶片接合片状预制体放置在半导体封装件上的晶片接合区域上；
在两个间隔的点处将所述晶片接合片状预制体焊接至所述晶片接合区域，
其中，所述半导体封装件未镀金；
所述晶片接合片状预制体本来是金和锡的均匀混合体，所述金和锡的均匀混合体容易通过熔融和再凝固而在金和锡之间发生相分离；并且
利用具有仅一个主电流峰的焊接电流波形通过电流电阻焊接来将所述晶片接合片状预制体焊接至所述晶片接合区域以最小化所述相分离，其中，在预期用于创建焊点的电流之前不施加预热电流。
7.根据权利要求6所述的半导体封装件，其中所述晶片接合片状预制体具有13μm的厚度。
8.根据权利要求6或7所述的半导体封装件，其中所述晶片接合片状预制体被轧制为13μm的厚度。
9.根据权利要求6所述的半导体封装件，其中所述晶片接合片状预制体点焊至晶片接合区域。
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