CN105103454B - 模块化且可扩展的循环冗余校验计算电路 - Google Patents

模块化且可扩展的循环冗余校验计算电路 Download PDF

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Publication number
CN105103454B
CN105103454B CN201480015715.2A CN201480015715A CN105103454B CN 105103454 B CN105103454 B CN 105103454B CN 201480015715 A CN201480015715 A CN 201480015715A CN 105103454 B CN105103454 B CN 105103454B
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cyclic
redundancy
crc
unit
data packet
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CN105103454A (zh
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蒋蔚荣
高登·J·布莱诺
马克·B·卡尔森
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Xilinx Inc
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Xilinx Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
CN201480015715.2A 2013-03-15 2014-03-14 模块化且可扩展的循环冗余校验计算电路 Active CN105103454B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/841,574 US9350385B2 (en) 2013-03-15 2013-03-15 Modular and scalable cyclic redundancy check computation circuit
US13/841,574 2013-03-15
PCT/US2014/029554 WO2014144941A1 (en) 2013-03-15 2014-03-14 Modular and scalable cyclic redundancy check computation circuit

Publications (2)

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CN105103454A CN105103454A (zh) 2015-11-25
CN105103454B true CN105103454B (zh) 2019-03-29

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US (1) US9350385B2 (enExample)
EP (1) EP2974036B1 (enExample)
JP (1) JP6220045B2 (enExample)
KR (1) KR102068384B1 (enExample)
CN (1) CN105103454B (enExample)
WO (1) WO2014144941A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9542261B2 (en) * 2013-07-01 2017-01-10 Ixia Methods, systems, and computer readable media for multi-packet cyclic redundancy check engine
US9684580B2 (en) 2013-11-05 2017-06-20 Ixia Methods, systems, and computer readable media for efficient scrambling of data for line rate transmission in high speed communications networks
US9471416B2 (en) * 2014-02-28 2016-10-18 Cavium, Inc. Partitioned error code computation
US9787434B2 (en) * 2014-12-11 2017-10-10 Mediatek Inc. Cyclic redundancy check device and method
DE102015004580A1 (de) * 2015-04-14 2016-10-20 Airbus Defence and Space GmbH Übertragungsverfahren und Vorrichtungen zur Übertragung
CN105099466B (zh) * 2015-08-17 2018-04-17 中国航天科技集团公司第九研究院第七七一研究所 一种用于128位并行数据的crc校验矩阵生成方法
DE102017208826A1 (de) * 2017-05-24 2018-11-29 Wago Verwaltungsgesellschaft Mbh Eingebettete zyklische Redundanzprüfungswerte
US10812103B1 (en) 2018-02-23 2020-10-20 Xilinx, Inc. Cyclic redundancy check engine and method therefor
US10652162B2 (en) * 2018-06-30 2020-05-12 Intel Corporation Scalable packet processing
IT201900007371A1 (it) * 2019-05-27 2020-11-27 St Microelectronics Srl Circuito di Cyclic Redundancy Check, dispositivo e procedimento corrispondenti
CN110377452A (zh) * 2019-07-19 2019-10-25 上海燧原智能科技有限公司 一种循环冗余校验数据的处理方法、循环冗余校验电路及存储介质
CN111082810B (zh) * 2020-01-07 2023-03-31 西安电子科技大学 一种基于fpga低开销并行循环冗余校验方法及应用
FR3108812B1 (fr) * 2020-03-30 2022-03-18 Kalray Circuit de calcul de CRC rapide utilisant un polynôme réducteur reconfigurable au vol
US12088411B2 (en) 2022-08-25 2024-09-10 Semiconductor Components Industries, Llc Cyclic redundancy check (CRC) generation
CN117271201B (zh) * 2023-11-22 2024-03-19 北京紫光芯能科技有限公司 循环冗余校验装置及循环冗余校验方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285076A (ja) * 2000-03-31 2001-10-12 Ando Electric Co Ltd Ｃｒｃ符号演算回路、及びｃｒｃ符号演算方法
CN1431594A (zh) * 2003-01-27 2003-07-23 西安电子科技大学 一种多通道多位并行计算crc码的方法
KR100645388B1 (ko) * 2005-11-30 2006-11-14 한국전자통신연구원 임의의 크기의 병렬 처리가 가능한 병렬 ｃｒｃ 생성 장치및 방법
CN101296053A (zh) * 2007-04-25 2008-10-29 财团法人工业技术研究院 计算循环冗余校验码之方法及系统
CN102571266A (zh) * 2011-01-04 2012-07-11 华为技术有限公司 一种传输块循环冗余校验的方法及装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3269415B2 (ja) * 1997-01-22 2002-03-25 日本電気株式会社 Ｃｒｃ演算回路
US6029186A (en) 1998-01-20 2000-02-22 3Com Corporation High speed calculation of cyclical redundancy check sums
US6810501B1 (en) * 2001-01-03 2004-10-26 Juniper Networks, Inc. Single cycle cyclic redundancy checker/generator
JP3546959B2 (ja) * 2001-05-31 2004-07-28 日本電気株式会社 Ｃｒｃ演算装置
JP3554715B2 (ja) * 2001-07-31 2004-08-18 アンリツ株式会社 誤り検出装置
US7249306B2 (en) * 2004-02-20 2007-07-24 Nvidia Corporation System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
US8095846B2 (en) * 2007-06-08 2012-01-10 Cortina Systems, Inc. Data coding apparatus and methods
US8037399B2 (en) 2007-07-18 2011-10-11 Foundry Networks, Llc Techniques for segmented CRC design in high speed networks
JP4831018B2 (ja) 2007-08-28 2011-12-07 日本電気株式会社 並列巡回符号生成装置および並列巡回符号検査装置
JP5550413B2 (ja) * 2010-03-29 2014-07-16 三菱電機株式会社 Ｃｒｃ演算回路
US8468439B2 (en) * 2011-06-02 2013-06-18 Nexus Technology, Inc. Speed-optimized computation of cyclic redundancy check codes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285076A (ja) * 2000-03-31 2001-10-12 Ando Electric Co Ltd Ｃｒｃ符号演算回路、及びｃｒｃ符号演算方法
CN1431594A (zh) * 2003-01-27 2003-07-23 西安电子科技大学 一种多通道多位并行计算crc码的方法
KR100645388B1 (ko) * 2005-11-30 2006-11-14 한국전자통신연구원 임의의 크기의 병렬 처리가 가능한 병렬 ｃｒｃ 생성 장치및 방법
CN101296053A (zh) * 2007-04-25 2008-10-29 财团法人工业技术研究院 计算循环冗余校验码之方法及系统
CN102571266A (zh) * 2011-01-04 2012-07-11 华为技术有限公司 一种传输块循环冗余校验的方法及装置

Also Published As

Publication number Publication date
EP2974036B1 (en) 2018-05-09
JP2016518750A (ja) 2016-06-23
US9350385B2 (en) 2016-05-24
KR20150130494A (ko) 2015-11-23
JP6220045B2 (ja) 2017-10-25
CN105103454A (zh) 2015-11-25
EP2974036A1 (en) 2016-01-20
KR102068384B1 (ko) 2020-01-20
US20140281844A1 (en) 2014-09-18
WO2014144941A1 (en) 2014-09-18

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