CN105097902A - 一种薄膜晶体管、阵列基板及其制备方法、显示装置 - Google Patents

一种薄膜晶体管、阵列基板及其制备方法、显示装置 Download PDF

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CN105097902A
CN105097902A CN201510319258.2A CN201510319258A CN105097902A CN 105097902 A CN105097902 A CN 105097902A CN 201510319258 A CN201510319258 A CN 201510319258A CN 105097902 A CN105097902 A CN 105097902A
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insulating barrier
preparation
thin
active layer
film transistor
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田宏伟
牛亚男
左岳平
徐文清
许晓伟
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201510319258.2A priority Critical patent/CN105097902A/zh
Publication of CN105097902A publication Critical patent/CN105097902A/zh
Priority to US15/088,385 priority patent/US20160365365A1/en
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  • Thin Film Transistor (AREA)

Abstract

本发明实施例提供了一种薄膜晶体管、阵列基板及其制备方法、显示装置，涉及显示技术领域，可有效改善与有源层相接触的绝缘层的界面缺陷，提高TFT导通时的电性能稳定性。该制备方法包括：在衬底基板上形成逐层设置且相互接触的有源层以及绝缘层的步骤；形成所述绝缘层的步骤包括：形成至少一层第一绝缘层；所述至少一层第一绝缘层中的一层与所述有源层相接触；其中，形成所述第一绝缘层的步骤包括：形成由硅氧化物构成的第一绝缘薄膜；利用含填充原子的修复源，对所述第一绝缘薄膜进行修复处理，以使所述第一绝缘薄膜中的至少部分硅悬挂键结合所述填充原子，形成第一绝缘层。用于薄膜晶体管及包括该薄膜晶体管的阵列基板、显示装置的制备。

Description

一种薄膜晶体管、阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板及其制备方法、显示装置。
背景技术
薄膜晶体管(ThinFilmTransistor，简称TFT)由于其良好的开关特性，目前已广泛应用于平板显示装置。薄膜晶体管通常由栅极、有源层、源极和漏极构成；其中，源极和漏极分设于有源层的两端且分别与有源层相接触。
在TFT中，有源层总是与一个绝缘层相邻接；其中，绝缘层的材料通常由氧化硅构成，氧化硅材料在制备过程中，在与有源层相接触的界面处会产生大量的硅悬挂键，导致界面态密度较大，使得TFT导通时产生有源层载流子迁移率下降、亚阈值电压(Vth)摆幅增大、漏电流(Ioff)增大等诸如缺陷，降低了TFT导通时的电性能稳定性。
发明内容
本发明的实施例提供一种薄膜晶体管、阵列基板及其制备方法、显示装置，可有效改善与有源层相接触的绝缘层的界面缺陷，提高TFT导通时的电性能稳定性。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面、本发明实施例提供了一种薄膜晶体管的制备方法，所述制备方法包括：在衬底基板上形成逐层设置且相互接触的有源层以及绝缘层的步骤；形成所述绝缘层的步骤包括：形成至少一层第一绝缘层；其中，所述至少一层第一绝缘层中的一层与所述有源层相接触；形成所述第一绝缘层的步骤包括：形成由硅氧化物构成的第一绝缘薄膜；利用含填充原子的修复源，对所述第一绝缘薄膜进行修复处理，以使所述第一绝缘薄膜中的至少部分硅悬挂键结合所述填充原子，形成第一绝缘层。
优选的，所述填充原子为氧原子。
进一步优选的，所述含填充原子的修复源为含氧等离子体。
进一步优选的，所述含氧等离子体为N2O等离子体和/或O2等离子体。
进一步优选的，所述形成所述第一绝缘层的步骤，具体包括：以N2O等离子体、SiH4等离子体为反应源，形成由硅氧化物构成的第一绝缘薄膜；停止SiH4等离子体的通入，在预设时间内继续通入所述N2O等离子体，利用所述N2O等离子体，对所述第一绝缘薄膜进行修复处理，以使所述第一绝缘薄膜中的硅悬挂键结合氧原子，形成所述第一绝缘层。
进一步优选的，所述预设时间为20～80s。
进一步优选的，形成的所述第一绝缘薄膜的厚度为2～10nm。
在上述基础上优选的，所述形成所述绝缘层的步骤包括：形成两层或三层所述第一绝缘层。
在上述基础上优选的，形成所述绝缘层的步骤还包括：形成远离所述有源层的第二绝缘层；其中，针对所述绝缘层位于所述有源层远离所述衬底基板一侧的情况，所述形成所述绝缘层的步骤具体包括：依次形成所述第一绝缘层、所述第二绝缘层；针对所述绝缘层位于所述有源层靠近所述衬底基板一侧的情况，所述形成所述绝缘层的步骤具体包括：依次形成所述第二绝缘层、所述第一绝缘层。
进一步优选的，所述第二绝缘层由硅氧化物和/或硅氮化物构成。
本发明实施例还提供了一种薄膜晶体管，所述薄膜晶体管包括：位于衬底基板上的逐层设置且相互接触的有源层以及绝缘层；所述绝缘层包括：至少一层第一绝缘层；其中，所述至少一层第一绝缘层中的一层与所述有源层相接触；所述第一绝缘层为利用含填充原子的修复源对第一绝缘薄膜进行修复处理得到的；所述第一绝缘薄膜由硅氧化物构成；所述修复处理用于使所述第一绝缘薄膜中的至少部分硅悬挂键结合所述填充原子。
优选的，所述填充原子为氧原子。
优选的，所述第一绝缘层的厚度为2～10nm。
优选的，所述绝缘层包括两层或三层所述第一绝缘层。
优选的，所述绝缘层还包括：远离所述有源层的第二绝缘层。
优选的，所述第二绝缘层由硅氧化物和/或硅氮化物构成。
在上述基础上优选的，所述绝缘层为所述薄膜晶体管中的栅绝缘层和/或刻蚀阻挡层。
另一方面、本发明实施例还提供了一种阵列基板的制备方法，所述制备方法包括在衬底基板上形成薄膜晶体管的步骤；所述薄膜晶体管采用上述任一项所述的制备方法获得。
本发明实施例还提供了一种阵列基板，所述阵列基板包括位于衬底基板上的如上述任一项所述的薄膜晶体管。
再一方面、本发明实施例又提供了一种显示装置，所述显示装置包括上述所述的阵列基板。
基于此，通过本发明实施例提供的上述薄膜晶体管的制备方法，在形成靠近有源层的第一绝缘层时，利用能够与构成第一绝缘层的第一绝缘薄膜中的硅悬挂键结合的填充原子，填充第一绝缘薄膜中的硅悬挂键，相当于对界面处的第一绝缘层进行了修复，避免由于界面处存在大量硅悬挂键而导致TFT导通时出现有源层中载流子迁移率下降、亚阈值电压Vth摆幅增大、漏电流Ioff增大等诸如缺陷，提高了TFT导通时的电性能稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本发明实施例提供的一种薄膜晶体管的剖面结构示意图一；
图1b为本发明实施例提供的一种薄膜晶体管的剖面结构示意图二；
图1c为本发明实施例提供的一种薄膜晶体管的剖面结构示意图三；
图1d为本发明实施例提供的一种薄膜晶体管的剖面结构示意图四；
图2为本发明实施例提供的一种薄膜晶体管的制备方法中步骤S01的结构示意图；
图3为本发明实施例提供的一种薄膜晶体管的制备方法中步骤S02的结构示意图；
图4为对应于图2中形成的第一绝缘薄膜在界面处的晶格结构示意图；
图5为对应于图3中采用填充原子R对第一绝缘薄膜310中的硅悬挂键进行填充后在界面处的晶格结构示意图；
图6a为本发明实施例提供的一种薄膜晶体管的剖面结构示意图五；
图6b为本发明实施例提供的一种薄膜晶体管的剖面结构示意图六；
图6c为本发明实施例提供的一种薄膜晶体管的剖面结构示意图七。
附图标记：
01-薄膜晶体管；10-衬底基板；20-有源层；30-绝缘层；31-第一绝缘层；310-第一绝缘薄膜；32-第二绝缘层；40-栅极；50-层间绝缘层；61-源极；62-漏极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要指出的是，除非另有定义，本发明实施例中所使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
并且，本发明专利申请说明书以及权利要求书中所使用的术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
本发明实施例提供了一种薄膜晶体管01的制备方法，该制备方法包括：如图1a或图1b所示，在衬底基板10上形成逐层设置且相互接触的有源层20以及绝缘层30的步骤；形成上述绝缘层30的步骤包括：形成至少一层第一绝缘层31；其中，至少一层第一绝缘层31中的一层与上述的有源层20相接触；其中，形成上述第一绝缘层31的步骤具体包括：
S01、如图2所示，形成由硅氧化物构成的第一绝缘薄膜310；
S02、如图3所示，利用含填充原子的修复源，对上述的第一绝缘薄膜310进行修复处理，以使第一绝缘薄膜310中的至少部分硅悬挂键结合填充原子，形成第一绝缘层31。
需要说明的是，第一、为方便理解本发明，现对本发明实施例中涉及到的“硅悬挂键”概念进行如下说明。
在材料的界面处，由于晶格在表面处突然终止或才开始形成晶格，在表面的最外层的每个原子将有一个未配对的电子，即有一个未饱和的键，这个键称为悬挂键。
如图4所示，在形成的第一绝缘薄膜310与有源层20相互接触的界面处，硅原子(Si)中存在未饱和的悬挂键(如图中虚线框所示)，由于具有未饱和悬挂键的硅原子Si能量高、体系稳定性差，其具有向能量低、体系稳定性高发展的趋势。而界面处的硅原子Si总是倾向于结合更多的原子已达到更为稳定的结构。因此，当上述TFT导通时，由于界面处存在大量的硅悬挂键，这些硅悬挂键会向有源层20掠夺原子以形成稳定结构，从而导致TFT出现有源层载流子迁移率下降、亚阈值电压Vth摆幅增大、漏电流Ioff增大等诸如缺陷，降低了TFT导通时的电性能稳定性。
而如图5所示，本发明实施例利用能够与第一绝缘薄膜310中的硅悬挂键结合的填充原子(图中及下文中均标记为R)，来填充第一绝缘薄膜310中的硅悬挂键，使得与有源层20相互接触的界面处的硅原子(Si)形成稳定的结构，从而避免上述TFT导通时出现有源层载流子迁移率下降、亚阈值电压Vth摆幅增大、漏电流Ioff增大等诸如缺陷，提高了TFT导通时的电性能稳定性。
这里，含填充原子的修复源可以为气体状物质，如等离子体(plasma)；其中，等离子体是由部分电子被剥夺后的原子及原子团被电离后产生的由正负电子组成的离子化气体状物质。
上述的填充原子R可以是任何能够与硅悬挂键结合形成具有一定稳定性的原子，例如可以为O原子、S原子等，具体不作限定。
但应当理解的是，图5所示出的对硅悬挂键进行的填充是一种理想情况，本发明及其实施例并不要求所有的硅悬挂键都被填充，只要有部分硅悬挂键被上述填充原子R所填充，则相对于现有技术而言，TFT的稳定性即得到了提高。
也即是，在本发明实施例中，可以是利用填充原子R对部分的硅悬挂键进行填充，当然也可以是对所有的硅悬挂键进行填充，可根据上述步骤S02的修复量及修复时间进行调整。
第二、上述的逐层设置且相互接触的有源层20与绝缘层30的上下相对位置可根据待形成的TFT的具体类型不同灵活调整，具体如下所述：
(1)、参考图1a所示，相对于衬底基板10而言，有源层20可以位于绝缘层30的下方，即待形成的TFT的具体类型为顶栅型(topgate，栅极位于有源层远离衬底基板的一侧)。此种情况下，上述的绝缘层30具体可以为TFT中使栅极与有源层20相互绝缘开的栅绝缘层(GateInsulation，简称GI)，或者为刻蚀阻挡层(EtchStopLayer，简称ESL)，以避免通过刻蚀等工艺在有源层20上形成源极与漏极时对有源层20产生影响。
(2)、参考图1b所示，相对于衬底基板10而言，有源层20可以位于绝缘层30的上方，即待形成的TFT的具体类型为底栅型(bottomgate，栅极位于有源层靠近于衬底基板的另一侧)。此种情况下，上述的绝缘层30具体也可以为TFT中的栅绝缘层GI，或者刻蚀阻挡层ESL。
第三、根据待形成的绝缘层30的设定厚度要求，上述步骤S01～S02可重复适当次数，即在上述绝缘层30靠近有源层20的一侧形成有数层的第一绝缘层31。
考虑到重复次数过多对硅悬挂键进行修复的效果没有显著地提高，还会延长绝缘层30整体形成工艺时间，降低生产效率。因此，上述步骤S01～S02优选地重复1～2次，即：形成的上述绝缘层30包括两层或三层上述的第一绝缘层31。
这里，以上述步骤S01～S02重复1次为例，如图1c或图1d所示，即形成的上述绝缘层30包括有两层的上述第一绝缘层31；其中，每层第一绝缘层31都经过上述的形成第一绝缘薄膜310，之后进行上述的修复过程。
其中，参考图1c所示，当相对于衬底基板10而言，有源层20位于绝缘层30的下方时，上述的两层第一绝缘层31依次位于有源层20的上方，其中相对较里侧的一层第一绝缘层31与有源层20相接触；参考图1d所示，当相对于衬底基板10而言，有源层20位于绝缘层30的上方时，上述的两层第一绝缘层31依次位于有源层20的下方，其中相对较外侧的一层第一绝缘层31与有源层20相接触。
第四、第一绝缘薄膜310由硅氧化物构成，该硅氧化物(SiOx)的化学式例如可以为SiO、SiO2、Si2O6；有源层20可以由低温多晶硅(LowTemperaturePolySilicon，LTPS)、氧化物半导体等材料构成，具体不作限定。
基于此，通过本发明实施例提供的上述制备方法，在形成靠近有源层20的第一绝缘层31时，利用能够与构成第一绝缘层31的第一绝缘薄膜310中的硅悬挂键结合的填充原子，填充第一绝缘薄膜310中的硅悬挂键，相当于对界面处的第一绝缘层31进行了修复，避免由于界面处存在大量硅悬挂键而导致TFT导通时出现有源层20中载流子迁移率下降、亚阈值电压Vth摆幅增大、漏电流Ioff增大等诸如缺陷，提高了TFT导通时的电性能稳定性。
在上述基础上，考虑到第一绝缘薄膜310为SiO、SiO2、Si2O6等硅氧化物，因此优选的，上述填充原子R采用与构成第一绝缘薄膜310相同元素的为氧原子，以提高第一绝缘薄膜310硅氧化物结构的稳定性。
进一步的，上述步骤S02具体包括，利用含氧等离子体，填充第一绝缘薄膜310中的硅悬挂键，形成第一绝缘层31。
上述的含氧等离子体可以为N2O等离子体或O2等离子体等，具体不作限定；其中，等离子体(plasma)是由部分电子被剥夺后的原子及原子团被电离后产生的由正负电子组成的离子化气体状物质。
这里，相对于衬底基板10，针对待形成的第一绝缘层31位于有源层20上方的情况，由于第一绝缘薄膜310是上述绝缘层30中在有源层20表面初步形成的部分，其内部的Si-O键处于一种不稳定的状态，而这种不稳定的状态随时有可能受到外界影响被破坏，进而形成新的硅悬挂键。而本发明实施例中，对初步形成的上述第一绝缘薄膜310进行等离子体的修复处理，利用等离子体所携带的高能量打断这些不稳定的Si-O键，形成的新的硅悬挂键就会结合含氧等离子体中的氧原子，从而形成新的稳定的Si-O键。
因此，本发明实施例更优选地适用于参考图1a所示的相对于衬底基板10而言，有源层20位于绝缘层30下方的TFT结构。
当然，上述的步骤S02具体也可以是在氧化性气氛下进行的，从而将氧原子结合到未饱和的硅悬挂键。
以含氧等离子体为N2O为例，上述形成第一绝缘层31的步骤具体可采用以下实施方式进行：
S11、参考图2所示，以N2O等离子体、SiH4等离子体为反应源，形成由硅氧化物构成的第一绝缘薄膜310；其中，上述的反应式为：
这里，考虑到形成的第一绝缘层31的绝缘性能，通过的N2O的量为通入的SiH4量的几十倍。
S12、参考图3所示，停止SiH4等离子体的通入，在预设时间内继续通入N2O等离子体，利用N2O等离子体，对第一绝缘薄膜310进行修复处理，以使第一绝缘薄膜310中的硅悬挂键结合氧原子R，形成第一绝缘层31。
这里，考虑到第一绝缘薄膜的厚度过小时，其还未稳定地形成；厚度过大时，则会削弱上述的修复作用，因此优选地，形成的第一绝缘薄膜的厚度范围优选地为2～10nm。
需要指出的是，上述的N2O等离子体为在步骤S11中形成第一绝缘薄膜310体系环境中就存在有的反应源，其浓度并未改变，因此，利用体系中本来就存在有的气氛对第一绝缘薄膜310进行修复，可以避免造成第一绝缘层31产生结构性分层的缺陷。
进一步的，上述的预设时间为20～80s；这里，由于上述步骤S12利用体系中本来就存在有的气氛对第一绝缘薄膜310进行修复，这一过程类似于现有技术中的低速沉积薄膜(通常是指沉膜速度小于)；因此，设定上述的预设时间为20～80s，不会显著延长形成上述绝缘层30的整体工艺时间，使得本发明实施例提供的上述方法可实际应用于量产技术。
进一步的，形成上述绝缘层30的步骤还包括：形成远离有源层20的第二绝缘层32。
其中，参考图1a所示，针对绝缘层30位于有源层20远离衬底基板一侧的情况，所述形成上述绝缘层30的步骤具体包括：依次形成第一绝缘层31、第二绝缘层32；其中，第二绝缘层32可以由硅氧化物和/或硅氮化物构成。
这里，针对第二绝缘层32由硅氧化物构成的情况，可以在上述步骤S11～S12之后，继续通入SiH4等离子体，以形成由SiO、SiO2、Si2O6等硅氧化物构成的第二绝缘层32。
参考图1b所示，针对绝缘层30位于有源层20靠近衬底基板一侧的情况，所述形成上述绝缘层30的步骤具体包括：依次形成第二绝缘层32、第一绝缘层31；其中，第二绝缘层32可以由硅氧化物和/或硅氮化物构成。
在上述基础上，本发明实施例还提供了一种采用上述制备方法获得的薄膜晶体管01，参考图1a或图1b所示，该薄膜晶体管01包括：位于衬底基板10上的逐层设置且相互接触的有源层20以及绝缘层30；上述的绝缘层30包括：至少一层第一绝缘层31；其中，至少一层第一绝缘层31中的一层与有源层20相接触；上述的第一绝缘层31为利用含填充原子R的修复源对第一绝缘薄膜310进行修复处理得到的；第一绝缘薄膜310由硅氧化物构成；上述的修复处理用于使第一绝缘薄膜310中的至少部分硅悬挂键结合上述的填充原子R。
进一步的，如图6a所示，当上述薄膜晶体管01的类型为顶栅型时，上述绝缘层30可以为薄膜晶体管01中的栅绝缘层GI。
具体的，该薄膜晶体管01包括依次位于衬底基板10上的有源层20、绝缘层30、栅极40、层间绝缘层(InterlayerDielectric，简称ILD)50、源极61和漏极62；其中，源极61和漏极62通过贯通层间绝缘层50和绝缘层30的过孔与有源层20相连。
或者，如图6b所示，当上述薄膜晶体管01的类型为底栅型时，上述绝缘层30同样可以为薄膜晶体管01中的栅绝缘层GI。
具体的，该薄膜晶体管01包括依次位于衬底基板10上的栅极40、绝缘层30、有源层20、源极61和漏极62。
再或者，如图6c所示，当在上述薄膜晶体管01的结构中，源极61和漏极62位于有源层20远离衬底基板一侧，且与有源层20直接相连(即无需借助过孔相连)时，由于构成图案化的源极61和漏极62通常需要经过湿法刻蚀的工艺，为了避免刻蚀工艺中的刻蚀液对有源层20对应于源极61和漏极62之间相对的区域(即TFT导通时的沟道区域)，上述绝缘层30还可以为薄膜晶体管01中的刻蚀阻挡层ESL，以对有源层20进行保护。
这里，有源层20与栅极40之间的栅绝缘层同样也可以为上述的绝缘层30，具体结构不再赘述。
本发明实施例还提供了一种阵列基板的制备方法，该制备方法包括在衬底基板10上形成上述薄膜晶体管01的步骤。
本发明实施例还提供了一种阵列基板，该阵列基板包括位于衬底基板10上的上述薄膜晶体管01。
这里，上述阵列基板当然还可包括像素电极、公共电极等结构，具体结构可沿用现有技术，在此不再赘述。
本发明实施例还提供了一种显示装置，该显示装置包括上述的阵列基板。
这里，该显示装置可以仅为显示面板，也可以为包括有显示面板的显示装置；其中，该显示装置可以为液晶面板、液晶显示装置、有机电致发光显示(OrganicLight-EmittingDisplay，OLED)面板、OLED显示装置、或电子纸、数码相框等具有任何显示功能的产品或者部件。
需要说明的是，本发明所有附图是上述薄膜晶体管及其制备方法的简略的示意图，只为清楚描述本方案体现了与发明点相关的结构，对于其他的与发明点无关的结构是现有结构，在附图中并未体现或只体现部分。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

1.一种薄膜晶体管的制备方法，其特征在于，所述制备方法包括：在衬底基板上形成逐层设置且相互接触的有源层以及绝缘层的步骤；
形成所述绝缘层的步骤包括：形成至少一层第一绝缘层；其中，所述至少一层第一绝缘层中的一层与所述有源层相接触；
形成所述第一绝缘层的步骤包括：
形成由硅氧化物构成的第一绝缘薄膜；
利用含填充原子的修复源，对所述第一绝缘薄膜进行修复处理，以使所述第一绝缘薄膜中的至少部分硅悬挂键结合所述填充原子，形成第一绝缘层。
2.根据权利要求1所述的制备方法，其特征在于，所述填充原子为氧原子。
3.根据权利要求2所述的制备方法，其特征在于，所述含填充原子的修复源为含氧等离子体。
4.根据权利要求3所述的制备方法，其特征在于，所述含氧等离子体为N2O等离子体和/或O2等离子体。
5.根据权利要求3所述的制备方法，其特征在于，所述形成所述第一绝缘层的步骤，具体包括：
以N2O等离子体、SiH4等离子体为反应源，形成由硅氧化物构成的第一绝缘薄膜；
停止SiH4等离子体的通入，在预设时间内继续通入所述N2O等离子体，利用所述N2O等离子体，对所述第一绝缘薄膜进行修复处理，以使所述第一绝缘薄膜中的硅悬挂键结合氧原子，形成所述第一绝缘层。
6.根据权利要求5所述的制备方法，其特征在于，所述预设时间为20～80s。
7.根据权利要求5所述的制备方法，其特征在于，形成的所述第一绝缘薄膜的厚度为2～10nm。
8.根据权利要求1至7任一项所述的制备方法，其特征在于，所述形成所述绝缘层的步骤包括：形成两层或三层所述第一绝缘层。
9.根据权利要求1至7任一项所述的制备方法，其特征在于，形成所述绝缘层的步骤还包括：形成远离所述有源层的第二绝缘层；
其中，针对所述绝缘层位于所述有源层远离所述衬底基板一侧的情况，所述形成所述绝缘层的步骤具体包括：
依次形成所述第一绝缘层、所述第二绝缘层；
针对所述绝缘层位于所述有源层靠近所述衬底基板一侧的情况，所述形成所述绝缘层的步骤具体包括：
依次形成所述第二绝缘层、所述第一绝缘层。
10.根据权利要求9所述的制备方法，其特征在于，所述第二绝缘层由硅氧化物和/或硅氮化物构成。
11.一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：位于衬底基板上的逐层设置且相互接触的有源层以及绝缘层；
所述绝缘层包括：至少一层第一绝缘层；其中，所述至少一层第一绝缘层中的一层与所述有源层相接触；
所述第一绝缘层为利用含填充原子的修复源对第一绝缘薄膜进行修复处理得到的；所述第一绝缘薄膜由硅氧化物构成；所述修复处理用于使所述第一绝缘薄膜中的至少部分硅悬挂键结合所述填充原子。
12.根据权利要求11所述的薄膜晶体管，其特征在于，所述填充原子为氧原子。
13.根据权利要求12所述的薄膜晶体管，其特征在于，所述第一绝缘层的厚度为2～10nm。
14.根据权利要求11所述的薄膜晶体管，其特征在于，所述绝缘层包括两层或三层所述第一绝缘层。
15.根据权利要求11所述的薄膜晶体管，其特征在于，所述绝缘层还包括：远离所述有源层的第二绝缘层。
16.根据权利要求15所述的薄膜晶体管，其特征在于，所述第二绝缘层由硅氧化物和/或硅氮化物构成。
17.根据权利要求11至16任一项所述的薄膜晶体管，其特征在于，所述绝缘层为所述薄膜晶体管中的栅绝缘层和/或刻蚀阻挡层。
18.一种阵列基板的制备方法，所述制备方法包括在衬底基板上形成薄膜晶体管的步骤；其特征在于，所述薄膜晶体管采用上述权利要求1至10任一项所述的制备方法获得。
19.一种阵列基板，其特征在于，所述阵列基板包括位于衬底基板上的如上述权利要求11至17任一项所述的薄膜晶体管。
20.一种显示装置，其特征在于，所述显示装置包括如上述权利要求19所述的阵列基板。
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