CN105097763A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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Abstract
一种半导体结构及其制造方法,该半导体结构的制造方法包含下列步骤:形成第一绝缘层于晶圆基板的第一表面;形成导电垫于第一绝缘层上;形成贯穿于晶圆基板的第一表面与第二表面的镂空区,使得第一绝缘层从镂空区裸露;以及激光蚀刻裸露于镂空区的第一绝缘层,使得第一绝缘层形成第一开口,且导电垫形成从第一开口裸露的凹部。本发明可提升半导体结构的良率,且可使导电垫的厚度得以减薄,节省成本。
Description
技术领域
本发明是有关一种半导体结构及一种半导体结构的制造方法。
背景技术
现有的半导体结构可包含具有穿孔的晶圆基板、第一绝缘层、导电垫、第二绝缘层与布线层。第一绝缘层与导电垫位于晶圆基板的表面上,且覆盖晶圆基板的穿孔的一端。当晶圆基板的表面形成第一绝缘层与导电垫后,接着一般是以光微影技术(例如干蚀刻制程)将导电垫上的第一绝缘层形成开口,使导电垫从第一绝缘层的开口露出。之后便可于第一绝缘层与其开口内的导电垫上形成第二绝缘层。接着以光微影技术将导电垫上的第二绝缘层形成开口,并于第二绝缘层与其开口内的导电垫上形成布线层,使布线层电性接触导电垫。
然而,当采用干蚀刻制程将导电垫上的第一绝缘层形成开口时,受限于制程能力,易在干蚀刻第一绝缘层时,同步于导电垫形成V形的凹槽。如此一来,当布线层电性接触导电垫时,接触面积会过小而导致接触不良,良率下降。此外,若导电垫的厚度较薄时,则容易因干蚀刻制程所形成的V形凹槽贯穿,而伤到导电垫下方的其他元件。
发明内容
本发明的一技术态样为一种半导体结构。
根据本发明一实施方式,一种半导体结构包含晶圆基板、第一绝缘层与导电垫。晶圆基板具有镂空区及相对的第一表面与第二表面。镂空区贯穿第一表面与第二表面。第一绝缘层位于晶圆基板的第一表面上。第一绝缘层具有第一开口,且第一开口连通于镂空区。导电垫位于第一绝缘层相对晶圆基板的表面上,且导电垫覆盖第一开口,使得导电垫从镂空区裸露。导电垫具有朝向第一开口的凹部。第一绝缘层具有围绕第一开口的倾斜面,使得凹部与倾斜面形成剖面形状为U形的凹槽。
在本发明一实施方式中,上述晶圆基板具有围绕镂空区的第三表面。半导体结构还包含第二绝缘层。第二绝缘层位于凹槽上及晶圆基板的第二表面与第三表面上,且第二绝缘层具有第二开口,使得导电垫从第二开口裸露。
在本发明一实施方式中,上述半导体结构还包含布线层。布线层位于第二绝缘层上,且电性接触裸露于第二开口的导电垫。
在本发明一实施方式中,上述凹槽的深度大于第一绝缘层的厚度。
本发明的另一技术态样为一种半导体结构的制造方法。
根据本发明一实施方式,一种半导体结构的制造方法包含下列步骤:形成第一绝缘层于晶圆基板的第一表面;形成导电垫于第一绝缘层上;形成贯穿于晶圆基板的第一表面与第二表面的镂空区,使得第一绝缘层从镂空区裸露;以及激光蚀刻裸露于镂空区的第一绝缘层,使得第一绝缘层形成第一开口,且导电垫形成从第一开口裸露的凹部。
在本发明一实施方式中,上述晶圆基板具有围绕镂空区的第三表面。第一绝缘层具有围绕第一开口的倾斜面。凹部与倾斜面形成凹槽。半导体结构制作方法还包含:形成第二绝缘层于凹槽上及晶圆基板的第二表面与第三表面上。
在本发明一实施方式中,上述半导体结构制作方法还包含:图案化第二绝缘层,使得第二绝缘层形成裸露导电垫的第二开口。
在本发明一实施方式中,上述图案化第二绝缘层包含:形成图案化的光阻层于第二绝缘层上;蚀刻未被光阻层覆盖的部分第二绝缘层,使得第二绝缘层形成裸露导电垫的第二开口;以及去除光阻层。
在本发明一实施方式中,上述半导体结构制作方法还包含:形成布线层于第二绝缘层上与裸露于第二开口的导电垫上。
在本发明一实施方式中,上述激光蚀刻第一绝缘层包含:提供具有穿孔的遮罩。发射激光通过遮罩的穿孔至第一绝缘层。
在本发明上述实施方式中,由于第一绝缘层是以激光蚀刻的方式形成第一开口,且在激光蚀刻第一绝缘层时,导电垫可同步形成从第一开口裸露的凹部,因此第一绝缘层会具有围绕第一开口的倾斜面,使得凹部与倾斜面可形成剖面形状为U形的凹槽。如此一来,当导电垫的表面形成与其电性接触的布线层时,U形的凹槽与布线层具有足够的接触面积而不易产生接触不良的状况,因此可提升半导体结构的良率。此外,因激光蚀刻的精度较高,可降低贯穿导电垫的风险,因此导电垫的厚度得以减薄,节省成本。
本发明的另一技术态样为一种半导体结构的制造方法。
根据本发明一实施方式,一种半导体结构的制造方法包含下列步骤:形成第一绝缘层于晶圆基板的第一表面;形成导电垫于第一绝缘层上;形成贯穿于晶圆基板的第一表面与第二表面的镂空区,使得第一绝缘层从镂空区裸露,且晶圆基板形成围绕镂空区的第三表面;形成第二绝缘层于晶圆基板的第二表面与第三表面上及裸露于镂空区的第一绝缘层上;以及激光蚀刻镂空区中的第一绝缘层与第二绝缘层,使得第一绝缘层形成第一开口,第二绝缘层形成第二开口,导电垫形成从第一开口与第二开口裸露的凹部。
在本发明一实施方式中,上述半导体结构制作方法还包含:形成布线层于第二绝缘层上及裸露于第一开口与第二开口的导电垫上。
在本发明一实施方式中,上述激光蚀刻第一绝缘层与第二绝缘层包含:提供具有穿孔的遮罩;以及发射激光通过遮罩的穿孔至第一绝缘层。
在本发明上述实施方式中,由于第一绝缘层与第二绝缘层是以激光蚀刻的方式分别形成第一开口与第二开口,且在激光蚀刻第一绝缘层与第二绝缘层时,导电垫可同步形成从第一开口与第二开口裸露的凹部。如此一来,当导电垫的表面形成与其电性接触的布线层时,U形的凹槽与布线层具有足够的接触面积而不易产生接触不良的状况,因此可提升半导体结构的良率。此外,因激光蚀刻的精度较高,可降低贯穿导电垫的风险,因此导电垫的厚度得以减薄,节省成本。
附图说明
图1绘示根据本发明一实施方式的半导体结构的俯视图。
图2绘示图1的半导体结构沿线段2-2的剖面图。
图3绘示图2的半导体结构的局部放大图。
图4绘示根据本发明一实施方式的半导体结构的制造方法的流程图。
图5绘示图4的第一绝缘层与导电垫形成于晶圆基板后的剖面图。
图6绘示图5的晶圆基板形成镂空区后的剖面图。
图7绘示图6的第一绝缘层激光蚀刻时的剖面图。
图8绘示图2的凹槽及晶圆基板形成第二绝缘层后的剖面图。
图9绘示图8的第二绝缘层形成图案化的光阻层后的剖面图。
图10绘示图9的第二绝缘层形成第二开口后的剖面图。
图11绘示图10的第二绝缘层与导电垫上形成布线层后的剖面图。
图12绘示根据本发明一实施方式的半导体结构的制造方法的流程图。
图13绘示图12的第一绝缘层、导电垫与第二绝缘层形成于晶圆基板后的剖面图。
图14绘示图13的第二绝缘层激光蚀刻时的剖面图。
图15绘示图14的第一绝缘层、第二绝缘层与导电垫被激光蚀刻后的剖面图。
其中,附图中符号的简单说明如下:
100:半导体结构100a:半导体结构
100b:半导体结构110:晶圆基板
112:镂空区114:第一表面
116:第二表面118:第三表面
120:第一绝缘层122:第一开口
124:表面126:倾斜面
130:导电垫131:凹槽
132:凹部140:第二绝缘层
142:第二开口150:光阻层
152:开口160:布线层
210:遮罩212:穿孔
2-2:线段D1:深度
D2:厚度L:激光
S1~S5:步骤。
具体实施方式
以下将以图式揭露本发明的多个实施方式,为明确说明起见,许多实务上的细节将在以下叙述中一并说明。然而,应了解到,这些实务上的细节不应用以限制本发明。也就是说,在本发明部分实施方式中,这些实务上的细节是非必要的。此外,为简化图式起见,一些现有惯用的结构与元件在图式中将以简单示意的方式绘示。
图1绘示根据本发明一实施方式的半导体结构100的俯视图。图2绘示图1的半导体结构100沿线段2-2的剖面图。同时参阅图1与图2,半导体结构100包含晶圆基板110、第一绝缘层120与导电垫130。其中,晶圆基板110具有镂空区112及相对的第一表面114与第二表面116。镂空区112贯穿第一表面114与第二表面116。第一绝缘层120位于晶圆基板110的第一表面114上。第一绝缘层120具有第一开口122,且第一开口122连通于镂空区112。导电垫130位于第一绝缘层120相对晶圆基板110的表面124上,且导电垫130覆盖第一开口122,使得导电垫130可从镂空区112裸露。导电垫130可以为电性导电垫(electricalpad)或延伸导电垫(extensionpad)。此外,U形的凹槽131形成于第一绝缘层120与导电垫130上。
图3绘示图2的半导体结构100的局部放大图。同时参阅图2与图3,导电垫130具有朝向第一开口122的凹部132。第一绝缘层120具有围绕第一开口122的倾斜面126,使得导电垫130的凹部132与第一绝缘层120的倾斜面126共同形成剖面形状为U形的凹槽131。凹槽131的形成方式是以激光蚀刻第一绝缘层120与导电垫130而产生。利用激光蚀刻所产生的凹槽131其深度D1大于第一绝缘层120的厚度D2,也就是凹槽131至少部分会延伸至导电垫130中,使导电垫130形成凹部132。
在本实施方式中,半导体结构100可用来制作影像感测元件、微机电(MEMS)系统元件、运算处理元件等,晶圆基板110的材质可以包含硅。第一绝缘层120可以为硅的氧化物,例如二氧化硅,但并不以此为限。导电垫130的材质可以包含铝、铜或其他可导电的金属,并不用以限制本发明。
在以下叙述中,将叙述上述半导体结构100的制造方法。
图4绘示根据本发明一实施方式的半导体结构的制造方法的流程图。首先在步骤S1中,形成第一绝缘层于晶圆基板的第一表面。接着在步骤S2中,形成导电垫于第一绝缘层上。之后在步骤S3中,形成贯穿于晶圆基板的第一表面与第二表面的镂空区,使得第一绝缘层从镂空区裸露。最后在步骤S4中。激光蚀刻裸露于镂空区的第一绝缘层,使得第一绝缘层形成第一开口,且导电垫形成从第一开口裸露的凹部。在以下叙述中,将说明上述半导体结构的制造方法的各步骤。
图5绘示图4的第一绝缘层120与导电垫130形成于晶圆基板110后的剖面图。如图所示,晶圆基板110具有相对的第一表面114与第二表面116。在图4步骤S1中,第一绝缘层120可形成于晶圆基板110的第一表面114上。接着在图4步骤S2中,导电垫130可形成于第一绝缘层120上。
图6绘示图5的晶圆基板110形成镂空区112后的剖面图。同时参阅图5与图6,待晶圆基板110的第一表面114形成第一绝缘层120与导电垫130后,在图4步骤S3中,便可通过光微影技术图案化晶圆基板110,使晶圆基板110形成贯穿第一表面114与第二表面116的镂空区112。其中,光微影技术例如包含光阻涂布、曝光显影与蚀刻等制程。待晶圆基板110形成镂空区112后,晶圆基板110具有围绕镂空区112的第三表面118,且第一绝缘层120从镂空区112裸露。
图7绘示图6的第一绝缘层120激光蚀刻时的剖面图。待第一绝缘层120从晶圆基板110的镂空区112裸露后,在图4步骤S4中,便可通过激光蚀刻第一绝缘层120,使得第一绝缘层120形成第一开口122(见图3),且导电垫130形成从第一开口122裸露的凹部132(见图3)。如此一来,便可得到图2的半导体结构100。
在本实施方式中,激光蚀刻第一绝缘层120的步骤包含:提供具有穿孔212的遮罩210,并将遮罩210置于晶圆基板110的上方,使遮罩210的穿孔212对准于晶圆基板110的镂空区112。接着可发射激光L通过遮罩210的穿孔212至第一绝缘层120,以形成图3的第一开口122与凹部132。
同时参阅图2与图3,由于第一绝缘层120是以激光蚀刻的方式形成第一开口122,且在激光蚀刻第一绝缘层120时,导电垫130可同步形成从第一开口122裸露的凹部132,因此第一绝缘层120会具有围绕第一开口122的倾斜面126,使得凹部132与倾斜面126可形成剖面形状为U形的凹槽131。如此一来,当导电垫130的表面形成与其电性接触的布线层时,U形的凹槽131与布线层具有足够的接触面积而不易产生接触不良的状况,因此可提升半导体结构100的良率。此外,因激光蚀刻的精度较高,可降低贯穿导电垫130的风险,因此导电垫130的厚度得以减薄,节省成本。在以下叙述中,将说明图2半导体结构100的后续制程。
图8绘示图2的凹槽131及晶圆基板110形成第二绝缘层140后的剖面图。图9绘示图8的第二绝缘层140形成图案化的光阻层150后的剖面图。同时参阅图8与图9,待第一绝缘层120与导电垫130形成U形的凹槽131后,可于凹槽131上及晶圆基板110的第二表面116与第三表面118上形成第二绝缘层140。第二绝缘层140通过喷洒涂布(spraycoating)的方式形成。第二绝缘层140可以为硅的氧化物,例如二氧化硅,但并不以此为限。接着,可于第二绝缘层140上形成图案化的光阻层150。在本实施方式中,光阻层150具有裸露第二绝缘层140的开口152。
图10绘示图9的第二绝缘层140形成第二开口142后的剖面图。同时参阅图9与图10,待图案化的光阻层150形成后,便可蚀刻未被光阻层150覆盖的部分第二绝缘层140(即位在开口152中的第二绝缘层140),使得第二绝缘层140形成裸露导电垫130的第二开口142。接着,便可去除光阻层150,而得到图10的结构。也就是说,第二绝缘层140被图案化后,形成第二开口142。
图11绘示图10的第二绝缘层140与导电垫130上形成布线层160后的剖面图。同时参阅图10与图11,待图案化的第二绝缘层140形成后,便可于第二绝缘层140上与裸露于第二开口142的导电垫130上形成布线层160。如此一来,布线层160便可电性接触裸露于第二开口142的导电垫130,而得到图11的半导体结构100a。布线层160的材质可以包含铝、铜或其他可导电的金属,并不以限制本发明。
图12绘示根据本发明一实施方式的半导体结构的制造方法的流程图。首先在步骤S1中,形成第一绝缘层于晶圆基板的第一表面。接着在步骤S2中,形成导电垫于第一绝缘层上。之后在步骤S3中,形成贯穿于晶圆基板的第一表面与第二表面的镂空区,使得第一绝缘层从镂空区裸露,且晶圆基板形成围绕镂空区的第三表面。接着在步骤S4中,形成第二绝缘层于晶圆基板的第二表面与第三表面上及裸露于镂空区的第一绝缘层上。最后在步骤S5中,激光蚀刻镂空区中的第一绝缘层与第二绝缘层,使得第一绝缘层形成第一开口,第二绝缘层形成第二开口,导电垫形成从第一开口与第二开口裸露的凹部。由于步骤S1至S3与图4相同,因此不重复赘述,在以下叙述中,将说明上述半导体结构的制造方法的步骤S4、S5。
图13绘示图12的第一绝缘层120、导电垫130与第二绝缘层140形成于晶圆基板110后的剖面图。待晶圆基板110的镂空区112形成后,第一绝缘层120会从镂空区112裸露,如图6所示。接着在图12步骤S4中,第二绝缘层140便可形成于晶圆基板110的第二表面116与第三表面118上、及裸露于镂空区112的第一绝缘层120上,如图13所示。
图14绘示图13的第二绝缘层140激光蚀刻时的剖面图。图15绘示图14的第一绝缘层120、第二绝缘层140与导电垫130被激光蚀刻后的剖面图。同时参阅图14与图15,待第二绝缘层140形成后,在图12步骤S5中,便可通过激光蚀刻镂空区112中的第一绝缘层120与第二绝缘层140,使得第一绝缘层120形成第一开口122,第二绝缘层140形成第二开口142,导电垫130形成从第一开口122与第二开口142裸露的凹部132(见图3),而形成U形的凹槽131。如此一来,便可得到图15的半导体结构100b。
在本实施方式中,激光蚀刻第一绝缘层120与第二绝缘层140的步骤包含:提供具有穿孔212的遮罩210,并将遮罩210置于晶圆基板110的上方,使遮罩210的穿孔212对准于晶圆基板110的镂空区112。接着可发射激光L通过遮罩210的穿孔212至第一绝缘层120,以形成凹槽131。待凹槽131形成后,在后续制程中,便可形成布线层于第二绝缘层140上及裸露于第一开口122与第二开口144的导电垫130上。
同时参阅图3与图15,由于第一绝缘层120与第二绝缘层140是以激光蚀刻的方式分别形成第一开口122与第二开口142,且在激光蚀刻第一绝缘层120与第二绝缘层140时,导电垫130可同步形成从第一开口122与第二开口142裸露的凹部132。如此一来,当导电垫130的表面形成与其电性接触的布线层时,U形的凹槽131与布线层具有足够的接触面积而不易产生接触不良的状况,因此可提升半导体结构100b的良率。此外,因激光蚀刻的精度较高,可降低贯穿导电垫130的风险,因此导电垫130的厚度得以减薄,节省成本。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (13)
1.一种半导体结构,其特征在于,包含:
一晶圆基板,具有一镂空区及相对的一第一表面与一第二表面,其中该镂空区贯穿该第一表面与该第二表面;
一第一绝缘层,位于该晶圆基板的该第一表面上,该第一绝缘层具有一第一开口,且该第一开口连通于该镂空区;以及
一导电垫,位于该第一绝缘层相对该晶圆基板的表面上,且该导电垫覆盖该第一开口,使得该导电垫从该镂空区裸露,其中该导电垫具有朝向该第一开口的一凹部,该第一绝缘层具有围绕该第一开口的一倾斜面,使得该凹部与该倾斜面形成剖面形状为U形的一凹槽。
2.根据权利要求1所述的半导体结构,其特征在于,该晶圆基板具有围绕该镂空区的一第三表面,该半导体结构还包含:
一第二绝缘层,位于该凹槽上及该晶圆基板的该第二表面与该第三表面上,且该第二绝缘层具有一第二开口,使得该导电垫从该第二开口裸露。
3.根据权利要求2所述的半导体结构,其特征在于,还包含:
一布线层,位于该第二绝缘层上,且电性接触裸露于该第二开口的该导电垫。
4.根据权利要求1所述的半导体结构,其特征在于,该凹槽的深度大于该第一绝缘层的厚度。
5.一种半导体结构制作方法,其特征在于,包含:
形成一第一绝缘层于一晶圆基板的一第一表面;
形成一导电垫于该第一绝缘层上;
形成贯穿于该晶圆基板的该第一表面与一第二表面的一镂空区,使得该第一绝缘层从该镂空区裸露;以及
激光蚀刻裸露于该镂空区的该第一绝缘层,使得该第一绝缘层形成一第一开口,该导电垫形成从该第一开口裸露的一凹部。
6.根据权利要求5所述的半导体结构制作方法,其特征在于,该晶圆基板具有围绕该镂空区的一第三表面,该第一绝缘层具有围绕该第一开口的一倾斜面,该凹部与该倾斜面形成一凹槽,该半导体结构制作方法还包含:
形成一第二绝缘层于该凹槽上及该晶圆基板的该第二表面与该第三表面上。
7.根据权利要求6所述的半导体结构制作方法,其特征在于,还包含:
图案化该第二绝缘层,使得该第二绝缘层形成裸露该导电垫的一第二开口。
8.根据权利要求7所述的半导体结构制作方法,其特征在于,图案化该第二绝缘层包含:
形成图案化的一光阻层于该第二绝缘层上;
蚀刻未被该光阻层覆盖的部分该第二绝缘层,使得该第二绝缘层形成裸露该导电垫的该第二开口;以及
去除该光阻层。
9.根据权利要求7所述的半导体结构制作方法,其特征在于,还包含:
形成一布线层于该第二绝缘层上与裸露于该第二开口的该导电垫上。
10.根据权利要求5所述的半导体结构制作方法,其特征在于,激光蚀刻该第一绝缘层包含:
提供具有一穿孔的一遮罩;以及
发射一激光通过该遮罩的该穿孔至该第一绝缘层。
11.一种半导体结构制作方法,其特征在于,包含:
形成一第一绝缘层于一晶圆基板的一第一表面;
形成一导电垫于该第一绝缘层上;
形成贯穿于该晶圆基板的该第一表面与一第二表面的一镂空区,使得该第一绝缘层从该镂空区裸露,且该晶圆基板形成围绕该镂空区的一第三表面;
形成一第二绝缘层于该晶圆基板的该第二表面与该第三表面上及裸露于该镂空区的该第一绝缘层上;以及
激光蚀刻该镂空区中的该第一绝缘层与该第二绝缘层,使得该第一绝缘层形成一第一开口,该第二绝缘层形成一第二开口,该导电垫形成从该第一开口与该第二开口裸露的一凹部。
12.根据权利要求11所述的半导体结构制作方法,其特征在于,还包含:
形成一布线层于该第二绝缘层上及裸露于该第一开口与该第二开口的该导电垫上。
13.根据权利要求11所述的半导体结构制作方法,其特征在于,激光蚀刻该第一绝缘层与该第二绝缘层包含:
提供具有一穿孔的一遮罩;以及
发射一激光通过该遮罩的该穿孔至该第一绝缘层。
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US20110024864A1 (en) * | 2008-05-19 | 2011-02-03 | Panasonic Corporation | Semiconductor device and method for manufacturing the same |
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US8823179B2 (en) * | 2008-05-21 | 2014-09-02 | Chia-Lun Tsai | Electronic device package and method for fabricating the same |
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JP2002290022A (ja) * | 2001-03-27 | 2002-10-04 | Kyocera Corp | 配線基板およびその製造方法ならびに電子装置 |
US7008821B1 (en) * | 2004-09-10 | 2006-03-07 | Touch Micro-System Technology Inc. | Method of forming a wafer backside interconnecting wire |
CN100466243C (zh) * | 2005-09-29 | 2009-03-04 | 三洋电机株式会社 | 半导体装置及其制造方法 |
US20110024864A1 (en) * | 2008-05-19 | 2011-02-03 | Panasonic Corporation | Semiconductor device and method for manufacturing the same |
US20100096749A1 (en) * | 2008-10-21 | 2010-04-22 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package and manufacturing method thereof |
CN102592982A (zh) * | 2011-01-17 | 2012-07-18 | 精材科技股份有限公司 | 晶片封装体的形成方法 |
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US9711469B2 (en) | 2017-07-18 |
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