CN105070756B - 超高压ldmos器件结构 - Google Patents

超高压ldmos器件结构 Download PDF

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CN105070756B
CN105070756B CN201510507290.3A CN201510507290A CN105070756B CN 105070756 B CN105070756 B CN 105070756B CN 201510507290 A CN201510507290 A CN 201510507290A CN 105070756 B CN105070756 B CN 105070756B
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邢军军
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01ELECTRIC ELEMENTS
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856Source regions
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856Source regions
    • H01L29/086Impurity concentration or distribution

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Abstract

本发明公开了一种超高压LDMOS器件结构,形成于P型衬底中,所述P型衬底中具有一N型深阱,N型深阱中还有一P型层;P型层覆盖场氧化层,场氧化层两侧分别为超高压LDMOS器件的漏区及源区,源区为非闭环结构且所述源区位于P型体区中;场氧与源区之间的衬底表面覆盖栅氧化层及多晶硅栅极;漏区与场氧化层之间的衬底表面覆盖多晶硅场板,形成漏极场板,且漏极场板覆盖靠近漏区的部分场氧化层;所述超高压LDMOS器件是圆形,圆心位置为漏区;所述的场氧化层、P型层、P型体区及源区是呈包围漏区的圆环状;漏区通过接触孔引出经金属走线从圆心向器件外引出,金属走线下方的源区掺杂类型变更为P型,场氧化层上方还具有第二多晶硅场板。

Description

超高压LDMOS器件结构
技术领域
本发明涉及半导体器件制造领域,特别是指一种超高压LDMOS器件的结构。
背景技术
超高压LDMOS(所述超高压是指器件的耐压值大于600V)工艺应用中,有一种应用将该LDMOS作为高压电路区域和低压电路区域的电平位移(level shift)用,此时要求该LDMOS的漏端金属引线到高压电路区域,去控制高压逻辑区域,如图1所示,这样就要求该电平位移LDMOS的漏端金属引线能够跨出高压器件的漂移区到高压逻辑区域。
常规结构的超高压LDMOS如图2所示,在应用上是在LDMOS的漏端(即图2中的8)直接形成触点(PAD),通过封装形式将漏端引出,所以不用考虑高压金属引线对漂移区电场以及沟道区域造成的影响,而一旦有高压金属引线引出时,漏极引线的高电压会影响到栅极使其正下方的栅极部分的沟道开启,从而形成漏电,LDMOS耐压会急剧下降。
发明内容
本发明所要解决的技术问题是提供一种超高压LDMOS器件结构,解决现有器件漏极引出线对器件耐压能力影响的问题。
为解决上述问题,本发明所述的一种超高压LDMOS器件结构,形成于P型衬底中,所述P型衬底中具有一N型深阱,N型深阱中还有一P型层;一场氧化层位于所述P型层上并完全覆盖P型层,所述场氧化层两侧分别为超高压LDMOS器件的源区及漏区,且所述源区是位于P型体区中;场氧与源区之间的衬底表面覆盖栅氧化层及多晶硅栅极,且多晶硅栅极覆盖靠近源区的部分场氧化层形成栅极场板;漏区与场氧化层之间的衬底表面覆盖多晶硅场板,形成漏极场板,且漏极场板覆盖靠近漏区的部分场氧化层;
所述的超高压LDMOS器件在俯视平面上是呈圆形,所述漏区位于圆心位置;所述的场氧化层、P型层、P型体区及源区是呈包围漏区的圆环状;所述漏区通过接触孔引出,接金属走线从圆心向器件外侧引出;
所述的源区是呈C型的非闭环的重掺杂N型区,其位于漏区引出的金属走线正下方的源区,即C型开口的位置,其掺杂类型变更为重掺杂的P型;场氧化层上方还具有第二多晶硅场板。
进一步地,所述第二多晶硅场板至少为2个,其是各自形成为封闭的圆环状。
进一步地,所述的栅极场板及漏极场板场板,其覆盖场氧化层的部分,是保证与场氧化层下方的P型层有交叠。
进一步地,所述的重掺杂的P型的源区,与漏区形成反向二极管。
本发明所述的超高压LDMOS器件结构,通过引入单层多晶场板结构,并且栅极场板和漏极场板均与P型层两头交叠,屏蔽高压引线对漂移区电场的影响;本发明还将漏极引线下方的源区从传统的重掺杂N型替换为重掺杂的P型,从而引入一个反向二极管(漏端对源端),这样即使漏极引线的高电压影响到其下方的栅极,也不会导致沟道的开启,避免高压引线对栅极电位影响而有漏电。
附图说明
图1是超高压LDMOS器件应用示意图;
图2是常规超高压LDMOS器件结构示意图;
图3是本发明超高压LDMOS器件结构示意图;
图4是本发明超高压LDMOS器件剖面示意图。
附图标记说明
1是P型衬底,2是N型深阱,3是P型层,4是场氧化层,5是(第二)多晶硅场板;6是金属引线,7是P型体区,8是漏区,9是源区,10是多晶硅栅极,11是漏极场板,12是栅极场板。
具体实施方式
本发明所述的超高压LDMOS器件结构如图3及图4所示,所述的超高压LDMOS器件在俯视平面上是呈圆形,其形成于P型衬底1中,所述P型衬底1中具有一N型深阱2,N型深阱2中还有一P型层3;一场氧化层4位于所述P型层3上并完全覆盖P型层3,所述场氧化层4两侧分别为超高压LDMOS器件的源区9及漏8区,且所述源区9是位于P型体区7中;场氧化层4与源区9之间的衬底表面覆盖栅氧化层(图中未示出)及多晶硅栅极10,且多晶硅栅极覆盖靠近源区的部分场氧化层形成栅极场板12;漏区8与场氧化层4之间的衬底1表面覆盖多晶硅场板形成漏极场板11,且漏极场板覆盖靠近漏区的部分场氧化层4。
所述漏区8位于圆心位置;所述的场氧化层4、P型层3、P型体区7及源区9是呈包围漏区8的圆环状;所述漏区8通过接触孔引出,接金属走线6从圆心向器件外侧引出。
所述的源区9是呈C型的非闭环的重掺杂N型区,其位于漏区引出的金属走线正下方的源区9,即C型开口的位置,源区9重掺杂的N型在此处断开,其掺杂类型变更为重掺杂的P型,如图4中虚线位置的放大图;场氧化层4上方还具有第二多晶硅场板5。
所述第二多晶硅场板5至少为2个,其是各自形成为封闭的圆环状。
所述栅极场板12及漏极场板11,其覆盖场氧化层4的部分,是保证与场氧化层下方的P型层3有交叠。
本发明所述的超高压LDMOS器件结构,通过引入单层多晶场板结构,并且栅极场板和漏极场板均与P型层两头交叠,屏蔽高压引线对漂移区电场的影响;本发明还将漏极引线下方的源区从传统的重掺杂N型替换为重掺杂的P型,从而引入一个反向二极管(漏端对源端),避免高压引线对栅极电位影响而产生漏电。
本发明所述的超高压LDMOS器件结构的制造方法,包含:
1.在低浓度的P型衬底上注入形成N型深阱,高温扩散形成LDMOS的漂移区。其中P衬底的浓度以及N型深阱的浓度和耐压的要求相关,视具体需求而定。
2.漂移区内注入形成P型层,生长场氧化层,场氧化层的厚度依据耐压需求而定。
3.形成氧化层及淀积多晶硅,并且刻蚀形成多晶硅栅极结构和漂移区上的多晶场板,从而减少了高压引线对于漂移区电场的影响。注入形成P型体区作为LDMOS的沟道。
4.注入形成漏区和源区,在高压引线下方的源区空开一段不进行重掺杂N型注入,即此处不形成LDMOS器件。
5.注入形成重掺杂P型层作为衬底引出(重掺杂P型层在结构图中未示出),其中源区有一段不进行N型重掺杂的区域进行重掺杂的P型注入,从而在高压引线下面形成一个反向二极管,防止高压引线影响而形成漏端通路。
本发明通过一种新型的超高压LDMOS器件结构,通过多晶场板尽量屏蔽漂移区的电场,以及引入一个超高压的反向二极管(漏端对源端)解决了超高压LDMOS漏端引线带来的耐压急剧下降的问题,可以实现漏端金属引出的超高压LDMOS,相对于普通结构击穿电压BV不会明显下降,满足电平位移的要求。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (4)

1.一种超高压LDMOS器件结构,形成于P型衬底中,所述P型衬底中具有一N型深阱,N型深阱中还有一P型层;一场氧化层位于所述P型层上并完全覆盖P型层,所述场氧化层两侧分别为超高压LDMOS器件的源区及漏区,且所述源区是位于P型体区中;场氧化层与源区之间的衬底表面覆盖栅氧化层及多晶硅栅极,且多晶硅栅极覆盖靠近源区的部分场氧化层,形成栅极场板;漏区与场氧化层之间的衬底表面覆盖多晶硅场板,形成漏极场板,且漏极场板覆盖靠近漏区的部分场氧化层;
所述的超高压LDMOS器件在俯视平面是呈圆形,所述漏区位于圆心位置;所述的场氧化层、P型层、P型体区及源区是呈包围漏区的圆环状;所述漏区通过接触孔,接金属走线从圆心向器件外侧引出;
其特征在于:
所述的源区是呈C型的非闭环的重掺杂N型区,其位于漏区引出的金属走线正下方的源区,即C型开口的位置,其掺杂类型变更为重掺杂的P型;场氧化层上方还具有第二多晶硅场板。
2.如权利要求1所述的超高压LDMOS器件结构,其特征在于:所述第二多晶硅场板至少为2个,其是各自形成为封闭的圆环状。
3.如权利要求1所述的超高压LDMOS器件结构,其特征在于:所述的栅极场板和漏极场板,其覆盖场氧化层的部分,是保证与场氧化层下方的P型层有交叠。
4.如权利要求1所述的超高压LDMOS器件结构,其特征在于:所述的重掺杂的P型的源区,与漏区形成反向二极管。
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