CN104969317A - 用于在集成电路中构造隔离电容器的方法及设备 - Google Patents
用于在集成电路中构造隔离电容器的方法及设备 Download PDFInfo
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- CN104969317A CN104969317A CN201480006942.9A CN201480006942A CN104969317A CN 104969317 A CN104969317 A CN 104969317A CN 201480006942 A CN201480006942 A CN 201480006942A CN 104969317 A CN104969317 A CN 104969317A
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- conductive layer
- integrated circuit
- high voltage
- specified
- isolating capacitor
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Abstract
在初级集成电路裸片的一面上形成至少一个高电压额定隔离电容器。所述隔离电容器将在第一电压域中的初级集成电路AC耦合到在第二电压域中的第二集成电路。所述隔离电容器将所述初级集成电路与第二集成电路裸片DC隔离。
Description
相关专利申请案
本申请案主张2013年3月9日提出申请的序列号为61/775,550的共同拥有的美国临时专利申请案的优先权;所述美国临时专利申请案出于所有目的借此以引用方式并入本文中。
技术领域
本发明涉及高电压隔离电容器,特定来说涉及一种用于在集成电路中构造高电压隔离电容器的方法及设备。
背景技术
在最近工业应用中,对针对(例如)在不同接地电势下的数据通信电压及直流(DC)供应电压两者进行电隔离(流电及DC到DC两者)的需要不断增加。典型隔离应用已主要用于跨越隔离势垒的数据通信。但在近些年,应用也要求隔离装置(用于数据通信)也包含经隔离DC到DC能量传送能力。
典型电隔离方法可包含:光学、电感(例如,使用穿过变压器的交流(AC)或电磁射频)电容器(电容器为极良好流电隔离器)等。光学耦合器已成为主导信号隔离装置,但限于慢数据速率(小于1MHz)且过于庞大而不能集成。此外,光学耦合器不能够传递经隔离DC电力。电感及电容性隔离实施方案提供高数据速率、提供电隔离的电力传送,且制造成本低。然而,将有效高电压隔离电容器集成于集成电路封装中是成问题的。
发明内容
因此,出于(例如)隔离电力传送及发信号两者的目的,需要在单片集成电路工艺中制作高电压隔离电容器的方式。
根据实施例,一种用于形成高电压额定隔离电容器的方法可包括以下步骤:提供半导体集成电路;在所述半导体集成电路的一面的至少一部分上沉积绝缘层;在所述绝缘层上沉积第一导电层;在所述第一导电层上沉积高电压额定电介质层;在所述高电压额定电介质层上沉积第二导电层;及将所述高电压额定电介质层及所述第二导电层图案化以覆盖所述第一导电层的区域以形成所述高电压额定隔离电容器,其中所述第一导电层的至少一个经暴露部分提供到其的至少一个第一电连接。
根据所述方法的又一实施例,可包括以下步骤:将所述第一导电层图案化成所述高电压额定隔离电容器的第一极板;及将所述第二导电层图案化成所述高电压额定隔离电容器的第二极板。根据所述方法的又一实施例,可包括以下步骤:将所述第一导电层图案化成多个高电压额定隔离电容器的多个第一极板;及将所述第二导电层图案化成所述多个高电压额定隔离电容器的多个第二极板。根据所述方法的又一实施例,可包括在所述第一导电层及所述第二导电层上方进行钝化的步骤,其中所述钝化覆盖所述第二导电层且提供用于所述至少一个第一电连接及到所述第二导电层的所述至少一个第二电连接的开口。
根据所述方法的又一实施例,所述半导体集成电路可为废弃集成电路裸片。根据所述方法的又一实施例,所述第一导电层及所述第二导电层可为金属。根据所述方法的又一实施例,所述第一导电金属层及所述第二导电金属层可由铝构成。根据所述方法的又一实施例,所述第一导电层及所述第二导电层可由铜构成。根据所述方法的又一实施例,所述第一导电层及所述第二导电层可选自由以下各项组成的群组中的任一者或多者:钛、钽、钴、钼及其硅化物及自对准硅化物。
根据所述方法的又一实施例,可通过耐电压要求来确定高电压额定电介质层厚度。根据所述方法的又一实施例,所述高电压额定电介质层可包括二氧化硅(SiO2)。根据所述方法的又一实施例,所述高电压额定电介质层可包括氮化硅(SiN)。根据所述方法的又一实施例,所述高电压额定电介质层可包括氮氧化物。根据所述方法的又一实施例,所述高电压额定电介质层可包括具有不同厚度且通过标准技术沉积或生长的经掺杂氧化物或未掺杂氧化物的经堆叠层。根据所述方法的又一实施例,所述高电压额定电介质层可具有大约四(4)微米(μ)的厚度。根据所述方法的又一实施例,所述高电压额定隔离电容器可具有大约10微微法拉的电容值。
根据另一实施例,一种用于形成高电压额定隔离电容器的方法可包括以下步骤:提供半导体集成电路;在所述半导体集成电路的一面的至少一部分上沉积绝缘层;在所述绝缘层上沉积第一导电层;在所述第一导电层上沉积高电压额定电介质层;将所述高电压额定电介质层图案化以覆盖所述第一导电层的区域且提供到其的至少一个开口;将导电材料沉积到所述至少一个开口中以形成到所述第一导电层的至少一个第一电连接;在所述高电压额定电介质层上沉积第二导电层;及将所述第二导电层图案化以覆盖所述第一导电层的区域以形成所述高电压额定隔离电容器。
根据所述方法的又一实施例,可包括以下步骤:将所述第一导电层图案化成所述高电压额定隔离电容器的第一极板;及将所述第二导电层图案化成所述高电压额定隔离电容器的第二极板。根据所述方法的又一实施例,可包括以下步骤:将所述第一导电层图案化成多个高电压额定隔离电容器的多个第一极板;及将所述第二导电层图案化成所述多个高电压额定隔离电容器的多个第二极板。根据所述方法的又一实施例,可包括在所述第一导电层及所述第二导电层上方进行钝化的步骤,其中所述钝化覆盖所述第二导电层且提供用于所述至少一个第一电连接及到所述第二导电层的所述至少一个第二电连接的开口。
根据再一实施例,一种适于具有不同电压域之间的电压隔离的集成电路装置可包括:初级集成电路;在所述初级集成电路的一面的至少一部分上的第一绝缘层;在所述第一绝缘层上的第一导电层,其中所述第一导电层可耦合到所述初级集成电路上的电路连接垫;在所述第一导电层的一部分上的高电压额定电介质层;及在所述高电压额定电介质层上的第二导电层,其中所述第一导电层及所述第二导电层以及所述高电压额定电介质层形成高电压额定隔离电容器。
根据又一实施例,可提供具有耦合到所述第二导电层的电路连接垫的次级集成电路,其中所述初级集成电路可在第一电压域中且所述次级集成电路可在第二电压域中。根据又一实施例,可在所述第二导电层的至少一部分上方且在所述高电压额定电介质层及所述第一导电层的部分上方提供第二绝缘层,其中所述第二绝缘层可具有:在所述第一导电层上方的第一开口,其用于使第一接合线将所述第一导电层耦合到所述初级集成电路上的所述电路连接垫;及在所述第二导电层上方的第二开口,其用于使第二接合线将所述第二导电层耦合到所述次级集成电路上的所述电路连接垫。
根据又一实施例,可提供用于囊封所述初级集成电路及所述次级集成电路以及所述高电压额定隔离电容器的集成电路封装。根据又一实施例,所述第一导电层及所述第二导电层可为金属。根据又一实施例,所述第一导电金属层及所述第二导电金属层可由铝构成。根据又一实施例,所述第一导电层及所述第二导电层可由铜构成。根据又一实施例,所述第一导电层及所述第二导电层可选自由以下各项组成的群组中的任一者或多者:钛、钽、钴、钼及其硅化物及自对准硅化物。
根据又一实施例,所述高电压额定电介质层可包括二氧化硅(SiO2)。根据又一实施例,所述高电压额定电介质层可包括氮化硅(SiN)。根据又一实施例,所述高电压额定电介质层可包括氮氧化物。根据又一实施例,所述高电压额定电介质层可包括具有不同厚度且通过标准技术沉积或生长的经掺杂氧化物或未掺杂氧化物的经堆叠层。根据又一实施例,所述高电压额定电介质层可具有大约四(4)微米(μ)的厚度。根据又一实施例,所述高电压额定隔离电容器可具有大约10微微法拉的电容值。根据又一实施例,所述初级集成电路可为微控制器。
根据再一实施例,一种适于具有不同电压域之间的电压隔离的集成电路装置可包括:初级集成电路;在所述初级集成电路的一面的至少一部分上方的第一绝缘层;在所述第一绝缘层上方的多个第一高电压额定隔离电容器,其中所述多个第一高电压额定隔离电容器中的每一者可包括在所述第一绝缘层上的第一导电层,其中所述第一导电层中的一些第一导电层可耦合到所述初级集成电路上的相应电路连接垫;在所述多个第一导电层中的相应一者的一部分上的第一高电压额定电介质层;及在所述相应高电压额定电介质层上的第二导电层。
根据又一实施例,可提供具有耦合到相应第二导电层的电路连接垫的第二集成电路,其中所述初级集成电路可在第一电压域中且所述第二集成电路可在第二电压域中。根据又一实施例,可提供用于囊封所述初级集成电路及所述第一高电压额定隔离电容器的集成电路封装。根据又一实施例,所述集成电路封装可具有耦合到相应第一导电层的一些外部连接节点及耦合到所述多个第一高电压额定隔离电容器的相应第二导电层的一些其它外部连接节点。根据又一实施例,所述外部连接节点可为集成电路封装引线框架的引线指状件且所述相应引线指状件可借助接合线耦合到所述第一导电层及所述第二导电层。
根据又一实施例,所述集成电路装置可包括:在所述第二导电层的至少一部分上方的第二绝缘层;在所述第二绝缘层上方的多个第二高电压额定隔离电容器,其中所述多个第二高电压额定隔离电容器中的每一者可包括在所述第二绝缘层上的第三导电层,其中所述第三导电层中的一些第三导电层可耦合到第三集成电路上的相应电路连接垫;在所述多个第三导电层中的相应一者的一部分上的第二高电压额定电介质层;及在所述相应第二高电压额定电介质层上的第四导电层,其中所述第四导电层中的一些第四导电层可耦合到所述初级集成电路裸片上的相应电路连接垫。
根据又一实施例,可提供用于囊封所述初级集成电路及所述第二集成电路以及所述第一高电压额定隔离电容器的集成电路封装。根据又一实施例,可提供用于囊封所述初级集成电路、所述第二集成电路及所述第三集成电路以及所述第一高电压额定隔离电容器及所述第二高电压额定隔离电容器的集成电路封装。根据又一实施例,所述第三集成电路可在第三电压域中。根据又一实施例,所述集成电路封装可具有耦合到相应第四导电层的一些外部连接节点及耦合到所述多个第二高电压额定隔离电容器的相应第三导电层的一些其它外部连接节点。根据又一实施例,所述外部连接节点可为集成电路封装引线框架的引线指状件且所述相应引线指状件可借助接合线耦合到所述第一导电层及所述第二导电层。
附图说明
可通过结合附图参考以下说明获取对本发明的较完整理解,其中:
图1及1A图解说明根据本发明的特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性立面视图;
图1B及1C图解说明根据本发明的另一特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性立面视图;
图2图解说明根据本发明的特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性正交视图;
图3图解说明根据本发明的特定实例性实施例的形成于初级集成电路上且耦合到次级集成电路的多个高电压额定隔离电容器的示意性平面视图;
图4图解说明根据本发明的特定实例性实施例的将电力电路及信号电路耦合于初级集成电路与次级集成电路之间的多个高电压额定隔离电容器的示意性框图;
图5图解说明根据本发明的另一特定实例性实施例的将电力电路及信号电路耦合于初级集成电路与次级集成电路之间的多个高电压额定隔离电容器的示意性框图,其中所述次级集成电路的电路控制从初级集成电路到次级集成电路的电力传送;
图6图解说明根据本发明的教示的10微微法拉(pF)电容器的电流携载能力对施加到所述电容器的信号频率的表及图表;
图7及7A图解说明根据本发明的另一特定实例性实施例的形成于集成电路上的多个经反向堆叠的高电压额定隔离电容器的示意性立面视图;及
图8图解说明根据本发明的另一特定实例性实施例的形成于初级集成电路上且耦合到第一次级集成电路及第二次级集成电路的多个高电压额定隔离电容器的示意性平面视图。
虽然本发明易于发生各种修改及替代形式,但已在图式中展示并在本文中详细描述其特定实例性实施例。然而,应理解,本文中对特定实例性实施例的说明并非打算将本发明限于本文中所揭示的特定形式,而是相反,本发明打算涵盖如所附权利要求书所界定的所有修改及等效形式。
具体实施方式
根据各种实施例,可提供用于在集成电路裸片上构造高电压额定隔离电容器的方法及设备。根据各种实施例,本文中揭示形成低成本高电压额定电容器的方法。本文中揭示形成具有特殊电极几何形状及低成本SiO2电介质材料的高电压额定电容器的独特方法,特殊电极几何形状及低成本SiO2电介质材料促进制成在其下可具有有源电路的集成电路硅上面仅需要小面积的基于低成本SiO2的电介质绝缘高电压额定电容器。
可产生与主要供应源电隔离的经隔离供应电压。对于现代电子系统设计,此特征可变得需求极高。DC到DC隔离及AC到DC隔离为其实例。电容性隔离装置可使用(a)跨越电容性隔离势垒将电力从初级侧传送到次级侧的方法;及(b)使用反馈网络来调节经隔离次级电力的方法。针对此应用,需要高电压额定值(>3000Vrms)硅电容器以在不同通信装置之间形成电(例如,流电)隔离势垒。此高电压额定电容器可用于(a)经隔离DC到DC电力传送及(b)连接到不同电压域的装置之间的经隔离数据通信。
根据各种实施例,举例来说,可借助简单处理使用废弃集成电路晶片以基于二氧化硅(Si02)及铝而制成适用于经堆叠集成电路封装中的本文中所描述的隔离电容器。可选择电绝缘氧化物厚度来耐受数千伏特且所得电容为足够高以实现连接到两个不同电压域的集成电路装置之间的有效电力及信号传送。
使用经堆叠裸片Si02绝缘的电容器被认为产生过低的电容值。然而,根据本发明的各种实施例,通过使用各种电路技术(例如,较高电压电晶体、电压增倍器及三倍器等)以跨越这些电容器提供较高电压,可以用于有效电力及信号传送的足够电容制作所述电容器。
现在参考图式,示意性地图解说明实例性实施例的细节。图式中的相似元件将由相似编号表示,且相似元件将由带有不同小写字母后缀的相同编号表示。
参考图1及1A,绘示根据本发明的特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性立面视图。通常由数字100表示的高电压额定隔离电容器可包括第一导电层106、第二导电层112、在分别第一导电层106与第二导电层112之间的高电压额定电介质(绝缘)层110及在第二导电层112及第一导电层106的一部分上方的绝缘层108,例如,钝化物。第一垫开口114可用于提供对第一导电层106的电接达。第二垫开口116可用于提供对第二导电层112的电接达。高电压额定隔离电容器100可定位于安置于集成电路102上的绝缘层104上方且附接到所述绝缘层。
可使用用以形成第一导电层106的第一掩模及用以形成第二导电层112及高电压额定电介质层110的第二掩模来制作至少一个高电压额定隔离电容器100。第三掩模可用于在绝缘(例如,钝化)层108中分别形成第一垫开口114及第二垫开口116。预期到且在本发明的范围内,可同样成功地使用其它工艺制作步骤,且集成电路制作领域中的且受益于本发明的技术人员可想出此类替代设计且仍在本发明的精神及意图内。
第一导电层106及第二导电层112分别可包括导电金属材料,例如(举例来说但不限于)铝、铜、钛、钽、钴、钼、其硅化物及自对准硅化物等。绝缘层104可为(举例来说但不限于)二氧化硅(SiO2)、氮化硅(SiN)、氮氧化物,或具有不同厚度且通过标准技术沉积或生长的经掺杂氧化物或未掺杂氧化物的经堆叠层等。高电压额定电介质层110可为(举例来说但不限于)二氧化硅(SiO2)、氮化硅(SiN)、SiOxNy、氧化物-氮化物-氧化物(ONO)等。绝缘电介质层110的厚度可确定高电压额定隔离电容器100的耐电压能力,且针对大约3,000伏DC绝缘击穿电压可为(举例来说但不限于)大约四(4)微米厚SiO2。绝缘层108可为具有用于连接到低电压垫114及高电压垫116的开口的保护性钝化层,例如,二氧化硅、氮化硅等。术语“高电压垫”及“低电压垫”是指不具有用于电力、接地或信号的直流(DC)连接的不同电压域。电压域之间的电压差可为大的或小的,且进一步可用于保护及隔离装置免受大电压瞬变的影响,例如,保护及隔离传感器免受可因闪电、电力切换瞬变等造成的感应电动势(EMF)电压。
现在参考图1A,高电压额定隔离电容器100组合件的第一导电层106可借助接合线124连接到引线指状件120及/或集成电路102(在下文为“初级IC 102”)上的连接垫。高电压额定隔离电容器100组合件的导电层112可借助接合线126连接到第二集成电路118(在下文为“次级IC 118”)上的连接垫及/或引线指状件122。次级IC 118可借助接合线128连接到引线指状件122。初级IC 102可经配置以在第一电压域中操作,且次级IC 118可经配置以在第二电压域中操作。第一电压域与第二电压域之间的接地电势及电压电势可相差数千伏,仅受高电压额定电介质层110的耐电压(击穿)(例如,其厚度)限制。引线指状件120可耦合到第一电压域,且引线指状件122可耦合到第二电压域。初级IC 102、高电压额定隔离电容器100、次级IC 118以及引线指状件120及122的部分可囊封于集成电路封装130(例如,环氧树脂)中。为说明清楚起见而未展示裸片焊盘(如果使用)。预期到且在本发明的范围内,可使用除引线指状件以外的其它集成电路外部连接节点,例如,球形凸块等。
参考图1B及1C,绘示根据本发明的另一特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性立面视图。通常由数字100a表示的高电压额定隔离电容器可包括第一导电层106、第二导电层112、在分别第一导电层106与第二导电层112之间的高电压额定电介质(绝缘)层110及在第二导电层112及第一导电层106的一部分上方的绝缘层108,例如,钝化物。导电材料132可用于填充于可在第一导电层106上方的高电压额定电介质层110中的开口中。导电材料132可用于提供对第一导电层106的电接达。第二垫开口116可用于提供对第二导电层112的电接达。高电压额定隔离电容器100a可定位于安置于集成电路102上的绝缘层104上方且附接到所述绝缘层。高电压额定隔离电容器100a的操作与上文所描述的高电压额定隔离电容器100的操作实质上相同。
参考图2,绘示根据本发明的特定实例性实施例的形成于集成电路上的高电压额定隔离电容器的示意性正交视图。高电压额定隔离电容器100经展示附接到初级IC 102且借助接合线124连接到一些引线指状件120,借助接合线124a连接到初级IC 102,借助接合线126连接到次级IC 118,及/或借助接合线126a连接到引线指状件122。高电压额定隔离电容器100可附接到在初级IC 102的一面上的绝缘层104,例如,钝化层。
参考图3,绘示根据本发明的特定实例性实施例的形成于初级集成电路上且耦合到次级集成电路的多个高电压额定隔离电容器的示意性平面视图。多个高电压额定隔离电容器100可安置于绝缘层104上的初级IC 102上方(图1及1A)。多个高电压额定隔离电容器100中的每一者可用于将第一电压域中的引线指状件120与第二电压域中的次级IC 118的信号或电力垫(例如,引线指状件120a、接合线124a、隔离电容器100a、接合线126a及次级IC 118的连接垫)直流(DC)隔离。从初级IC 102的信号垫到次级IC 118的信号垫(例如,接合线124b、隔离电容器100b、接合线126b及次级IC 118的连接垫)。从第一电压域中的引线指状件120e到第二电压中的引线指状件122h(例如,接合线124e、隔离电容器100e、接合线126e及引线指状件122h)。
可在必要时针对特定应用连接多个高电压额定隔离电容器100。可如图1及1A中所展示及上文所描述形成高电压额定隔离电容器100中的每一者。预期到且在本发明的范围内,高电压额定隔离电容器100可以所要的任何几何形状形成且其不限于如图3中所展示的特定实例性实施例中所展示的正方形或矩形形状。
参考图4,绘示根据本发明的特定实例性实施例的将电力电路及信号电路耦合于初级集成电路与次级集成电路之间的多个高电压额定隔离电容器的示意性框图。可透过多个高电压额定隔离电容器100(例如,隔离电容器100a到100f)使用交流(AC)电压来隔离电力及将电力从第一电压域传送到第二电压域,或反之亦然。可通过波形产生器432(例如,振荡器、由脉冲宽度调制(PWM)调制器控制的电力开关等)或当闭合开关434且波形产生器432不作用时通过外部脉冲宽度调制(PWM)信号产生此AC电压。驱动器430及428可透过隔离电容器100a到100f向电压电荷泵444提供不需要接地参考的推拉(例如,差动信号)波形,所述电压电荷泵然后可向第二电压域中的电压调节器446提供经隔离电压。可提供第一电压域中的可编程输入/输出(I/O)436及第二电压域中的可编程输入/输出(I/O)442且借助较小串联连接的电容器438及440(增加的耐电压)或通过额外隔离电容器100将可编程输入/输出(I/O)436与可编程输入/输出(I/O)442 DC隔离。
参考图6,绘示根据本发明的教示的10微微法拉(pF)电容器的电流携载能力对施加到所述电容器的信号频率的表及图表。隔离电容器100可优选地具有大约10微微法拉的电容值。图6中所展示的表及图表提供10 pF电容器的在不同频率下的电流携载能力。当一个10 pF电容器无法在所要频率下供应足够量的电流时,那么添加额外并联连接的隔离电容器100可为适当的,例如,参见图4,隔离电容器100a到100f。
返回参考图4,从信号输出驱动器到信号输入驱动器的低电平信号可具有低得多的信号电流要求,例如,较高阻抗。因此,可有效地使用小值电容器,例如,大约一(1)pF。电容器438及440可具有与隔离电容器100相同的构造,或集成电路制作技术中已知的构造。任何电容器阻挡DC,因此将借助用于长期数据逻辑电平保持的锁存器或寄存器边缘触发第一电压域及第二电压域中的电路之间的优选地信号数据传送。这些隔离电容器100也可用于微控制器及其它类比产品中的供电应用且不仅限于隔离装置。
参考图5,绘示根据本发明的另一特定实例性实施例的将电力电路及信号电路耦合于初级集成电路与次级集成电路之间的多个高电压额定隔离电容器的示意性框图,其中次级集成电路的电路控制从初级集成电路到次级集成电路的电力传送。可透过高电压额定隔离电容器100(例如,隔离电容器100a及100b)使用交流(AC)电压来隔离电力及将电力从第一电压域传送到第二电压域,或反之亦然。可通过波形产生器532(例如,振荡器、由脉冲宽度调制(PWM)调制器控制的电力开关等)或当闭合开关534且波形产生器532不作用时通过外部脉冲宽度调制(PWM)信号产生此AC电压。波形产生器532向驱动器530及528提供AC电压,且驱动器530及528可透过隔离电容器100a及100b向第二电压域中的整流器544提供不需要接地参考的推拉(例如,差动信号)波形。
整流器544向电压调节器546提供DC电压,所述电压调节器提供第二电压域中的电源电压。电压调节器546也可向PWM调制器548提供内部电压参考(未展示)与经隔离电压VDD-ISO之间的误差电压。PWM调制器548的输出透过隔离电容器100c向波形产生器532或外部PWM产生器(未展示)提供反馈控制信号。依据此反馈控制信号,波形产生器532可使其输出振幅及/或频率变化以维持(例如)次级IC 118的所要经隔离电压VDD-ISO。因此,可将经隔离、高效率、经调节电压从第一电压域提供到第二电压域。举例来说,来自第一电压域的经隔离输入可由输入电路538接收且透过隔离电容器100e到输出驱动器电路544隔离耦合到第二电压域。类似地,举例来说,来自第二电压域的经隔离输入可由输入电路542接收且透过隔离电容器100d到输出驱动器电路536隔离耦合到第一电压域。
应注意,第一电压域中的供应电压(VDD)使用内部波形产生器532传送为AC能量,且透过隔离电容器100a及100b跨越隔离势垒传送到第二电压域侧。DC供应电压(VDD-IS0)可从来自隔离电容器100a及100b的经整流AC信号发展,且透过由PWM调制器548及反馈隔离耦合电容器100c形成的反馈电路被调节。
波形产生器532也可为受PWM调制器548控制的PWM产生器。预期到且在本发明的范围内,可使用外部PWM产生器(未展示)且通过PWM调制器548来控制所述产生器。
参考图7及7A,绘示根据本发明的另一特定实例性实施例的形成于集成电路上的多个经反向堆叠的高电压额定隔离电容器的示意性立面视图。通常由数字700表示的另一高电压额定隔离电容器可包括在第二导电层112上方的绝缘层704、在绝缘层704上方的第三导电层712、在第三导电层712的一部分上方的绝缘电介质层710、在绝缘电介质层710上方的第四导电层706及在第四导电层706及第三导电层712的一部分上方的绝缘层708。绝缘层708中的第三垫开口716可提供对第三导电层712的电连接接达。绝缘层708中的第四垫开口714可提供对第四导电层706的电连接接达。
高电压额定隔离电容器700可定位于安置于初级IC 102上的高电压额定隔离电容器100上方且附接到高电压额定隔离电容器100。高电压额定隔离电容器700的构造可与高电压额定隔离电容器100实质上相同,只不过第三导电层712及第四导电层706可分别为反向的,使得较不厚的电绝缘物(例如,电绝缘层704)必须放置于隔离电容器100与700之间以便维持第一电压域与第二电压域之间的所要电压击穿额定值。初级IC 102及次级IC 118以及隔离电容器100及700可囊封(封装)于集成电路封装730中。
参考图8,绘示根据本发明的另一特定实例性实施例的形成于初级集成电路上且耦合到第一集成电路及第二次级集成电路的多个高电压额定隔离电容器的示意性平面视图。隔离电容器100及700可彼此垂直地放置且另一次级IC 818可耦合到隔离电容器700。此允许两个或两个以上次级IC(例如,IC封装830)与初级IC 102一起经封装。次级IC 118及818可均在第二电压域中,或次级IC 118可在第二电压域中且次级IC 818可在第三电压域中,其中次级IC 118及818两者均可与第一电压域中的初级IC 102完全隔离。另外,次级IC 118及818可在配置于第二电压域及第三电压域中时彼此隔离。初级IC 102可包括微控制器等,且次级IC 118/818可为数字信号处理器(DSP)、充电时间测量单元(CTMU)、协同处理器、专用输入输出接口、计数器、计时器、模/数转换器(ADC)、数/模转换器(DAC)等。初级IC 102及次级IC 118及818以及隔离电容器100及700可囊封(封装)于集成电路封装830中。
可在必要时针对特定应用连接多个高电压额定隔离电容器100及700。可如图7及7A中所展示及上文所描述而形成高电压额定隔离电容器100及700中的每一者。预期到且在本发明的范围内,高电压额定隔离电容器100及700可以所要的任何几何形状形成且其不限于如图3及8中所展示的特定实例性实施例中所展示的正方形或矩形形状。
虽然本发明易于发生各种修改及替代形式,但已在图式中展示并在本文中详细描述其特定实例性实施例。然而,应理解,本文中对特定实例性实施例的说明并非打算将本发明限于本文中所揭示的特定形式,而是相反,本发明打算涵盖如所附权利要求书所界定的所有修改及等效形式。
Claims (46)
1.一种用于形成高电压额定隔离电容器的方法,所述方法包括以下步骤:
提供半导体集成电路;
在所述半导体集成电路的一面的至少一部分上沉积绝缘层;
在所述绝缘层上沉积第一导电层;
在所述第一导电层上沉积高电压额定电介质层;
在所述高电压额定电介质层上沉积第二导电层;及
将所述高电压额定电介质层及所述第二导电层图案化以覆盖所述第一导电层的区域以形成所述高电压额定隔离电容器,其中所述第一导电层的至少一个经暴露部分提供到其的至少一个第一电连接。
2.根据权利要求1所述的方法,其进一步包括以下步骤:将所述第一导电层图案化成所述高电压额定隔离电容器的第一极板;及将所述第二导电层图案化成所述高电压额定隔离电容器的第二极板。
3.根据权利要求1所述的方法,其进一步包括以下步骤:将所述第一导电层图案化成多个高电压额定隔离电容器的多个第一极板;及将所述第二导电层图案化成所述多个高电压额定隔离电容器的多个第二极板。
4.根据权利要求1所述的方法,其进一步包括在所述第一导电层及所述第二导电层上方进行钝化的步骤,其中所述钝化覆盖所述第二导电层且提供用于所述至少一个第一电连接及到所述第二导电层的至少一个第二电连接的开口。
5.根据权利要求1所述的方法,其中所述半导体集成电路为废弃集成电路裸片。
6.根据权利要求1所述的方法,其中所述第一导电层及所述第二导电层为金属。
7.根据权利要求6所述的方法,其中所述第一导电金属层及所述第二导电金属层由铝构成。
8.根据权利要求6所述的方法,其中所述第一导电层及所述第二导电层由铜构成。
9.根据权利要求1所述的方法,其中所述第一导电层及所述第二导电层选自由以下各项组成的群组中的任一者或多者:钛、钽、钴、钼以及其硅化物及自对准硅化物。
10.根据权利要求1所述的方法,其中通过耐电压要求来确定高电压额定电介质层厚度。
11.根据权利要求1所述的方法,其中所述高电压额定电介质层包括二氧化硅SiO2。
12.根据权利要求1所述的方法,其中所述高电压额定电介质层包括氮化硅SiN。
13.根据权利要求1所述的方法,其中所述高电压额定电介质层包括氮氧化物。
14.根据权利要求1所述的方法,其中所述高电压额定电介质层包括具有不同厚度且通过标准技术沉积或生长的经掺杂氧化物或未掺杂氧化物的经堆叠层。
15.根据权利要求1所述的方法,其中所述高电压额定电介质层具有大约四(4)微米(μ)的厚度。
16.根据权利要求1所述的方法,其中所述高电压额定隔离电容器具有大约10微微法拉的电容值。
17.一种用于形成高电压额定隔离电容器的方法,所述方法包括以下步骤:
提供半导体集成电路;
在所述半导体集成电路的一面的至少一部分上沉积绝缘层;
在所述绝缘层上沉积第一导电层;
在所述第一导电层上沉积高电压额定电介质层;
将所述高电压额定电介质层图案化以覆盖所述第一导电层的区域且提供到其的至少一个开口;
将导电材料沉积到所述至少一个开口中以形成到所述第一导电层的至少一个第一电连接;
在所述高电压额定电介质层上沉积第二导电层;及
将所述第二导电层图案化以覆盖所述第一导电层的区域以形成所述高电压额定隔离电容器。
18.根据权利要求17所述的方法,其进一步包括以下步骤:将所述第一导电层图案化成所述高电压额定隔离电容器的第一极板;及将所述第二导电层图案化成所述高电压额定隔离电容器的第二极板。
19.根据权利要求17所述的方法,其进一步包括以下步骤:将所述第一导电层图案化成多个高电压额定隔离电容器的多个第一极板;及将所述第二导电层图案化成所述多个高电压额定隔离电容器的多个第二极板。
20.根据权利要求17所述的方法,其进一步包括在所述第一导电层及所述第二导电层上方进行钝化的步骤,其中所述钝化覆盖所述第二导电层且提供用于所述至少第一电连接及到所述第二导电层的至少一个第二电连接的开口。
21.一种适于具有不同电压域之间的电压隔离的集成电路装置,其包括:
初级集成电路;
在所述初级集成电路的一面的至少一部分上的第一绝缘层;
在所述第一绝缘层上的第一导电层,其中所述第一导电层耦合到所述初级集成电路上的电路连接垫;
在所述第一导电层的一部分上的高电压额定电介质层;及
在所述高电压额定电介质层上的第二导电层,其中所述第一导电层及所述第二导电层以及所述高电压额定电介质层形成高电压额定隔离电容器。
22.根据权利要求21所述的集成电路装置,其进一步包括具有耦合到所述第二导电层的电路连接垫的次级集成电路,其中所述初级集成电路在第一电压域中且所述次级集成电路在第二电压域中。
23.根据权利要求22所述的集成电路装置,其进一步包括在所述第二导电层的至少一部分上方且在所述高电压额定电介质层及所述第一导电层的部分上方的第二绝缘层,其中所述第二绝缘层具有
在所述第一导电层上方的第一开口,其用于使第一接合线将所述第一导电层耦合到所述初级集成电路上的所述电路连接垫,及
在所述第二导电层上方的第二开口,其用于使第二接合线将所述第二导电层耦合到所述次级集成电路上的所述电路连接垫。
24.根据权利要求23所述的集成电路装置,其进一步包括囊封所述初级集成电路及所述次级集成电路以及所述高电压额定隔离电容器的集成电路封装。
25.根据权利要求21所述的集成电路装置,其中所述第一导电层及所述第二导电层为金属。
26.根据权利要求25所述的集成电路装置,其中所述第一导电金属层及所述第二导电金属层由铝构成。
27.根据权利要求25所述的集成电路装置,其中所述第一导电层及所述第二导电层由铜构成。
28.根据权利要求21所述的集成电路装置,其中所述第一导电层及所述第二导电层选自由以下各项组成的群组中的任一者或多者:钛、钽、钴、钼以及其硅化物及自对准硅化物。
29.根据权利要求21所述的集成电路装置,其中所述高电压额定电介质层包括二氧化硅SiO2。
30.根据权利要求21所述的集成电路装置,其中所述高电压额定电介质层包括氮化硅SiN。
31.根据权利要求21所述的集成电路装置,其中所述高电压额定电介质层包括氮氧化物。
32.根据权利要求21所述的集成电路装置,其中所述高电压额定电介质层包括具有不同厚度且通过标准技术沉积或生长的经掺杂氧化物或未掺杂氧化物的经堆叠层。
33.根据权利要求21所述的集成电路装置,其中所述高电压额定电介质层具有大约四(4)微米(μ)的厚度。
34.根据权利要求21所述的集成电路装置,其中所述高电压额定隔离电容器具有大约10微微法拉的电容值。
35.根据权利要求21所述的集成电路装置,其中所述初级集成电路为微控制器。
36.一种适于具有不同电压域之间的电压隔离的集成电路装置,其包括:
初级集成电路;
在所述初级集成电路的一面的至少一部分上方的第一绝缘层;
在所述第一绝缘层上方的多个第一高电压额定隔离电容器,其中所述多个第一高电压额定隔离电容器中的每一者包括
在所述第一绝缘层上的第一导电层,其中所述第一导电层中的一些第一导电层耦合到所述初级集成电路上的相应电路连接垫;
在所述多个第一导电层中的相应一者的一部分上的第一高电压额定电介质层;及
在所述相应高电压额定电介质层上的第二导电层。
37.根据权利要求36所述的集成电路装置,其进一步包括具有耦合到相应第二导电层的电路连接垫的第二集成电路,其中所述初级集成电路在第一电压域中且所述第二集成电路在第二电压域中。
38.根据权利要求36所述的集成电路装置,其进一步包括囊封所述初级集成电路及所述第一高电压额定隔离电容器的集成电路封装。
39.根据权利要求38所述的集成电路装置,其中所述集成电路封装具有耦合到相应第一导电层的一些外部连接节点及耦合到所述多个第一高电压额定隔离电容器的相应第二导电层的一些其它外部连接节点。
40.根据权利要求39所述的集成电路装置,其中所述外部连接节点为集成电路封装引线框架的引线指状件,且所述相应引线指状件借助接合线耦合到所述第一导电层及所述第二导电层。
41.根据权利要求37所述的集成电路装置,其进一步包括:
在所述第二导电层的至少一部分上方的第二绝缘层;
在所述第二绝缘层上方的多个第二高电压额定隔离电容器,其中所述多个第二高电压额定隔离电容器中的每一者包括
在所述第二绝缘层上的第三导电层,其中所述第三导电层中的一些第三导电层耦合到第三集成电路上的相应电路连接垫;
在所述多个第三导电层中的相应一者的一部分上的第二高电压额定电介质层;及
在所述相应第二高电压额定电介质层上的第四导电层,其中所述第四导电层中的一些第四导电层耦合到初级集成电路裸片上的相应电路连接垫。
42.根据权利要求37所述的集成电路装置,其进一步包括囊封所述初级集成电路及所述第二集成电路以及所述第一高电压额定隔离电容器的集成电路封装。
43.根据权利要求41所述的集成电路装置,其进一步包括囊封所述初级集成电路、所述第二集成电路及所述第三集成电路以及所述第一高电压额定隔离电容器及所述第二高电压额定隔离电容器的集成电路封装。
44.根据权利要求41所述的集成电路装置,其中所述第三集成电路在第三电压域中。
45.根据权利要求43所述的集成电路装置,其中所述集成电路封装具有耦合到相应第四导电层的一些外部连接节点及耦合到所述多个第二高电压额定隔离电容器的相应第三导电层的一些其它外部连接节点。
46.根据权利要求45所述的集成电路装置,其中所述外部连接节点为所述集成电路封装引线框架的引线指状件,且所述相应引线指状件借助接合线耦合到所述第一导电层及所述第二导电层。
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US14/199,522 US9337253B2 (en) | 2013-03-09 | 2014-03-06 | Method and apparatus for constructing an isolation capacitor in an integrated circuit |
US14/199,522 | 2014-03-06 | ||
PCT/US2014/021540 WO2014164258A1 (en) | 2013-03-09 | 2014-03-07 | Method and apparatus for constructing an isolation capacitor in an integrated circuit |
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102832189B (zh) * | 2012-09-11 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 一种多芯片封装结构及其封装方法 |
US10147784B2 (en) | 2014-05-15 | 2018-12-04 | Texas Instruments Incorporated | High voltage galvanic isolation device |
US9299697B2 (en) | 2014-05-15 | 2016-03-29 | Texas Instruments Incorporated | High breakdown voltage microelectronic device isolation structure with improved reliability |
JP2017026505A (ja) * | 2015-07-24 | 2017-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN106952896B (zh) * | 2017-04-07 | 2019-08-23 | 上海莱狮半导体科技有限公司 | 一种电容以及一种开关电源ac-dc电路 |
US10074713B1 (en) * | 2017-09-15 | 2018-09-11 | Allegro Microsystems, Llc | Signal isolator integrated circuit package |
US11222945B2 (en) * | 2017-12-29 | 2022-01-11 | Texas Instruments Incorporated | High voltage isolation structure and method |
US10345832B1 (en) * | 2018-05-14 | 2019-07-09 | Asm Ip Holding B.V. | Insulation system and substrate processing apparatus |
EP3896855B1 (en) * | 2020-04-15 | 2024-03-20 | Melexis Bulgaria Ltd. | Floating switch for signal commutation |
JP7377181B2 (ja) * | 2020-09-11 | 2023-11-09 | 株式会社東芝 | 半導体装置 |
US11984802B2 (en) * | 2021-06-30 | 2024-05-14 | Texas Instruments Incorporated | Rectifier with signal reconstruction |
CN113889456A (zh) * | 2021-08-24 | 2022-01-04 | 华为数字能源技术有限公司 | 一种集成型高压隔离电容及数字电容隔离器 |
US11901402B2 (en) | 2021-11-18 | 2024-02-13 | Texas Instruments Incorporated | Standalone isolation capacitor |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020135236A1 (en) * | 1997-10-23 | 2002-09-26 | Haigh Geoffrey T. | Non-optical signal isolator |
US20030071322A1 (en) * | 2001-10-11 | 2003-04-17 | Comeau Alain R. | Apparatus for controlling a high voltage circuit using a low voltage circuit |
US20040029404A1 (en) * | 1998-12-21 | 2004-02-12 | Megic Corporation | High performance system-on-chip passive device using post passivation process |
CN1921112A (zh) * | 2005-08-24 | 2007-02-28 | 东京毅力科创株式会社 | 电介质膜电容器及其制造方法 |
US20080290444A1 (en) * | 2007-05-24 | 2008-11-27 | Philip John Crawley | Capacitor structure in a semiconductor device |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5444600A (en) * | 1992-12-03 | 1995-08-22 | Linear Technology Corporation | Lead frame capacitor and capacitively-coupled isolator circuit using the same |
US5973367A (en) | 1995-10-13 | 1999-10-26 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
US6442213B1 (en) | 1997-04-22 | 2002-08-27 | Silicon Laboratories Inc. | Digital isolation system with hybrid circuit in ADC calibration loop |
JP3839267B2 (ja) | 2001-03-08 | 2006-11-01 | 株式会社ルネサステクノロジ | 半導体装置及びそれを用いた通信端末装置 |
DE10234999A1 (de) | 2002-07-31 | 2004-02-19 | Infineon Technologies Ag | Hilfsstromversorgungseinrichtung |
US7737871B2 (en) | 2004-06-03 | 2010-06-15 | Silicon Laboratories Inc. | MCU with integrated voltage isolator to provide a galvanic isolation between input and output |
US20060290377A1 (en) | 2005-05-31 | 2006-12-28 | Jongsun Kim | Capacitively coupled pulsed signaling bus interface |
US7742277B2 (en) * | 2005-08-24 | 2010-06-22 | Ibiden Company Limited | Dielectric film capacitor and method of manufacturing the same |
US7864546B2 (en) | 2007-02-13 | 2011-01-04 | Akros Silicon Inc. | DC-DC converter with communication across an isolation pathway |
JP5153793B2 (ja) | 2007-03-22 | 2013-02-27 | トムソン ライセンシング | 絶縁され調整されたdc電力を電子機器へ供給する装置 |
US8188814B2 (en) | 2008-02-15 | 2012-05-29 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | High voltage isolation dual capacitor communication system |
US8014218B2 (en) * | 2008-12-24 | 2011-09-06 | International Business Machines Corporation | Capacitively isolated mismatch compensated sense amplifier |
KR20120088013A (ko) | 2010-09-20 | 2012-08-08 | 삼성전자주식회사 | 디커플링 반도체 커패시터를 포함하는 반도체 패키지 |
US9093433B2 (en) | 2010-11-18 | 2015-07-28 | Microchip Technology Incorporated | Using bump bonding to distribute current flow on a semiconductor power device |
US8680690B1 (en) * | 2012-12-07 | 2014-03-25 | Nxp B.V. | Bond wire arrangement for efficient signal transmission |
US8988142B2 (en) * | 2013-03-10 | 2015-03-24 | Microchip Technology Incorporated | Integrated high voltage isolation using low value capacitors |
-
2014
- 2014-03-06 US US14/199,522 patent/US9337253B2/en active Active
- 2014-03-07 EP EP14712974.6A patent/EP2965331A1/en not_active Withdrawn
- 2014-03-07 CN CN201480006942.9A patent/CN104969317A/zh active Pending
- 2014-03-07 KR KR1020157020774A patent/KR20150130976A/ko not_active Application Discontinuation
- 2014-03-07 WO PCT/US2014/021540 patent/WO2014164258A1/en active Application Filing
- 2014-03-10 TW TW103108238A patent/TWI638392B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020135236A1 (en) * | 1997-10-23 | 2002-09-26 | Haigh Geoffrey T. | Non-optical signal isolator |
US20040029404A1 (en) * | 1998-12-21 | 2004-02-12 | Megic Corporation | High performance system-on-chip passive device using post passivation process |
US20030071322A1 (en) * | 2001-10-11 | 2003-04-17 | Comeau Alain R. | Apparatus for controlling a high voltage circuit using a low voltage circuit |
CN1921112A (zh) * | 2005-08-24 | 2007-02-28 | 东京毅力科创株式会社 | 电介质膜电容器及其制造方法 |
US20080290444A1 (en) * | 2007-05-24 | 2008-11-27 | Philip John Crawley | Capacitor structure in a semiconductor device |
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US20140252551A1 (en) | 2014-09-11 |
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