TWI638392B - 在積體電路中建構隔離電容器之方法及裝置 - Google Patents

在積體電路中建構隔離電容器之方法及裝置 Download PDF

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Publication number
TWI638392B
TWI638392B TW103108238A TW103108238A TWI638392B TW I638392 B TWI638392 B TW I638392B TW 103108238 A TW103108238 A TW 103108238A TW 103108238 A TW103108238 A TW 103108238A TW I638392 B TWI638392 B TW I638392B
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high voltage
integrated circuit
conductive layer
voltage rated
layer
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TW103108238A
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TW201442085A (zh
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喬葛瑞 迪克斯
藍迪 葉奇
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微晶片科技公司
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Abstract

在一初級積體電路晶粒之一面上形成至少一個高電壓額定隔離電容器。該隔離電容器將在一第一電壓域中之初級積體電路AC耦合至在一第二電壓域中之一第二積體電路。該隔離電容器DC隔離該初級積體電路與第二積體電路晶粒。

Description

在積體電路中建構隔離電容器之方法及裝置 相關專利申請案
此申請案主張2013年3月9日提出申請之共同擁有之第61/775,550號美國臨時專利申請案之優先權；該美國臨時專利申請案出於所有目的據此以引用方式併入本文中。
本發明係關於高電壓隔離電容器，特定而言係關於一種用於在一積體電路中建構高電壓隔離電容器之方法及裝置。
在最近工業應用中，對用於(例如)在不同接地電位下之資料通信電壓及DC供應電壓兩者之電隔離(流電及直流(DC)對DC)兩者)之需要不斷增加。典型隔離應用已主要用於跨越一隔離障壁之資料通信。但在近些年，應用亦要求隔離器件(用於資料通信)亦包含經隔離DC對DC能量傳送能力。
典型電隔離方法可包含：光學、感應(例如，使用穿過一變壓器之交流(AC)或電磁射頻)電容器(電容器係一極良好流電隔離器)等。光學耦合器已成為主導信號隔離器件，但限於慢資料速率(小於1MHz)且對於整合而言係龐大的。此外，光學耦合器不能夠傳遞經隔離DC電力。感應及電容隔離實施方案提供高資料速率、提供電隔離之電力傳送，且製造起來係低成本的。然而，在一積體電路封裝中整合有效 高電壓隔離電容器係成問題的。
因此，需要在一單片積體電路程序中製作高電壓隔離電容器(例如)以用於隔離電力傳送及發信號目的兩者之一方式。
根據一實施例，一種用於形成一高電壓額定隔離電容器之方法可包括以下步驟：提供一半導體積體電路；在該半導體積體電路之一面之至少一部分上沈積一絕緣層；在該絕緣層上沈積一第一導電層；在該第一導電層上沈積一高電壓額定介電層；在該高電壓額定介電層上沈積一第二導電層；及圖案化該高電壓額定介電層及該第二導電層以覆蓋該第一導電層之一區域以用於形成該高電壓額定隔離電容器，其中該第一導電層之至少一個經曝露部分提供至其之至少一個第一電連接。
根據該方法之又一實施例，可包括以下步驟：將該第一導電層圖案化成該高電壓額定隔離電容器之一第一極板；及將該第二導電層圖案化成該高電壓額定隔離電容器之一第二極板。根據該方法之又一實施例，可包括以下步驟：將該第一導電層圖案化成複數個高電壓額定隔離電容器之複數個第一極板；及將該第二導電層圖案化成該複數個高電壓額定隔離電容器之複數個第二極板。根據該方法之又一實施例，可包括在該第一導電層及該第二導電層上方進行鈍化之步驟，其中該鈍化覆蓋該第二導電層且將用於該至少一個第一電連接及該至少一個第二電連接之開口提供至該第二導電層。
根據該方法之又一實施例，該半導體積體電路可係一廢棄積體電路晶粒。根據該方法之又一實施例，該第一導電層及該第二導電層可係金屬。根據該方法之又一實施例，該第一導電金屬層及該第二導電金屬層可由鋁構成。根據該方法之又一實施例，該第一導電層及該第二導電層可由銅構成。根據該方法之又一實施例，該第一導電層及 該第二導電層可選自由以下各項組成之群組中之任何一或多者：鈦、鉭、鈷、鉬及其矽化物及自對準矽化物。
根據該方法之又一實施例，該高電壓額定介電層厚度可係藉由一耐電壓要求而判定。根據該方法之又一實施例，該高電壓額定介電層可包括二氧化矽(SiO2)。根據該方法之又一實施例，該高電壓額定介電層可包括氮化矽(SiN)。根據該方法之又一實施例，該高電壓額定介電層可包括氮氧化物。根據該方法之又一實施例，該高電壓額定介電層可包括不同厚度且藉由標準技術沈積或生長之摻雜氧化物或未摻雜氧化物之堆疊層。根據該方法之又一實施例，該高電壓額定介電層可具有大約四(4)微米(μ)之一厚度。根據該方法之又一實施例，該高電壓額定隔離電容器可具有大約10微微法拉之一電容值。
根據另一實施例，一種用於形成一高電壓額定隔離電容器之方法可包括以下步驟：提供一半導體積體電路；在該半導體積體電路之一面之至少一部分上沈積一絕緣層；在該絕緣層上沈積一第一導電層；在該第一導電層上沈積一高電壓額定介電層；圖案化該高電壓額定介電層以覆蓋該第一導電層之一區域且提供至其之至少一個開口；將一導電材料沈積至該至少一個開口中以用於形成至該第一導電層之至少一個第一電連接；在該高電壓額定介電層上沈積一第二導電層；及圖案化該第二導電層以覆蓋該第一導電層之一區域以用於形成該高電壓額定隔離電容器。
根據該方法之又一實施例，可包括以下步驟：將該第一導電層圖案化成該高電壓額定隔離電容器之一第一極板；及將該第二導電層圖案化成該高電壓額定隔離電容器之一第二極板。根據該方法之又一實施例，可包括以下步驟：將該第一導電層圖案化成複數個高電壓額定隔離電容器之複數個第一極板；及將該第二導電層圖案化成該複數個高電壓額定隔離電容器之複數個第二極板。根據該方法之又一實施 例，可包括在該第一導電層及該第二導電層上方進行鈍化之步驟，其中該鈍化覆蓋該第二導電層且將用於該至少一個第一電連接及該至少一個第二電連接之開口提供至該第二導電層。
根據再一實施例，一種經調適以具有不同電壓域之間的電壓隔離之積體電路器件可包括：一初級積體電路；在該初級積體電路之一面之至少一部分上之一第一絕緣層；在該第一絕緣層上之一第一導電層，其中該第一導電層可耦合至該初級積體電路上之一電路連接墊；在該第一導電層之一部分上之一高電壓額定介電層；及在該高電壓額定介電層上之一第二導電層，其中該第一導電層及該第二導電層以及該高電壓額定介電層形成一高電壓額定隔離電容器。
根據又一實施例，可提供具有耦合至該第二導電層之一電路連接墊之一次級積體電路，其中該初級積體電路可在一第一電壓域中且該次級積體電路可在一第二電壓域中。根據又一實施例，可在該第二導電層之至少一部分上方且在該高電壓額定介電層及該第一導電層之部分上方提供一第二絕緣層，其中該第二絕緣層可具有：在該第一導電層上方之一第一開口，其用於使一第一接合線將該第一導電層耦合至該初級積體電路上之該電路連接墊；及在該第二導電層上方之一第二開口，其用於使一第二接合線將該第二導電層耦合至該次級積體電路上之該電路連接墊。
根據又一實施例，可提供一種用於囊封該初級積體電路及該次級積體電路以及該高電壓額定隔離電容器之積體電路封裝。根據又一實施例，該第一導電層及該第二導電層可係金屬。根據又一實施例，該第一導電金屬層及該第二導電金屬層可由鋁構成。根據又一實施例，該第一導電層及該第二導電層可由銅構成。根據又一實施例，該第一導電層及該第二導電層可選自由以下各項組成之群組中之任何一或多者：鈦、鉭、鈷、鉬，及其矽化物及自對準矽化物。
根據又一實施例，該高電壓額定介電層可包括二氧化矽(SiO2)。根據又一實施例，該高電壓額定介電層可包括氮化矽(SiN)。根據又一實施例，該高電壓額定介電層可包括氮氧化物。根據又一實施例，該高電壓額定介電層可包括不同厚度且藉由標準技術沈積或生長之摻雜氧化物或未摻雜氧化物的堆疊層。根據又一實施例，該高電壓額定介電層可具有大約四(4)微米(μ)之一厚度。根據又一實施例，該高電壓額定隔離電容器可具有大約10微微法拉之一電容值。根據又一實施例，該初級積體電路可係一微控制器。
根據又另一實施例，一種經調適以具有不同電壓域之間之電壓隔離的積體電路器件可包括：一初級積體電路；在該初級積體電路之一面之至少一部分上方之一第一絕緣層；在該第一絕緣層上方之複數個第一高電壓額定隔離電容器，其中該複數個第一高電壓額定隔離電容器中之每一者可包括在該第一絕緣層上之一第一導電層，其中該等第一導電層中之某些導電層可耦合至該初級積體電路上之各別電路連接墊；在該複數個第一導電層中之一各別者之一部分上之一第一高電壓額定介電層；及在該各別高電壓額定介電層上之一第二導電層。
根據又一實施例，可提供具有耦合至各別第二導電層之電路連接墊之一第二積體電路，其中該初級積體電路可在一第一電壓域中，且該第二積體電路可在一第二電壓域中。根據又一實施例，可提供用於囊封該初級積體電路及該等第一高電壓額定隔離電容器之一積體電路封裝。根據又一實施例，該積體電路封裝可具有耦合至各別第一導電層的某些外部連接節點及耦合至該複數個第一高電壓額定隔離電容器之各別第二導電層的某些其他外部連接節點。根據又一實施例，該等外部連接節點可係該積體電路封裝引線框之引線指狀件，且該等各別引線指狀件可藉助接合線而耦合至該等第一導電層及該等第二導電層。
根據又一實施例，該積體電路器件可包括：在該等第二導電層之至少一部分上方之一第二絕緣層；在該第二絕緣層上方之複數個第二高電壓額定隔離電容器，其中該複數個第二高電壓額定隔離電容器中之每一者可包括在該第二絕緣層上之一第三導電層，其中該等第三導電層中之某些導電層可耦合至一第三積體電路上之各別電路連接墊；在該複數個第三導電層中之一各別者之一部分上之一第二高電壓額定介電層；及在該各別第二高電壓額定介電層上之一第四導電層，其中該等第四導電層中之某些導電層可耦合至該初級積體電路晶粒上之各別電路連接墊。
根據又一實施例，可提供用於囊封該初級積體電路及該第二積體電路以及該等第一高電壓額定隔離電容器之一積體電路封裝。根據又一實施例，可提供用於囊封該初級積體電路、該第二積體電路及該第三積體電路以及該等第一高電壓額定隔離電容器及該等第二高電壓額定隔離電容器之一積體電路封裝。根據又一實施例，該第三積體電路可在一第三電壓域中。根據又一實施例，該積體電路封裝可具有耦合至各別第四導電層之某些外部連接節點及耦合至該複數個第二高電壓額定隔離電容器之各別第三導電層之某些其他外部連接節點。根據又一實施例，該等外部連接節點可係該積體電路封裝引線框之引線指狀件且該等各別引線指狀件可藉助接合線耦合至該等第一導電層及該等第二導電層。
100‧‧‧高電壓額定隔離電容器/隔離電容器
100a‧‧‧高電壓額定隔離電容器/隔離電容器
100b‧‧‧隔離電容器
100c‧‧‧隔離電容器/回饋隔離耦合電容器
100d‧‧‧隔離電容器
100f‧‧‧隔離電容器
100e‧‧‧隔離電容器
102‧‧‧積體電路/初級積體電路
104‧‧‧絕緣層
106‧‧‧第一導電層
110‧‧‧高電壓額定介電層/高電壓額定絕緣層/絕緣介電層
112‧‧‧第二導電層/導電層
114‧‧‧第一墊開口/開口
116‧‧‧第二墊開口/開口
118‧‧‧第二積體電路/次級積體電路
120‧‧‧引線指狀件
120a‧‧‧引線指狀件
120e‧‧‧引線指狀件
122‧‧‧引線指狀件
122h‧‧‧引線指狀件
124‧‧‧接合線
124a‧‧‧接合線
124b‧‧‧接合線
124e‧‧‧接合線
126‧‧‧接合線
126a‧‧‧接合線
126b‧‧‧接合線
126e‧‧‧接合線
128‧‧‧接合線
130‧‧‧積體電路封裝
132‧‧‧導電材料
428‧‧‧驅動器
430‧‧‧驅動器
432‧‧‧波形產生器
434‧‧‧開關
444‧‧‧電壓電荷泵
446‧‧‧電壓調節器
528‧‧‧驅動器
530‧‧‧驅動器
532‧‧‧波形產生器/內部波形產生器
534‧‧‧開關
536‧‧‧輸出驅動器電路
538‧‧‧輸入電路
542‧‧‧輸入電路
544‧‧‧整流器
546‧‧‧電壓調節器
548‧‧‧脈衝寬度調變調變器
700‧‧‧高電壓額定隔離電容器/隔離電容器
704‧‧‧絕緣層/電絕緣層
706‧‧‧第四導電層
708‧‧‧絕緣層
710‧‧‧絕緣介電層
712‧‧‧第三導電層
714‧‧‧第四墊開口
716‧‧‧第三墊開口
730‧‧‧積體電路封裝
818‧‧‧次級積體電路
830‧‧‧積體電路封裝
VDD‧‧‧供應電壓
VDD-ISO‧‧‧經隔離電壓
可結合附圖藉由參考以下說明獲得對本發明之一更完整理解，其中：圖1及圖1A圖解說明根據本發明之一特定實例性實施例之形成於一積體電路上之一高電壓額定隔離電容器之示意性立面視圖；圖1B及圖1C圖解說明根據本發明之另一特定實例性實施例之形 成於一積體電路上之一高電壓額定隔離電容器之示意性立面視圖；圖2圖解說明根據本發明之特定實例性實施例之形成於一積體電路上之一高電壓額定隔離電容器之一示意性正交視圖；圖3圖解說明根據本發明之特定實例性實施例之形成於一初級積體電路上且耦合至一次級積體電路之複數個高電壓額定隔離電容器之一示意性平面視圖；圖4圖解說明根據本發明之特定實例性實施例之將電力電路及信號電路耦合於一初級積體電路與一次級積體電路之間的複數個高電壓額定隔離電容器之一示意性方塊圖；圖5圖解說明根據本發明之另一特定實例性實施例之將電力電路及信號電路耦合於一初級積體電路與一次級積體電路之間的複數個高電壓額定隔離電容器之一示意性方塊圖，其中該次級積體電路之電路控制自初級積體電路至次級積體電路之電力傳送；圖6圖解說明根據本發明之教示之一10微微法拉(pF)電容器之電流攜載能力對施加至其之信號頻率之一表格及一圖表；圖7及圖7A圖解說明根據本發明之另一特定實例性實施例之形成於一積體電路上之複數個反轉堆疊高電壓額定隔離電容器之示意性立面視圖；及圖8圖解說明根據本發明之另一特定實例性實施例之形成於一初級積體電路上且耦合至第一次級積體電路及第二次級積體電路之複數個高電壓額定隔離電容器之一示意性平面視圖。
雖然本發明易於發生各種修改及替代形式，但在圖式中展示並在本文中詳細闡述其特定實例性實施例。然而，應理解，本文中對特定實例性實施例之說明並非意欲將本發明限於本文中所揭示之特定形式，而是相反，本發明意欲涵蓋如隨附申請專利範圍所界定之所有修改及等效形式。
根據各種實施例，可提供一種用於在一積體電路晶粒上建構高電壓額定隔離電容器之方法及裝置。根據各種實施例，本文中揭示一種形成低成本高電壓額定電容器之方法。本文中揭示一種形成具有特殊電極幾何形狀及低成本SiO2介電材料之一高電壓額定電容器之獨特方法，特殊電極幾何形狀及低成本SiO2介電材料促進製成在其下可具有主動電路之積體電路矽上面僅需要一小面積的基於低成本SiO2之介電絕緣高電壓額定電容器。
可產生與主要供應源電隔離之一經隔離供應電壓。對於現代電子系統設計，此一特徵可變為要求極高的。DC對DC隔離及AC對DC隔離係其實例。一電容隔離器件可使用(a)跨越一電容隔離障壁將電力自初級側傳送至次級側之一方法；及(b)使用一回饋網路調節經隔離次級電力之一方法。針對此一應用，需要高電壓額定值(>3000Vrms)矽電容器以在不同通信器件之間形成一電(例如，流電)隔離障壁。此高電壓額定電容器可用於(a)經隔離DC對DC電力傳送及(b)連接至不同電壓域之器件之間的經隔離資料通信。
根據各種實施例，舉例而言，可藉助簡單處理使用廢棄積體電路晶圓以基於二氧化矽(Si02)及鋁而製成適用於一堆疊式積體電路封裝中之本文中所闡述之隔離電容器。可選擇電絕緣氧化物厚度來耐受數千伏特且所得電容為足夠高以達成連接至兩個不同電壓域之積體電路器件之間的有效電力及信號傳送。
使用堆疊晶粒Si02絕緣之電容器被認為產生過低之一電容值。然而，根據本發明之各種實施例，藉由使用各種電路技術(例如，較高電壓電晶體、電壓二倍器及三倍器等)以用於跨越此等電容器提供一較高電壓，可以用於有效電力及信號傳送之足夠電容製作該等電容器。
現在參考圖式，示意性地圖解說明實例性實施例之細節。圖式中之相似元件將由相似編號表示，且相似元件將由帶有一不同小寫字母後綴之相同編號表示。
參考圖1及圖1A，繪示根據本發明之一特定實例性實施例之形成於一積體電路上之一高電壓額定隔離電容器之示意性立面視圖。通常由數字100表示之一高電壓額定隔離電容器可包括一第一導電層106、一第二導電層112、在分別第一導電層106與第二導電層112之間的一高電壓額定介電(絕緣)層110及在第二導電層112及第一導電層106之一部分上方之一絕緣(例如，鈍化)層108。一第一墊開口114可用於提供對第一導電層106之電接達。一第二墊開口116可用於提供對第二導電層112之電接達。高電壓額定隔離電容器100可定位於置於一積體電路102上之一絕緣層104上方且附接至絕緣層104。
可使用用以形成第一導電層106之一第一遮罩及用以形成第二導電層112之一第二遮罩及高電壓額定介電層110來製作至少一個高電壓額定隔離電容器100。一第三遮罩可用於在絕緣(例如，鈍化)層108中分別形成第一墊開口114及第二墊開口116。預期且在本發明之範疇內，可以同樣成功使用其他程序製作步驟，且熟習積體電路製作技術者及受益於本發明者可想出此等替代設計且仍在本發明之精神及意圖內。
第一導電層106及第二導電層112分別可包括一導電金屬材料，諸如(舉例而言但不限於)鋁、銅、鈦、鉭、鈷、鉬、其矽化物及自對準矽化物等。絕緣層104可係(舉例而言但不限於)二氧化矽(SiO2)、氮化矽(SiN)、氮氧化物或不同厚度且藉由標準技術沈積或生長之摻雜氧化物或未摻雜氧化物之堆疊層等。高電壓額定介電層110可係(舉例而言但不限於)二氧化矽(SiO2)、氮化矽(SiN)、SiOxNy、氧化物-氮化物-氧化物(ONO)等。絕緣介電層110之厚度可判定高電壓額定隔離電容 器100之耐電壓能力，且針對大約一3,000伏DC絕緣崩潰電壓可係(舉例而言但不限於)大約四(4)微米厚SiO2。絕緣層108可係具有用於連接至低電壓墊之開口114及用於連接至高電壓墊之開口116之一保護性鈍化層，例如，二氧化矽、氮化矽等。術語「高電壓墊」及「低電壓墊」係指不具有用於電力、接地或信號之直流(DC)連接之不同電壓域。電壓域之間的電壓差可係大的或小的，且進一步可用於保護及隔離器件免受大電壓暫態，例如，保護及隔離感測器免受可因閃電、電力切換暫態等造成之感應電動勢(EMF)電壓。
現在參考圖1A，高電壓額定隔離電容器100總成之第一導電層106可藉助接合線124連接至引線指狀件120及/或在積體電路102(在下文為「初級IC 102」)上之連接墊。高電壓額定隔離電容器100總成之導電層112可藉助接合線126而連接至一第二積體電路118(下文稱為「次級IC 118」)上之連接墊及/或引線指狀件122。次級IC 118可藉助接合線128而連接至引線指狀件122。初級IC 102可經組態以在一第一電壓域中操作，且次級IC 118可經組態以在一第二電壓域中操作。第一電壓域與第二電壓域之間的接地電位及電壓電位可係數千伏差異，而僅受高電壓額定介電層110之耐電壓(崩潰)(例如，其厚度)限制。引線指狀件120可耦合至第一電壓域，且引線指狀件122可耦合至第二電壓域。初級IC 102、高電壓額定隔離電容器100、次級IC 118以及引線指狀件120及122之部分可囊封於一積體電路封裝130(例如，環氧樹脂)中。為說明清楚起見而未展示晶粒座(die paddle)(若使用)。預期且在本發明之範疇內，可使用除引線指狀件之外的其他積體電路外部連接節點，例如，球凸塊等。
參考圖1B及圖1C，所繪示者係根據本發明之另一特定實例性實施例之形成於一積體電路上之一高電壓額定隔離電容器之示意性立面視圖。通常由數字100a表示之一高電壓額定隔離電容器可包括一第一 導電層106、一第二導電層112、在分別第一導電層106與第二導電層112之間之一高電壓額定介電(絕緣)層110及在第二導電層112及第一導電層106之一部分上方之一絕緣(例如，鈍化)層108。導電材料132可用於填充可在第一導電層106上方之高電壓額定介電層110中之一開口中。導電材料132可用於提供對第一導電層106之電接達。一第二墊開口116可用於提供對第二導電層112之電接達。高電壓額定隔離電容器100a可定位於置於一積體電路102上之一絕緣層104上方且附接至絕緣層104。高電壓額定隔離電容器100a之操作與上文所闡述之高電壓額定隔離電容器100之操作實質上相同。
參考圖2，繪示根據本發明之特定實例性實施例之形成於一積體電路上之一高電壓額定隔離電容器之一示意性正交視圖。高電壓額定隔離電容器100經展示為附接至初級IC 102且藉助接合線124而連接至某些引線指狀件120，藉助接合線124a而連接至初級IC 102，藉助接合線126而連接至次級IC 118，及/或藉助接合線128a而連接至引線指狀件122。高電壓額定隔離電容器100可附接至在初級IC 102之一面上之一絕緣層104，例如，鈍化層。
參考圖3，繪示根據本發明之特定實例性實施例之形成於一初級積體電路上且耦合至一次級積體電路之複數個高電壓額定隔離電容器之一示意性平面視圖。複數個高電壓額定隔離電容器100可置於一絕緣層104上的初級IC 102上方(圖1及圖1A)。複數個高電壓額定隔離電容器100中之每一者可用於直流(DC)隔離在一第一電壓域中之一引線指狀件120與在一第二電壓域中之次級IC 118之一信號或電力墊(例如，引線指狀件120a、接合線124a、隔離電容器100a、接合線126a及次級IC 118之連接墊)。自初級IC 102之一信號墊至次級IC 118之一信號墊(例如，接合線124b、隔離電容器100b、接合線126b及次級IC 118之連接墊)。自在第一電壓域中之一引線指狀件120e至在第二電壓域 中之一引線指狀件122h(例如，接合線124e、隔離電容器100e、接合線126e及引線指狀件122h)。
可在必要時針對一特定應用連接複數個高電壓額定隔離電容器100。可如圖1及圖1A中所展示及上文所闡述形成高電壓額定隔離電容器100中之每一者。預期且在本發明之範疇內，高電壓額定隔離電容器100可以所要之任何幾何形狀形成且其不限於如圖3中所展示之特定實例性實施例中所展示之正方形或矩形形狀。
參考圖4，繪示根據本發明之特定實例性實施例之將電力電路及信號電路耦合於一初級積體電路與一次級積體電路之間的複數個高電壓額定隔離電容器之一示意性方塊圖。可透過複數個高電壓額定隔離電容器100(例如，隔離電容器100a至100f)使用一交流(AC)電壓隔離電力及將電力自第一電壓域傳送至第二電壓域，或反之亦然。可藉由一波形產生器432(例如，振盪器)、由脈衝寬度調變(PWM)調變器控制之電力開關等產生此AC電壓，或當閉合一開關434且波形產生器432不作用時產生一外部脈衝寬度調變(PWM)信號。驅動器430及428可透過隔離電容器100a至100f將不需要一接地參考之一推拉(例如，差動信號)波形提供至一電壓電荷泵444，電壓電荷泵444然後可將一經隔離電壓提供至在第二電壓域中之一電壓調節器446。可提供且藉助較小串聯連接之電容器438及440(增加之耐電壓)或藉由額外隔離電容器100 DC隔離在第一電壓域中之可程式化輸入/輸出(I/O)436與在第二電壓域中之可程式化輸入/輸出(I/O)442。
參考圖6，繪示根據本發明之教示之一10微微法拉(pF)電容器之電流攜載能力對施加至該電容器之信號頻率之一表格及一圖表。隔離電容器100可較佳地具有大約10微微法拉之一電容值。圖6中所展示之表格及圖表提供一10pF電容器之在不同頻率下之電流攜載能力。當一個10pF電容器無法在一所要頻率下供應足夠量之電容時，那麼添 加並聯連接之隔離電容器100可係適當的，例如，參見圖4，隔離電容器100a至100f。
返回參考圖4，自信號輸出驅動器至信號輸入驅動器之低階信號可具有低得多之信號電流要求，例如，較高阻抗。因此，可有效地使用小值電容器，例如，大約一(1)pF。電容器438及440可具有與隔離電容器100相同之構造，或積體電路製作技術中已知之構造。任何電容器阻擋DC，因此將藉助用於長期資料邏輯位準保持之鎖存器或暫存器邊沿觸發在第一電壓域及第二電壓域中之電路之間的較佳地信號資料傳送。此等隔離電容器100亦可用於微控制器及其他類比產品中之供電應用且不僅限於隔離器件。
參考圖5，繪示根據本發明之另一特定實例性實施例之將電力電路及信號電路耦合於一初級積體電路與一次級積體電路之間的複數個高電壓額定隔離電容器之一示意性方塊圖，其中次級積體電路之電路控制自初級積體電路至次級積體電路之電力傳送。可透過高電壓額定隔離電容器100(例如，隔離電容器100a及100b)使用一交流(AC)電壓隔離電力及將電力自第一電壓域傳送至第二電壓域，或反之亦然。可藉由一波形產生器532(例如，振盪器)、由脈衝寬度調變(PWM)調變器控制之電力開關等產生此AC電壓，或當閉合一開關534且波形產生器532不作用時產生一外部脈衝寬度調變(PWM)信號。波形產生器532將一AC電壓提供至驅動器530及528，且驅動器530及528可透過隔離電容器100a及100b將不需要一接地參考之一推拉(例如，差動信號)波形提供至在第二電壓域中之一整流器544。
整流器544將一DC電壓提供至提供在第二電壓域中之一電源電壓之一電壓調節器546。電壓調節器546亦可將一內部電壓參考(未展示)與經隔離電壓VDD-ISO之間的一誤差電壓提供至一PWM調變器548。PWM調變器548之輸出透過隔離電容器100c將一回饋控制信號提供至 波形產生器532或一外部PWM產生器(未展示)。依據此回饋控制信號，波形產生器532可使其輸出振幅及/或頻率變化以維持(例如)次級IC 118之一所要經隔離電壓VDD-ISO。因此，可將一經隔離、高效率、經調節電壓自第一電壓域提供至第二電壓域。舉例而言，來自第一電壓域之經隔離輸入可由一輸入電路538接收且透過隔離電容器100e至一輸出驅動器電路544隔離耦合至第二電壓域。類似地，舉例而言，來自第二電壓域之經隔離輸入可由一輸入電路542接收且透過隔離電容器100d至一輸出驅動器電路536隔離耦合至第一電壓域。
應注意，在第一電壓域中之供應電壓(VDD)使用一內部波形產生器532轉移為AC能量，且透過隔離電容器100a及100b跨越隔離障壁傳送至第二電壓域側。DC供應電壓(VDD-ISO)可自來自隔離電容器100a及100b之經整流AC信號發展，且透過由PWM調變器548及回饋隔離耦合電容器100c形成之一回饋電路經調節。
波形產生器532亦可係受PWM調變器548控制之一PWM產生器。預期且在本發明之範疇內，可使用一外部PWM產生器(未展示)且藉由PWM調變器548控制其。
參考圖7及圖7A，繪示根據本發明之另一特定實例性實施例之形成於一積體電路上之複數個反向堆疊高電壓額定隔離電容器之示意性立面視圖。通常由數字700表示之另一高電壓額定隔離電容器可包括在第二導電層112上方之一絕緣層704、在絕緣層704上方之一第三導電層712、在第三導電層712之一部分上方之一絕緣介電層710、在絕緣介電層710上方之一第四導電層706及在第四導電層706及第三導電層712之一部分上方之一絕緣層708。在絕緣層708中之一第三墊開口716可提供對第三導電層712之電連接接達。在絕緣層708中之一第四墊開口714可提供對第四導電層706之電連接接達。
高電壓額定隔離電容器700可定位於置於初級IC 102上之高電壓 額定隔離電容器100上方且附接至高電壓額定隔離電容器100。高電壓額定隔離電容器700之構造可與高電壓額定隔離電容器100實質上相同，惟分別第三導電層712及第四導電層706可係反轉的以使得一較不厚之電絕緣物(例如，電絕緣層704)必須放置於隔離電容器100與700之間以便維持第一電壓域與第二電壓域之間的一所要電壓崩潰額定值除外。初級IC 102及次級IC 118以及隔離電容器100及700可囊封(封裝)於一積體電路封裝730中。
參考圖8，繪示根據本發明之另一特定實例性實施例之形成於一初級積體電路上且耦合至第一積體電路及第二次級積體電路之複數個高電壓額定隔離電容器之一示意性平面視圖。隔離電容器100及700可垂直於彼此經放置且另一次級IC 818可耦合至隔離電容器700。此允許兩個或兩個以上次級IC與初級IC 102一起經封裝，例如，IC封裝830。次級IC 118及818可兩者皆在一第二電壓域中，或次級IC 118可在第二電壓域中且次級IC 818可在第三電壓域中，其中次級IC 118及818兩者可與在第一電壓域中之初級IC 102完全隔離。另外，次級IC 118及818可在組態於第二電壓域及第三電壓域中時彼此隔離。初級IC 102可包括一微控制器等，且次級IC 118/818可係數位信號處理器(DSP)、充電時間量測單元(CTMU)、協同處理器、專用輸入輸出介面、計數器、計時器、類比轉數位轉換器(ADC)、數位轉類比轉換器(DAC)等。初級IC 102及次級IC 118及818以及隔離電容器100及700可囊封(封裝)於一積體電路封裝830中。
可在必要時針對一特定應用連接複數個高電壓額定隔離電容器100及700。可如圖7及圖7A中所展示及上文所闡述而形成高電壓額定隔離電容器100及700中之每一者。預期且在本發明之範疇內，高電壓額定隔離電容器100及700可以所要之任何幾何形狀形成且其不限於如圖3及圖8中所展示之特定實例性實施例中所展示之正方形或矩形形 狀。
雖然本發明易於發生各種修改及替代形式，但在圖式中展示並在本文中詳細闡述其特定實例性實施例。然而，應理解，本文中對特定實例性實施例之說明並非意欲將本發明限於本文中所揭示之特定形式，而是相反，本發明意欲涵蓋如隨附申請專利範圍所界定之所有修改及等效形式。

Claims (22)

  1. 一種用於形成一高電壓額定隔離電容器之方法，該方法包括以下步驟：提供一半導體積體電路；在該半導體積體電路之一面的至少一部分上沈積一絕緣層；在該絕緣層上沈積一第一導電層；在該第一導電層上沈積一高電壓額定介電層，該高電壓額定介電層具有藉由一耐電壓要求而判定之一厚度；在該高電壓額定介電層上沈積一第二導電層；及圖案化該高電壓額定介電層及該第二導電層以覆蓋該第一導電層之一區域之至少一部分，以用於形成該高電壓額定隔離電容器，其中該第二導電層之至少一個經曝露部分提供至其之至少一個第一電連接，該至少一個第一電連接與該半導體積體電路絕緣。
  2. 如請求項1之方法，進一步包括以下步驟：將該第一導電層圖案化成該高電壓額定隔離電容器之一第一極板；及將該第二導電層圖案化成該高電壓額定隔離電容器之一第二極板。
  3. 如請求項1之方法，進一步包括以下步驟：將該第一導電層圖案化成複數個高電壓額定隔離電容器之複數個第一極板；及將該第二導電層圖案化成該複數個高電壓額定隔離電容器之複數個第二極板。
  4. 如請求項1之方法，進一步包括在該第一導電層及該第二導電層上方進行鈍化之步驟，其中該鈍化覆蓋該第二導電層且將用於該至少一個第一電連接及至少一個第二電連接之開口提供至該第二導電層。
  5. 如請求項1之方法，其中該半導體積體電路係一廢棄積體電路晶粒。
  6. 如請求項1至5中之任一項之方法，其中沈積一高電壓額定介電層之步驟進一步包括：圖案化該高電壓額定介電層以覆蓋該第一導電層之一區域且提供至其之至少一個開口；及將一導電材料沈積至該至少一個開口中，以用於形成至該第一導電層之至少一個第一電連接。
  7. 如請求項6之方法，其中該第一導電層及該第二導電層包括金屬、鋁或銅或選自由以下各項組成之群組中之任何一或多者：鈦、鉭、鈷、鉬及其矽化物及自對準矽化物。
  8. 如請求項1之方法，其中該高電壓額定介電層包括二氧化矽(SiO2)、氮化矽(SiN)或氮氧化物。
  9. 如請求項1之方法，其中該高電壓額定介電層包括不同厚度且由標準技術沈積或生長之摻雜氧化物或未摻雜氧化物之堆疊層。
  10. 如請求項1之方法，其中該高電壓額定介電層具有大約四(4)微米(μ)之一厚度及/或該高電壓額定隔離電容器具有大約10微微法拉之一電容值。
  11. 一種經調適以具有不同電壓域之間之電壓隔離的積體電路器件，其包括：一初級積體電路；在該初級積體電路之一面之至少一部分上之一第一絕緣層；在該第一絕緣層上之一第一導電層，其中該第一導電層經組態以經由一接合線耦合至一引線指狀件或在該初級積體電路上之一電路連接墊；在該第一導電層之一部分上之一高電壓額定介電層；及 在該高電壓額定介電層上之一第二導電層，其中該第二導電層包括與該初級積體電路電絕緣之一接觸墊區域，其中該第一導電層及該第二導電層以及該高電壓額定介電層形成一高電壓額定隔離電容器。
  12. 如請求項11之積體電路器件，進一步包括具有經由一接合線耦合至該第二導電層之一電路連接墊之一次級積體電路，其中該初級積體電路在一第一電壓域中，且該次級積體電路在一第二電壓域中。
  13. 如請求項12之積體電路器件，進一步包括在該第二導電層之至少一部分上方且在該高電壓額定介電層及該第一導電層之部分上方之一第二絕緣層，其中該第二絕緣層具有在該第一導電層上方之一第一開口，用於使一第一接合線將該第一導電層耦合至該初級積體電路上之該電路連接墊，及在該第二導電層上方之一第二開口，用於使一第二接合線將該第二導電層耦合至該次級積體電路上之該電路連接墊。
  14. 如請求項13之積體電路器件，進一步包括囊封該初級積體電路及該次級積體電路以及該高電壓額定隔離電容器之一積體電路封裝。
  15. 如請求項11之積體電路器件，其中該第一導電層及該第二導電層包含金屬、鋁或銅或係選自由以下各項組成之群組中之任何一或多者：鈦、鉭、鈷、鉬及其矽化物及自對準矽化物。
  16. 如請求項11之積體電路器件，其中該高電壓額定介電層包括二氧化矽(SiO2)、氮化矽(SiN)或氮氧化物。
  17. 如請求項11之積體電路器件，其中該高電壓額定介電層包括不同厚度且藉由標準技術沈積或生長之摻雜氧化物或未摻雜氧化物之堆疊層。
  18. 如請求項11之積體電路器件，其中該高電壓額定介電層具有大約四(4)微米(μ)之一厚度及/或該高電壓額定隔離電容器具有大約10微微法拉之一電容值。
  19. 如請求項11之積體電路器件，其包括：在該第一絕緣層上方之複數個第一高電壓額定隔離電容器，其中該複數個第一高電壓額定隔離電容器中之每一者包括在該第一絕緣層上之一第一導電層，其中該等第一導電層中之某些導電層耦合至該初級積體電路上之各別電路連接墊；在該複數個第一導電層中之一各別者之至少一部分上之一第一高電壓額定介電層；及在該各別高電壓額定介電層上之一第二導電層。
  20. 如請求項11之積體電路器件，其包括一積體電路封裝，其具有耦合至各別第一導電層的某些外部連接節點，及耦合至該複數個第一高電壓額定隔離電容器之各別第二導電層的某些其他外部連接節點。
  21. 如請求項20之積體電路器件，其中該等外部連接節點係積體電路封裝引線框之引線指狀件，且該等各別引線指狀件藉助接合線而耦合至該等第一導電層及該等第二導電層。
  22. 如請求項11之積體電路器件，進一步包括：在該等第二導電層之至少一部分上方之一第二絕緣層；在該第二絕緣層上方之複數個第二高電壓額定隔離電容器，其中該複數個第二高電壓額定隔離電容器中之每一者包括在該第二絕緣層上之一第三導電層，其中該等第三導電層中之某些導電層耦合至一第三積體電路上之各別電路連接墊； 在該複數個第三導電層中之一各別者之至少一部分上之一第二高電壓額定介電層；及在該各別第二高電壓額定介電層上之一第四導電層，其中該等第四導電層中之某些導電層耦合至初級積體電路晶粒上之各別電路連接墊。
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