CN104952869A - 具有多个雪崩二级管的esd保护电路 - Google Patents

具有多个雪崩二级管的esd保护电路 Download PDF

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CN104952869A
CN104952869A CN201510128280.9A CN201510128280A CN104952869A CN 104952869 A CN104952869 A CN 104952869A CN 201510128280 A CN201510128280 A CN 201510128280A CN 104952869 A CN104952869 A CN 104952869A
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CN104952869B (zh
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H·L·爱德华兹
A·A·萨尔曼
L·于
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Abstract

本发明涉及具有多个雪崩二级管的ESD保护电路。公开了一种静电放电(ESD)保护电路(图3C)。该电路包括具有基极、集电极和发射极的双极晶体管(304)。多个二极管(308-316)中的每个二极管具有耦合到基极的第一端子和耦合到集电极的第二端子。集电极连接到第一端子(V+)。发射极连接到电源端子(V-)。

Description

具有多个雪崩二级管的ESD保护电路
技术领域
本发明的实施例涉及具有初级放电装置和多个雪崩二极管的静电放电(ESD)保护电路。该电路的优选实施例意图用在集成电路的输入端子、输出端子、输入-输出端子或者电源端子处。
背景技术
参照图1A，其为由Yu在美国专利6,472,286中所公开的现有技术的ESD保护电路。图1A的电路是多指NPN双极晶体管的横截面，如在第3栏第31行至第4栏第8行中所描述的。该电路被制造在具有重掺杂N+层12的P型衬底10上。在层12上方形成N型层14。在衬底10的表面处形成P型基极区域24，并且将其连接至P+区域22。在基极区域24内形成N+发射极区域26。将深N+区域16连接到N+层12并且用作集电极表面触点。集电极区域、基极区域以及发射极区域各自的表面触点18、20以及28在衬底10的表面上方形成。
图1B公开了如图1A所示的双极NPN晶体管的典型的电流-电压特性(第1栏第31-61行)。该波形示出了双极NPN晶体管特性的三个感兴趣的点。首先是初始的集电极-基极击穿电压BVcbo，其也可以被称为集电极-基极雪崩阈值、第一击穿或者Vt1、It1。第二个点是BVceo，其也可以被称为转折电压(snapback voltage)。第三个点是Vt2、It2，其为NPN雪崩传导和第二击穿之间的过渡点。
图1A的电路以及图1B的关联的电流-电压特性存在一些问题。首先，BVcbo大约是18V并且可能超过ESD保护电路要保护的现代集成电路的损坏阈值(Vdam)。其次，BVceo大约是8V并且可能小于ESD保护电路要保护的集成电路的工作电压，由此，在ESD事件之后导致过度电性应力(EOS)。最后，图1A的深N+集电极触点区域16必须与P+基极接触区域22隔开，以避免雪崩传导并且为集成电路的随后的高温处理步骤中的横向扩散提供足够的区域。本发明的各种实施例针对解决这些问题和其他问题，并且提高ESD保护电路的操作，而不增加工艺复杂性。
发明内容
在本发明的优选实施例中，公开了一种静电放电(ESD)保护电路。该ESD保护电路包括具有基极、集电极以及发射极的双极晶体管。多个二极管中的每个二级管具有耦合到基极的第一端子并且具有耦合到集电极的第二端子。第一端子连接到集电极。第一电源端子连接到发射极。
附图说明
图1A是现有技术的静电放电(ESD)保护电路的电路图；
图1B是如图1A所示的双极NPN ESD保护晶体管的电流-电压(IV)特性；
图2是本发明的ESD保护电路的第一实施例的简化平面图。
图3A是图2的实施例沿线3A-3A’的平面图；
图3B是图3A的实施例沿线3B-3B’的横截面图；
图3C是图3A和图3B的实施例的原理图；
图4是本发明的第一实施例的、具有500ns和100ns脉冲宽度的所测得的传输线脉冲(TLP)波形；
图5是本发明的ESD保护电路的第二实施例的原理图；以及
图6是本发明的ESD保护电路的第三实施例的原理图。
具体实施方式
本发明的优选实施例提供超过现有技术的静电放电(ESD)保护电路的显著优势，这将从以下具体实施方式变得明显。
参照图2，其为本发明的ESD保护电路的第一实施例的简化平面图。图2的实施例将参照沿横截平图3A-3A'获取的图3A和图3B更详细地讨论。在此及下面的讨论中，相同的参考数字被用于指示基本上相同的特征。图2的保护电路优选地形成在集成电路衬底上并且包括多个(plural)垂直双极晶体管。双极晶体管可以是NPN或PNP，如本领域技术人员在阅读本说明书之后显而易见的。双极晶体管包括在衬底的一面处以及在保护电路的中心处形成的各自的并联/平行(parallel)的发射极(E)区域和基极(B)区域。并联的发射极区域和基极区域由同心且相互交叉的集电极(C)区域和基极(B)区域围绕。同心且相互交叉的集电极区域和基极区域被紧密间隔，以在多个垂直双极晶体管的集电极区域和基极区域之间形成多个PN二极管。
现在转向图3A和图3B，其分别是图2的ESD保护电路的实施例沿线3A-3A’和3B-3B’的对应的平面图和横截面图。图3A-3B将参照图3C的原理图讨论。图3A是图2的实施例在线3A-3A’处的详细的平面图。基极区域340、发射极区域342以及集电极区域344被示为通过线来连接，这些线优选指示通过通孔连接到相应的半导体区域的金属，如本领域已知的。诸如320、330、334以及338的N+半导体区域被形成在半导体衬底302的表面处，如点填充所指示的。诸如322、332以及336的P+半导体区域被形成在半导体衬底302的表面处，如线填充所指示的。N+区域和P+区域通过由无填充的矩形所指示的浅沟槽隔离(STI)区域(例如，328)来隔离。有源区域也可以由硅的局部氧化(LOCOS)来隔开，如本领域已知的。每个N+区域连接到相应的浅N阱(NW)区域。同样地，每个P+区连接到相应的浅P阱(PW)区域。在衬底302的表面下方形成N型掩埋层(NBL)300。NBL 300通过深N+注入(DN)318电连接到集电极端子344。NPN双极晶体管304和306并联连接并且分别具有形成在NBL 300和发射极342之间的垂直的集电极-发射极电流路径。NPN晶体管304和306的基极区域通过衬底302、P+以及浅P阱区域连接至基极端子340。衬底区域302通过NBL 300和周围的深N+注入318与集成电路的其他区域电隔离。
在相邻的PW区域和NW区域之间形成二极管308至316。二极管310至316中的每个二极管的相邻PW区域和NW区域之间的间距是基本相同的，并且小于二极管308的PW至NW的间距。因此，二极管310至316具有比二极管308低的雪崩阈值。电阻器360至368分别表示与二极管308至316串联的寄生电阻。
现将参照图3C的原理图和图4的传输线脉冲(TLP)波形对图3A至图3B的ESD保护电路的操作进行描述。图4示出脉冲宽度为100ns和500ns的所测得的TLP波形，其中正电压对应于端子344(V+)处相对于端子342(V-)的正电压。在正常电路操作期间，NPN晶体管304和306都是断开的，因为它们没有接收基极电流。随着电压V+变得更加正的并且超过二极管310-316的雪崩阈值，电流分别流过串联电阻器362-368并且流入NPN晶体管304和306的基极。NPN晶体管304和306因此在31V处开始双极传导。对于100ns的波形，当集电极-发射极电压(Vce)降低到在0.6A下18V的转折电压或保持电压时，流过NPN晶体管304和306的集电极电流增大。随着电流变得越来越正，100ns的TLP波形呈现出正斜率，该正斜率对应于电流路径电阻和寄生电路电阻。对于500ns的TLP波形，ESD保护电路以类似的方式运行，除了转折电压或保持电压处于稍高于25V之外。这是由于高注入效应，其中基极区域中注入的少数载流子密度(电子)接近基极杂质浓度，由此降低发射极效率。发射效率进一步由于发射极集边效应而降低，从而使发射极周边处的电流密度比发射极中心高。在转折之后，500ns的TLP波形也呈现出对应于电流路径电阻和寄生电路电阻的正斜率。
图3A-3C的ESD保护电路提供超过现有技术的电路的几个显著优点。第一，仅需要单个深N+集电极注入318来围绕NPN晶体管304和306以及二极管308至316。这使得ESD保护电路的面积显著减少。第二，二极管308至316以及NPN晶体管304和306被形成在相同的隔离的基极区域302中。这有利地提高了NPN开启。另外，二极管的阳极端子332和336以金属连接到NPN P+基极触点，所以由于基极电流而导致的衬底302中的横向电压降可忽略。第三，相邻的PW到NW间距被调节以设置二极管310至316的雪崩阈值。这有利地设置了ESD保护电路的触发电压，并保证该触发电压将小于受保护的电路350的损坏阈值。第五，二极管的阳极端子和阴极端子在相邻二极管之间共享，由此进一步减小面积。最后，NPN晶体管304和306被有利地设计为具有多个并联的发射极指，如图2和图3A所示。这有利地增加发射极的周长面积比，由此提高了高注入下的发射极效率。
现在转到图5，图5是本发明的ESD保护电路的第二实施例的原理图。除了增加电阻器500之外，这个实施例与之前针对图2和图3A-3C所描述的相同。电阻器500是NPN晶体管304和306的基极-发射极分流电阻器。通常，当电阻器500较大时，例如大于1kΩ，电路以与图3A-3C所描述的相同方式运行。当电阻器500较小时，例如金属分流，电路如同并联的雪崩二极管310至316运行。因此，可以通过选择电阻器500的合适值来调整图5的ESD保护电路的转折电压或保持电压。这有利地提供了独立选择ESD保护电路的触发电压和转折电压或保持电压的方法。电路的触发电压是通过如先前所描述地设置二极管310-316的雪崩阈值来选择的。电路的转折电压或保持电压是通过电阻器500的适当值来选择的，并且优选在NPN晶体管的BVceo和BVcbo之间。这个独立可编程性适合于具有多种工作电压的广泛的ESD保护电路应用。
现在参照图6，其是本发明的ESD保护电路的第三实施例的原理图。除了NPN晶体管304和306由半导体受控整流器(SCR)代替之外，这个实施例类似于先前描述的图2和图3A-3C的实施例。具体地，NPN晶体管304被替换为包括PNP晶体管600和NPN晶体管602的第一SCR。NPN晶体管306被替换为包括PNP晶体管604和NPN晶体管606的第二SCR。电阻器500是NPN晶体管602和606的基极-发射极分流电阻器。电阻器608是PNP晶体管600和604的基极-发射极分流电阻器。电阻器500和608有几个用途。第一，这两个电阻器被选择以确保SCR在正常电路操作期间不会锁存。第二，电阻器500和608被独立地选择以匹配相应的NPN和PNP晶体管的电流增益。这提供了一种设置SCR保持电压的方法，即使NPN和PNP晶体管的电流增益非常不同。最后，该电路的触发电压是通过如先前所描述地设置二极管310-316的雪崩阈值来选择的。该电路的保持电压是通过电阻器500和608的适当值来选择的，并且优选在二极管310-316的正向偏置二极管压降和雪崩阈值之间。这有利地提供一种独立选择电路的触发电压和保持电压的方法。此外，对于低电压应用，与仅具有NPN晶体管的实施例相比，由于电流电压积较低，SCR可以消耗少得多的功率，并且因此产生少得多的热量。独立可编程性适合于具有多种工作电压的广泛的ESD保护电路应用。
鉴于前述解释，重要的是，ESD保护电路的各种实施例的触发电压或开关电压小于受保护的电路350(图3C、图5以及图6)的损坏阈值(Vdam)。同样重要的是，ESD保护电路的转折电压或保持电压大于受保护的电路的工作电压。这确保了当功率被施加到受保护的电路350时，ESD脉冲的施加不会造成ESD保护电路由于来自电源的过度电性应力(EOS)而失效。
更进一步地，尽管已经提供了大量示例，但是本领域技术人员应认识到，可以对描述的实施例进行各种修改、替代或改变，同时仍然落入以下权利要求所限定的发明范围内。此外，应当理解，本发明可以响应于ESD脉冲的极性和端子的组合而将ESD电流排放至Vss、Vdd或其他合适的端子。在本领域技术人员阅读本说明书之后，其它组合将是明显的。

Claims (20)

1.一种静电放电(ESD)保护电路，其包括：
具有基极、集电极和发射极的双极晶体管；
多个二极管，每个二极管具有耦合到所述基极的第一端子并且具有耦合到所述集电极的第二端子；
第一端子，其连接到所述集电极；和
电源端子，其连接到所述发射极。
2.根据权利要求1所述的电路，其中所述双极晶体管包括并联连接的多个双极晶体管。
3.根据权利要求1所述的电路，其中所述双极晶体管包括多个并联的基极区域和发射极区域。
4.根据权利要求1所述的电路，其中所述多个二极管包括多个并联的基极区域和集电极区域。
5.根据权利要求1所述的电路，其中所述多个二极管中的每个二极管包括阳极和阴极，并且其中每个二极管与至少另一个二极管共享阳极，并且其中每个二极管与至少另一个二极管共享阴极。
6.根据权利要求1所述的电路，其中所述多个二极管确定所述双极晶体管的触发电压。
7.根据权利要求1所述的电路，其中所述发射极被形成在衬底的一面处，并且其中所述多个二极管被形成在所述衬底的所述面处并且围绕所述发射极。
8.根据权利要求1所述的电路，其包括耦合在所述基极和发射极之间的电阻器。
9.一种静电放电保护电路即ESD保护电路，其包括：
半导体受控整流器即SCR，其具有NPN晶体管和PNP晶体管；
多个二极管，每个二极管具有耦合到所述NPN晶体管的基极的第一端子并且具有耦合到所述PNP晶体管的发射极的第二端子；
ESD端子，其连接到所述PNP晶体管的所述发射极；和
电源端子，其连接到所述NPN晶体管的发射极。
10.根据权利要求9所述的电路，其中所述SCR包括并联连接的多个SCR。
11.根据权利要求9所述的电路，其中所述NPN晶体管和PNP晶体管中的每个包括多个并联的基极区域和发射极区域。
12.根据权利要求9所述的电路，其中所述多个二极管包括多个并联的基极区域和集电极区域。
13.根据权利要求9所述的电路，其中所述多个二极管确定所述SCR的触发电压。
14.根据权利要求9所述的电路，其中所述NPN晶体管的发射极被形成在衬底的表面处，并且其中所述多个二极管被形成在所述衬底的所述面处并且围绕所述NPN晶体管的所述发射极。
15.根据权利要求9所述的电路，其包括：
第一电阻器，其耦合在所述PNP晶体管的所述基极和发射极之间；和
第二电阻器，其耦合在所述NPN晶体管的所述基极和发射极之间。
16.根据权利要求15所述的电路，其中所述第一电阻器和第二电阻器确定所述SCR的保持电压。
17.一种对静电放电保护电路即ESD保护电路进行编程的方法，其包括：
形成具有基极、集电极和发射极的第一双极晶体管；
形成多个二极管，每个二级管具有阳极和阴极；
将每个阳极连接到所述基极；
将每个阴极连接到所述集电极；和
将所述阳极和阴极分隔开，以确定所述第一双极晶体管的触发电压。
18.根据权利要求17所述的方法，其包括在所述基极和发射极之间连接电阻器，以确定所述第一双极晶体管的保持电压。
19.根据权利要求17所述的方法，其中所述第一双极晶体管包括多个并联的基极区域和发射极区域，并且其中所述多个二极管包括多个并联的基极区域和集电极区域。
20.根据权利要求17所述的方法，其包括将第二双极晶体管连接到所述第一双极晶体管，以形成半导体受控整流器。
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US9899368B2 (en) 2018-02-20
US20160079228A1 (en) 2016-03-17
CN104952869B (zh) 2019-04-05
US20160079750A1 (en) 2016-03-17
US9831231B2 (en) 2017-11-28
US20150270708A1 (en) 2015-09-24
US20160079227A1 (en) 2016-03-17
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US9231403B2 (en) 2016-01-05

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