CN104952856A - 一种双面组装集成电路 - Google Patents

一种双面组装集成电路 Download PDF

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CN104952856A
CN104952856A CN201510378023.0A CN201510378023A CN104952856A CN 104952856 A CN104952856 A CN 104952856A CN 201510378023 A CN201510378023 A CN 201510378023A CN 104952856 A CN104952856 A CN 104952856A
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substrate
integrated circuit
casing
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draw
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CN104952856B (zh
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夏俊生
李寿胜
候育增
潘大卓
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No 214 Institute of China North Industries Group Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

本发明公开一种双面组装集成电路，包括壳体(1)，壳体(1)底部两侧设有引脚(4)，壳体(1)内设有基板(5)，壳体(1)的顶部设有封装盖板(3)，其特征在于，所述壳体(1)的内壁四周设有台阶(2)，基板(5)的底面四周边缘粘接在所述台阶(2)上，基板(5)将壳体(1)内腔分割为上腔体与下腔体；所述基板(5)的底面四周边缘还设有与台阶(2)形成配合的绝缘层(9)，基板(5)的顶面与底面分别设置电气元件(6)；所述台阶(2)还设有竖直的槽口(8)，槽口(8)将上腔体与下腔体连通；舍弃将基板整个底面与壳体粘接的传统方式，在壳体内壁四周设置台阶，使基板的四周边缘粘接在台阶上，基板的顶面与底面均可以设置组装电气元件，实现双面同时组装，从而极大地提高了基板的利用率，以及集成电路的集成度。

Description

一种双面组装集成电路
技术领域
本发明涉及微电子产品制造领域，具体是一种双面组装集成电路。
背景技术
公知的，微电子技术是实现电子系统小型化、多功能、高可靠的重要途径，近年来在各领域得到了广泛应用。对于混合集成电路，目前一般是在基板的一面组装裸芯片、片式阻容等电气元件，然后将另一面粘接于外壳底座上，仅仅能够实现在基板单面上的组装，基板的组装利用率低，不利于提升电路的集成度。
发明内容
本发明的目的在于提供一种双面组装集成电路，该集成电路能够在基板的双面同时实现元器件组装，提高基板的利用率，以及集成电路的集成度。
本发明解决其技术问题所采用的技术方案是：
一种双面组装集成电路，包括壳体，壳体底部两侧设有引脚，壳体内设有基板，壳体的顶部设有封装盖板；所述壳体的内壁四周设有台阶，基板的底面四周边缘粘接在所述台阶上，基板将壳体内腔分割为上腔体与下腔体；所述基板的底面四周边缘还设有与台阶形成配合的绝缘层，基板的顶面与底面分别设置电气元件；所述台阶还设有竖直的槽口，所述槽口将上腔体与下腔体连通。
进一步的，相对于引脚排列方向垂直的两侧壳体内壁上设有卡槽，卡槽位于台阶上方，卡槽与基板的侧边形成配合。
本发明的有益效果是，舍弃将基板整个底面与壳体粘接的传统方式，在壳体内壁四周设置台阶，使基板的四周边缘粘接在台阶上，基板的顶面与底面均可以设置组装电气元件，实现双面同时组装，从而极大地提高了基板的利用率，以及集成电路的集成度。
附图说明
下面结合附图和实施例对本发明进一步说明：
图1是本发明的结构示意图；
图2是图1中壳体的俯视图；
图3是图1的A-A剖视图；
图4是图2的B-B剖视图；
图5是基板的仰视图。
具体实施方式
结合图1与图2所示，本发明提供一种双面组装集成电路，包括壳体1，壳体1底部两侧分别设有引脚4，壳体1内设有基板5，壳体1的顶部设有封装盖板3；结合图3与图4所示，所述壳体1的内壁四周设有台阶2，基板5的底面四周边缘通过粘接胶7粘接在台阶2上，基板5将壳体1内腔分割为上腔体与下腔体；结合图5所示，基板5的底面四周边缘还设有与台阶2形成配合的绝缘层9，绝缘层9能够防止基板5背面布线与壳体之间出现短路问题，基板5的顶面与底面分别设置电气元件6，基板5采用引线键合实现与引脚4的互连，台阶2还设有竖直的槽口8，所述槽口8将上腔体与下腔体连通。
舍弃将基板整个底面与壳体粘接的传统方式，在壳体内壁四周设置台阶，使基板的四周边缘粘接在台阶上，基板的顶面与底面均可以设置组装电气元件，实现双面同时组装，从而极大地提高了基板的利用率，以及集成电路的集成度。由于在封装后需要对壳体1内腔充满惰性气氛，所以必须使上腔体与下腔体连通才能够保证惰性气氛充满壳体1内腔，对基板的两面电路都起到气氛保护作用，通过在台阶2上设置竖直的槽口就很好的解决了这一问题，上腔体与下腔体通过槽口8相连通。为了提高基板安装的稳定性，相对于引脚排列方向垂直的两侧壳体内壁上设有卡槽10，卡槽10位于台阶2上方，卡槽10与基板5的侧边形成配合，基板5的两条侧边卡在卡槽10内，卡槽在竖直方向对基板形成支撑，使基板安装更牢固。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制；任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同替换、等效变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (2)

1.一种双面组装集成电路，包括壳体(1)，壳体(1)底部两侧设有引脚(4)，壳体(1)内设有基板(5)，壳体(1)的顶部设有封装盖板(3)，其特征在于，所述壳体(1)的内壁四周设有台阶(2)，基板(5)的底面四周边缘粘接在所述台阶(2)上，基板(5)将壳体(1)内腔分割为上腔体与下腔体；所述基板(5)的底面四周边缘还设有与台阶(2)形成配合的绝缘层(9)，基板(5)的顶面与底面分别设置电气元件(6)；所述台阶(2)还设有竖直的槽口(8)，所述槽口(8)将上腔体与下腔体连通。
2.根据权利要求1所述的一种双面组装集成电路，其特征在于，相对于引脚排列方向垂直的两侧壳体内壁上设有卡槽(10)，卡槽(10)位于台阶(2)上方，卡槽(10)与基板(5)的侧边形成配合。
CN201510378023.0A 2015-06-27 2015-06-27 一种双面组装集成电路 Active CN104952856B (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110058116A (zh) * 2019-04-28 2019-07-26 珠海市运泰利自动化设备有限公司 一种连接器pin在内腔的测试机构
CN111399141A (zh) * 2020-05-12 2020-07-10 东莞铭普光磁股份有限公司 一种光器件和光模块

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JPH03248454A (ja) * 1990-02-26 1991-11-06 Nec Corp 混成集積回路装置
US20020079060A1 (en) * 2000-12-25 2002-06-27 Kaneka Corporation Sheet set apparatus for sealing preparation, output lead wire set apparatus for sealing preparation, and sealing preparation apparatus
JP4845090B2 (ja) * 2005-07-28 2011-12-28 オンセミコンダクター・トレーディング・リミテッド 回路装置の製造方法
CN1790606A (zh) * 2005-12-26 2006-06-21 友达光电股份有限公司 平面荧光灯结构
CN101083231A (zh) * 2006-06-01 2007-12-05 美国博通公司 集成电路封装体及其装配方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110058116A (zh) * 2019-04-28 2019-07-26 珠海市运泰利自动化设备有限公司 一种连接器pin在内腔的测试机构
CN111399141A (zh) * 2020-05-12 2020-07-10 东莞铭普光磁股份有限公司 一种光器件和光模块

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