CN102820384B - 发光二极管封装结构的制造方法 - Google Patents
发光二极管封装结构的制造方法 Download PDFInfo
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- CN102820384B CN102820384B CN201110152295.0A CN201110152295A CN102820384B CN 102820384 B CN102820384 B CN 102820384B CN 201110152295 A CN201110152295 A CN 201110152295A CN 102820384 B CN102820384 B CN 102820384B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000005323 electroforming Methods 0.000 claims description 3
- 230000037250 Clearance Effects 0.000 claims description 2
- 230000035512 clearance Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound 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[Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound 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O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000012080 ambient air Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006011 modification reaction Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Abstract
一种发光二极管封装结构的制造方法，包括以下步骤：提供一基板，该基板表面具有多个间隔设置的粗糙区域，该粗糙区域上形成粗糙结构，该基板在多个粗糙区域之外的其它区域形成阻隔层；在该粗糙结构的表面形成金属层作为电极；在该基板上形成反射层，该反射层环绕该金属层形成一凹杯；将发光二极管芯片置于凹杯内并装设于该金属层上，且与该金属层形成电连接；在该凹杯内形成封装层用以密封该发光二极管芯片；将该基板与该金属层和反射层分离。
Description
技术领域
[0001] 本发明涉及一种发光二极管封装结构的制造方法。
背景技术
[0002] 相比于传统的发光源，发光二极管（LightEmittingDiode，LED)具有重量轻、体 积小、污染低、寿命长等优点，其作为一种新型的发光源，已经被越来越多地应用到各领域 当中，如路灯、交通灯、信号灯、射灯及装饰灯等。
[0003] 发光二极管在应用到上述各领域中之前，需要将发光二极管芯片进行封装，以保 护发光二极管芯片，从而获得较高的发光效率及较长的使用寿命。发光二极管封装结构通 常使用基板作为封装衬底，因此其整体厚度因受限于基板的厚度而无法更薄，然而发光二 极管元件趋向于轻、薄的外观，因此其内部的各元件都需要薄型化；另外，该基板一般由散 热性能较差的塑料材料包围其表面，因此不利于高功率发光二极管灯具的散热。
发明内容
[0004] 鉴于此，本发明旨在提供一种厚度更薄且散热良好的发光二极管封装结构的制造 方法。
[0005] 一种发光二极管封装结构的制造方法，包括以下步骤：提供一基板，该基板表面具 有多个间隔设置的粗糙区域，该粗糙区域上形成有粗糙结构，该基板在多个粗糙区域之外 的其它区域形成阻隔层；在该粗糙结构的表面形成金属层作为电极；在该基板上形成反射 层，该反射层环绕该金属层形成一凹杯；将发光二极管芯片置于凹杯内并装设于该金属层 上，且与该金属层形成电连接；在该凹杯内形成封装层用以密封该发光二极管芯片；将该 基板与该金属层和反射层分离。
[0006] 一种发光二极管封装结构的制造方法，包括以下步骤：提供一板体；在该板体表 面形成若干个凸起，该若干个凸起间隔设置，且该基板表面其它区域向下凹陷形成凹槽；在 凹槽内设置阻隔层，该阻隔层为非导电性材料组成；在该若干个凸起的表面形成粗糙结构； 在该粗糙结构的表面形成金属层作为电极；在该板体上形成反射层，该反射层环绕该金属 层且形成一凹杯；将发光二极管芯片置于凹杯内并装设于金属层上，且与两金属层形成的 电极电连接；在该凹杯内形成封装层用以密封该发光二极管芯片；将该板体与该金属层和 反射层分离。
[0007] 本发明通过提供一基板，并在基板表面形成粗糙结构，从而降低基板与金属层间 的接触面积以分离基板与金属层，使完成封装后的发光二极管封装结构无基板存在，从而 使发光二极管封装结构更为轻薄；且由于发光二极管芯片直接固定于金属层上，故在工作 过程中发光二极管芯片产生的热量可通过金属层直接散发至周围的空气中，且金属层因无 基板阻隔而直接暴露在发光二极管封装结构之外，散热效果更好，提高发光二极管封装结 构的使用寿命。
附图说明
[0008] 图1为本发明的发光二极管封装结构的制造方法步骤一所得到的封装结构的剖 面示意图。
[0009] 图2为本发明的发光二极管封装结构的制造方法步骤一所得到的封装结构的俯 视示意图。
[0010] 图3为本发明的发光二极管封装结构的制造方法步骤二所得到的封装结构的剖 面示意图。
[0011] 图4为本发明的发光二极管封装结构的制造方法步骤三所得到的封装结构的剖 面示意图。
[0012] 图5为本发明的发光二极管封装结构的制造方法步骤三所得到的封装结构的俯 视示意图。
[0013] 图6为本发明的发光二极管封装结构的制造方法步骤四所得到的封装结构的剖 面示意图。
[0014] 图7为本发明的发光二极管封装结构的制造方法步骤五所得到的封装结构的剖 面示意图。
[0015] 图8为本发明的发光二极管封装结构的制造方法步骤六所得到的封装结构的剖 面示意图。
[0016] 图9为本发明的发光二极管封装结构的制造方法步骤七所得到的封装结构的剖 面示意图。
[0017] 图10为本发明的发光二极管封装结构的制造方法步骤八所得到的封装结构的剖 面示意图。
[0018] 图11为本发明中基板的制造方法步骤一所得到的基板的剖面示意图。
[0019] 图12为本发明中基板的制造方法步骤二所得到的基板的剖面示意图。
[0020] 图13为本发明中基板的制造方法步骤三所得到的基板的剖面示意图。
[0021] 图14为本发明中基板的制造方法步骤四所得到的基板的剖面示意图。
[0022] 主要元件符号说明
[0023]
[0024] 如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
[0025] 如图10所示，本发明无基板的发光二极管封装结构1包括两个作为电极的金属层 20,装设于其中一个金属层20上且与两个金属层20电连接的发光二极管芯片40,围设发光 二极管芯片40的反射层30,以及密封发光二极管芯片40的封装层60。
[0026] 本发明还提供上述无基板的发光二极管封装结构1的制造方法，以下，将结合其 他附图对该制造方法进行详细说明。
[0027] 请参阅图1和图2,提供一个基板10,基板10表面具有多个间隔设置的粗糙区域 用以形成多个粗糙结构11，该表面上在多个粗糙结构11之外的其它区域形成阻隔层12。 在本实施例中，粗糙结构11和阻隔层12的上表面平齐，粗糙结构11包含多个间隔排列的 凹坑111，该多个凹坑111的排列方式可根据实际需要进行设计，其内可包含非导电性的材 料，如二氧化硅。粗糙结构11可利用电铸、印刷或显影的方式形成。阻隔层12为非导电性 材料组成，如二氧化硅。
[0028] 请参阅图3,多个金属层20对应形成在基板10的多个粗糙结构11上，每个金属 层20与阻隔层12相邻，即，相邻的两个金属层20间通过阻隔层12相隔。本实施例中，金 属层20是通过电镀的方式形成在该多个粗糙结构11上的。
[0029] 请同时参阅图4和图5,在基板10上形成反射层30,反射层30环绕每相邻的两金 属层20四围，且于相邻的两金属层20处形成一凹杯31。于本实施例中，凹杯31大致呈倒 立的圆台状，金属层20位于凹杯31的底部。当然，凹杯31也可为其他形状。
[0030] 请参阅图6,在凹杯31内的金属层20上固定至少一个发光二极管芯片40,并且通 过打导线50的方式将该至少一个发光二极管芯片40与相邻的两金属层20分别电连接。在 其他实施例中，该至少一个发光二极管芯片40也可以利用覆晶或共金的方式与金属层20 结合。该两金属层20作为发光二极管封装结构1的电极以与外部电源如电路板连接而向 该至少一个发光二极管芯片40供电。
[0031] 请参阅图7,形成多个封装层60分别覆盖发光二极管芯片40。本实施例中，封装 层60填充整个凹杯31。封装层60是采用点胶工艺完成，先在反射层30所包围的空间内利 用点胶机点上封装胶，使封装胶覆盖若干个发光二极管芯片40并填满反射层30所包围的 整个区域，然后用模具挤压使封装层60的上端与反射层30的上端平齐。于本实施例中，可 在准备封装胶时混合荧光粉，或者在封装完成后，于封装层60的上表面涂覆一层荧光层， 以获得想要的出光颜色。
[0032] 请参阅图8,通过机械方式将基板10与金属层20、反射层30分离，由于基板10的 阻隔层12与反射层30之间的结合力较小，且基板10由于设置了粗糙结构11与金属层20 之间的结合力也较小，故可通过拨离的方式进行分离。分离下来的基板10可重复使用。
[0033] 请参阅图9,对分离下来的多个发光二极管封装结构进行切割，可得到单个无基板 的发光二极管封装结构1，如图10所示，每个无基板的发光二极管封装结构1包含至少一发 光二极管芯片40。
[0034] 本发明通过提供一基板10,并在基板10表面形成有粗糙结构11，从而降低基板10 与金属层20间的接触面积以分离基板10与金属层20,使完成封装后的发光二极管封装结 构1无基板存在，从而使发光二极管封装结构1更为轻薄；且由于发光二极管芯片40直 接固定于金属层20上，故在工作过程中发光二极管芯片40产生的热量可通过金属层20直 接散发至周围的空气中，且金属层20因无基板阻隔而直接暴露在发光二极管封装结构1之 外，散热效果更好，提高发光二极管封装结构1的使用寿命。
[0035] 以下，将结合附图11至14对本发明实施例提供的基板10的制造方法进行详细说 明。
[0036] 提供一个金属板体70 ;
[0037] 在板体70的上表面形成多个凸起71，该多个凸起71用以形成隔离层。该多个凸 起71间隔设置，且板体70上的其它区域相对该多个凸起71向下形成凹槽72。该多个凸 起71可通过微影或压合的技术形成的，且该多个凸起71形成于板体70的中部，且均成小 长方体结构；
[0038] 在凹槽72内设置阻隔层73,阻隔层73的高度与该多个凸起71的高度相等，从而 使阻隔层73的上表面与该多个凸起71的上表面平齐。阻隔层73为非导电性材料组成，如 二氧化硅等；
[0039] 在该多个凸起71上形成粗糙结构74,粗糙结构74包含多个间隔排列的凹坑741， 该多个凹坑741的排列方式不限定，其内包含有非导电性的材料，如二氧化硅等，粗糙结构 74可利用电铸、印刷或显影的方式形成。
[0040] 通过以上方法，即可得到基板10。当然，基板10的制造方法并不限定，也可以通过 其它方式形成。
[0041] 本发明的技术内容及技术特点已揭露如上，然而本领域技术人员仍可能基于本发 明的教示及揭示而作出种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应 不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为所附的权利 要求所涵盖。
Claims (10)
1. 一种发光二极管封装结构的制造方法，包括以下步骤： 提供一基板，该基板表面具有多个间隔设置的粗糙区域，该粗糙区域上形成粗糙结构， 该基板在多个粗糙区域之外的其它区域形成阻隔层，该阻隔层为一完整的、非导电性材料 组成的片体； 在该粗糙结构的表面形成金属层作为电极； 在该基板的阻隔层上形成反射层，该反射层环绕该金属层形成一凹杯；上 将发光二极管芯片置于凹杯内并装设于该金属层上，且与该金属层形成电连接； 在该凹杯内形成封装层用以密封该发光二极管芯片； 将该基板与该金属层和反射层分离。
2. 如权利要求1所述的发光二极管封装结构的制造方法，其特征在于：在该基板与该 金属层和反射层分离后，还对所形成的多个发光二极管封装结构进行切割，得到单个发光 二极管封装结构，每个发光二极管封装结构包含至少一发光二极管芯片。
3. 如权利要求1所述的发光二极管封装结构的制造方法，其特征在于：该粗糙结构包 括若干个间隔设置的凹坑。
4. 如权利要求3所述的发光二极管封装结构的制造方法，其特征在于：该凹坑内包含 非导电性的材料。
5. 如权利要求1所述的发光二极管封装结构的制造方法，其特征在于：该粗糙结构利 用电铸、印刷或显影的方式形成。
6. 如权利要求1所述的发光二极管封装结构的制造方法，其特征在于：该金属层通过 电镀的方式形成于该粗糙结构上。
7. 如权利要求1所述的发光二极管封装结构的制造方法，其特征在于：该发光二极管 芯片利用覆晶、共金或固晶打线的方式与该金属层电连接。
8. -种发光二极管封装结构的制造方法，包括以下步骤： 提供一板体； 在该板体表面形成若干个凸起，该若干个凸起间隔设置，且该板体表面其它区域向下 凹陷形成凹槽； 在凹槽内设置阻隔层，该阻隔层为一完整的、非导电性材料组成的片体； 在该若干个凸起的表面形成粗糙结构； 在该粗糙结构的表面形成金属层作为电极； 在该板体的阻隔层上形成反射层，该反射层环绕该金属层且形成一凹杯； 将发光二极管芯片置于凹杯内并装设于金属层上，且与两金属层形成的电极电连接； 在该凹杯内形成封装层用以密封该发光二极管芯片； 将该板体与该金属层和反射层分离。
9. 如权利要求8所述的发光二极管封装结构的制造方法，其特征在于：在该板体与该 金属层和反射层分离后，还对所形成的多个发光二极管封装结构进行切割，得到单个发光 二极管封装结构，每个发光二极管封装结构包含至少一发光二极管芯片。
10. 如权利要求8所述的发光二极管封装结构的制造方法，其特征在于：该若干个凸起 和凹槽是利用微影或压合的技术形成的。
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